mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-08-16 13:11:13 -07:00
parent d97e4e1dd0
commit c08351f4d3
108 changed files with 98 additions and 94 deletions

View File

@@ -37,7 +37,7 @@
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "mem/protocol/InvalidateGeneratorStatus.hh"
#include "mem/ruby/protocol/InvalidateGeneratorStatus.hh"
#include "params/InvalidateGenerator.hh"
class InvalidateGenerator : public DirectedGenerator

View File

@@ -37,7 +37,7 @@
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "mem/protocol/SeriesRequestGeneratorStatus.hh"
#include "mem/ruby/protocol/SeriesRequestGeneratorStatus.hh"
#include "params/SeriesRequestGenerator.hh"
class SeriesRequestGenerator : public DirectedGenerator

View File

@@ -33,9 +33,9 @@
#include <iostream>
#include "cpu/testers/rubytest/RubyTester.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/TesterStatus.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/TesterStatus.hh"
class SubBlock;

View File

@@ -482,7 +482,7 @@ machine(MachineType:L1Cache, "MSI cache")
// across different directories, so query the network.
out_msg.Destination.add(mapAddressToMachine(address,
MachineType:Directory));
// See mem/protocol/RubySlicc_Exports.sm for possible sizes.
// See mem/ruby/protocol/RubySlicc_Exports.sm for possible sizes.
out_msg.MessageSize := MessageSizeType:Control;
// Set that the reqeustor is this machine so we get the response.
out_msg.Requestor := machineID;

View File

@@ -1,6 +1,6 @@
Import('*')
# NOTE: All SLICC setup code found in src/mem/protocol/SConscript
# NOTE: All SLICC setup code found in src/mem/ruby/protocol/SConscript
# Register this protocol with gem5/SCons
all_protocols.extend([

View File

@@ -98,7 +98,7 @@ def do_embed_text(target, source, env):
#
# Link includes
#
generated_dir = Dir('../protocol')
generated_dir = Dir('protocol')
def MakeIncludeAction(target, source, env):
f = file(str(target[0]), 'w')
@@ -138,9 +138,9 @@ MakeInclude('structures/WireBuffer.hh')
MakeInclude('system/DMASequencer.hh')
MakeInclude('system/Sequencer.hh')
# External types : Group "mem/protocol" : include "header.hh" to the bottom
# of this MakeIncludes if it is referenced as
# <# include "mem/protocol/header.hh"> in any file
# generated_dir = Dir('../protocol')
# External types : Group "mem/ruby/protocol" : include "header.hh" to the
# bottom of this MakeIncludes if it is referenced as
# <# include "mem/ruby/protocol/header.hh"> in any file
# generated_dir = Dir('protocol')
MakeInclude('system/GPUCoalescer.hh')
MakeInclude('system/VIPERCoalescer.hh')

View File

@@ -33,7 +33,7 @@
#include <string>
#include "base/cprintf.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/protocol/MachineType.hh"
struct MachineID
{

View File

@@ -61,12 +61,12 @@
#include "base/types.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/protocol/LinkDirection.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/network/Topology.hh"
#include "mem/ruby/network/dummy_port.hh"
#include "mem/ruby/protocol/LinkDirection.hh"
#include "mem/ruby/protocol/MessageSizeType.hh"
#include "params/RubyNetwork.hh"
#include "sim/clocked_object.hh"

View File

@@ -44,9 +44,9 @@
#include <string>
#include <vector>
#include "mem/protocol/LinkDirection.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/network/BasicLink.hh"
#include "mem/ruby/protocol/LinkDirection.hh"
class NetDest;
class Network;

View File

@@ -43,9 +43,9 @@
#include <vector>
#include "mem/packet.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/network/BasicRouter.hh"
#include "mem/ruby/protocol/MessageSizeType.hh"
#include "params/Switch.hh"
class MessageBuffer;

View File

@@ -31,10 +31,10 @@
#include <iostream>
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Set.hh"
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
class Histogram;

View File

@@ -31,8 +31,8 @@
#include <vector>
#include "base/stl_helpers.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
using namespace std;
typedef AddressProfiler::AddressMap AddressMap;

View File

@@ -32,12 +32,12 @@
#include <iostream>
#include <unordered_map>
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Histogram.hh"
#include "mem/ruby/profiler/AccessTraceForAddress.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/protocol/AccessType.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
class Set;

View File

@@ -52,10 +52,10 @@
#include "base/stl_helpers.hh"
#include "base/str.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/profiler/AddressProfiler.hh"
#include "mem/ruby/protocol/MachineType.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
/**
* the profiler uses GPUCoalescer code even
@@ -72,6 +72,7 @@
*/
#ifdef BUILD_GPU
#include "mem/ruby/system/GPUCoalescer.hh"
#endif
#include "mem/ruby/system/Sequencer.hh"

View File

@@ -51,11 +51,11 @@
#include "base/callback.hh"
#include "base/statistics.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/protocol/AccessType.hh"
#include "mem/ruby/protocol/PrefetchBit.hh"
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
#include "params/RubySystem.hh"
class RubyRequest;

View File

@@ -47,7 +47,7 @@ output_dir = Dir('.')
html_dir = Dir('html')
slicc_dir = Dir('../slicc')
sys.path[1:1] = [ Dir('..').srcnode().abspath ]
sys.path[1:1] = [ Dir('..').Dir('..').srcnode().abspath ]
from slicc.parser import SLICC
slicc_depends = []

View File

@@ -36,8 +36,8 @@
#include <iostream>
#include "base/logging.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
class DataBlock;

View File

@@ -41,8 +41,8 @@
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "debug/RubyQueue.hh"
#include "mem/protocol/MemoryMsg.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/protocol/MemoryMsg.hh"
#include "mem/ruby/system/GPUCoalescer.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/Sequencer.hh"

View File

@@ -48,7 +48,6 @@
#include "base/addr_range.hh"
#include "base/callback.hh"
#include "mem/packet.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/qport.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
@@ -56,6 +55,7 @@
#include "mem/ruby/common/Histogram.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "params/RubyController.hh"
#include "sim/clocked_object.hh"

View File

@@ -31,7 +31,7 @@
#include <iostream>
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
class AbstractEntry
{

View File

@@ -34,8 +34,8 @@
#include <stack>
#include "mem/packet.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/protocol/MessageSizeType.hh"
class Message;
typedef std::shared_ptr<Message> MsgPtr;

View File

@@ -32,15 +32,15 @@
#include <ostream>
#include <vector>
#include "mem/protocol/HSAScope.hh"
#include "mem/protocol/HSASegment.hh"
#include "mem/protocol/Message.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/WriteMask.hh"
#include "mem/ruby/protocol/HSAScope.hh"
#include "mem/ruby/protocol/HSASegment.hh"
#include "mem/ruby/protocol/Message.hh"
#include "mem/ruby/protocol/PrefetchBit.hh"
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
class RubyRequest : public Message
{

View File

@@ -29,10 +29,10 @@
#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
#define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/protocol/MachineType.hh"
#include "mem/ruby/structures/DirectoryMemory.hh"
inline NetDest

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@@ -35,7 +35,7 @@
#include "debug/RubyCacheTrace.hh"
#include "debug/RubyResourceStalls.hh"
#include "debug/RubyStats.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/WeightedLRUPolicy.hh"

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@@ -35,10 +35,10 @@
#include <vector>
#include "base/statistics.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/CacheResourceType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/protocol/CacheRequestType.hh"
#include "mem/ruby/protocol/CacheResourceType.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"

View File

@@ -45,8 +45,8 @@
#include <string>
#include "base/addr_range.hh"
#include "mem/protocol/DirectoryRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/protocol/DirectoryRequestType.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "params/RubyDirectoryMemory.hh"
#include "sim/sim_object.hh"

View File

@@ -31,8 +31,8 @@
#include <unordered_map>
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
template<class ENTRY>
struct PerfectCacheLineState

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@@ -32,10 +32,10 @@
#include <iostream>
#include <unordered_map>
#include "mem/protocol/AccessType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/protocol/AccessType.hh"
class PersistentTableEntry
{

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@@ -38,10 +38,10 @@
#include <vector>
#include "base/types.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
class Sequencer;

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@@ -32,8 +32,8 @@
#include "debug/RubyDma.hh"
#include "debug/RubyStats.hh"
#include "mem/protocol/SequencerMsg.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/protocol/SequencerMsg.hh"
#include "mem/ruby/protocol/SequencerRequestType.hh"
#include "mem/ruby/system/RubySystem.hh"
DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,

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@@ -33,9 +33,9 @@
#include <ostream>
#include <unordered_map>
#include "mem/protocol/DMASequencerRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/protocol/DMASequencerRequestType.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "params/DMASequencer.hh"

View File

@@ -40,15 +40,15 @@
#include <unordered_map>
#include "base/statistics.hh"
#include "mem/protocol/HSAScope.hh"
#include "mem/protocol/HSASegment.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/request.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/protocol/HSAScope.hh"
#include "mem/ruby/protocol/HSASegment.hh"
#include "mem/ruby/protocol/PrefetchBit.hh"
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
#include "mem/ruby/protocol/SequencerRequestType.hh"
#include "mem/ruby/system/Sequencer.hh"
class DataBlock;

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@@ -45,7 +45,7 @@
#include "debug/Config.hh"
#include "debug/Drain.hh"
#include "debug/Ruby.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/simple_mem.hh"
#include "sim/full_system.hh"

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