This patch adds the uret, sret, and mret instructions for use with
returning from user-, supervisor-, and machine-level code, respectively.
These instructions read the STATUS register to determine the previous
privilege level and modify it to re-enable interrupts at the old
privilege level. These instructions can only be executed at the
corresponding privilege level or higher.
Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9
Reviewed-on: https://gem5-review.googlesource.com/11136
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de>
RISC-V has a set of CSRs that contain information about a trap that was
taken into each privilegel level, such as illegal instruction bytes or
faulting address. This patch adds that register, modifies existing
faults to make use of it, and adds a new fault for future use with
handling page faults and bad addresses.
Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551
Reviewed-on: https://gem5-review.googlesource.com/11135
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
This patch adds support for handling RISC-V faults, including tracking
current and previous execution privilege, correctly switching to
the privilege mode specified by CSRs, and setting/storing the PC. It
also includes changes introduced by patch #9821, which disables
interrupts during handling of a fault.
Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9
Reviewed-on: https://gem5-review.googlesource.com/9161
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
ucontext functions (like getcontext, setcontext etc) have been marked
as deprecated and are hence hidden in latest macOS releases.
This patch uncovers them; warnings wil be produced but compilation
won't fail since -Wno-error=deprecated-declarations flag is currently
used.
Change-Id: Ic10e6f77a38875828b1891eaed2f0626ecffff67
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11729
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.
Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This change is because I want to make CacheBlk::data private, so that
I can track all the places which write to it. But to keep that commit
smaller (it is pretty big, because of all the places which might
change it), I have split this into a commit of its own.
Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea
Reviewed-on: https://gem5-review.googlesource.com/11829
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
These are the header files as defined by the standard, although some
predefined channel types and most of the sc_dt namespace have yet to be
stubbed out, and so those portions are excluded.
Change-Id: Ic70f887c06e591974a4265c820eb0fdfa740d19a
Reviewed-on: https://gem5-review.googlesource.com/10838
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Most (but not all) of the SystemC headers are part of the "external"
interface that an existing, standard compliant module would include
through <systemc.h> or <systemc>. Since those follow slightly different
rules (relative includes, no gem5 includes), this change separates them
out so that they're easier to identify.
Also, this change moves the other files into a "core" subdirectory,
with the intention to add a "dt", aka data type, directory some time in
the future when those standard defined types are implemented.
Change-Id: Ida63f9cc0bc0431024d4dd691cc5b22b944a99a8
Reviewed-on: https://gem5-review.googlesource.com/10835
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Free the squahsed instructions' heads of DepGraph in IQ squashing
In a system with large register file (ex.2048), the number of
DynInst hits the hardcoded limit (1500). This is caused by
missing freeing the heads of DepGraph in IQ. IQ only clears
out the heads when instructions reach writeback stage.
If a instruction is squashed before writeback stage, its head of
dependency graph, which holds the instruction's DynInstPtr,
would not be cleared out. This prevents freeing the DynInst of the
squahsed instruction even after it is committed.
Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3
Reviewed-on: https://gem5-review.googlesource.com/7481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
sc_main is exported as a python method on the SystemC_Kernel class and
takes a series of string arguments. The internal c++ implementation
converts those arguments into the standard argc and argv and uses them
to call the standard SystemC version of that function.
A weak SystemC version of sc_main is provided so that systemc will
compile with or without a simulation provided version of that
function. The weak version just complains and dies.
Change-Id: Iad735536c37c8bc85d06cf24779f607ae4309b8b
Reviewed-on: https://gem5-review.googlesource.com/10824
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
This class is mostly implemented as defined by the spec, except that
it doesn't maintain the module name stack (which doesn't yet exist).
Change-Id: I05fdc4aa40fb0497b0165824baee87ebf01a7821
Reviewed-on: https://gem5-review.googlesource.com/10823
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are
- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional
Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
To avoid unintentional variable capture, all std calls must be
prefixed. These are the identifiers which are in the std
namespace (according to
https://en.cppreference.com/w/cpp/symbol_index), but that will remain
unprefixed with this change:
int8_t int16_t int32_t int64_t
uint8_t uint16_t uint32_t uint64_t
The (u)int types are included from the packet header file, which
includes <inttypes.h>, where they occur in the global namespace. They
are in the std namespace in <cinttypes>/<cstdint>.
There is an occurrence of "set" in this file, which is "Packet::set"
and not "std::set", so it is not prefixed with the std namespace
Change-Id: I7f6c0b61b09658e224fe31a9f73150b81861d6f8
Reviewed-on: https://gem5-review.googlesource.com/11809
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
There was an off-by-one error in the isRead() case, as `val_end` and
`func_end` pointed to the last byte to write to (not one past the last
byte), and thus `*_end - *_start` was not the length of the data to
memcpy.
This was correct in the case of
val_start >= func_start && val_end <= func_end
where `overlap_size = size`, but if it were (as the other cases
suggest) `overlap_size = val_end - val_start`, then it would also be
off by one.
Also, the isWrite() case catered for this.
I simplified the four ifs into one case which uses min/max (this is
how I spotted the inconsistency).
Change-Id: Ib5c5da084652e752f6baf1eec56b51b4f0f5c95c
Reviewed-on: https://gem5-review.googlesource.com/11750
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
The current traffic generator relies on a configuration file that
describes a small machine to generate stimuli. This configuration file
is usually generated by the gem5 Python configuration. This creates an
unnecessary and fragile step.
This changeset introduces a Python-based trace module. When
instantiated, the module exposes a start method that takes an iterable
object as a parameter (e.g., a generator). The iterable object is
expected to represent a list of generators that will be run one after
the other. For example:
system.tgen = PyTrafficGen()
m5.instantiate()
def trace():
yield system.tgen.createIdle(1000)
yield system.tgen.createExit(0)
system.tgen.start(trace())
Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11518
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Make the BaseTrafficGen handle cases where getNextPacket() can't find
a new packet and returns NULL. In that case, assume the generator has
run out of packets and switch to the next generator.
Change-Id: I5ca6ead550005812fb849ed9ce6b5007a65ddfa7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11517
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The traffic generator currently assumes that it is always driven from
a configuration file. Split it into a base class (BaseTrafficGen) that
handles basic packet generation and a derived class that implements
the config handling (TrafficGen).
Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11515
Doxygen was stopping with #include "arch/null/cpu_dummy.hh" so the html
for BaseCPU was only the three functions defined in the dummy CPU. This
forces doxygen to skip this #include correctly.
Note: The file references for base_cpu still aren't quite right, but it's
better than it was.
Change-Id: Ifafe247df2511caee2569d534bd29348a5ce9e8e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11649
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.
Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
There are cases where we need to limit the symbol visibility to avoid
compilation errors. This is a problem for Python code that relies on
PyBind11 since recent versions enforce hidden symbols. As a
consequence, classes that have member variables from PyBind11 need to
be declared with the hidden attribute (or gem5 needs to be compiled
with -fvisibility=hidden).
Change-Id: I30e582fde494ff61ab7a596a595efc26a2952a5f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11513
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:
* delayReq(pkt)
* delayResp(pkt)
* delaySnoopResp(pkt)
These methods should be specialized to implement delays for specific
packet types.
The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.
The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.
Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
