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arch-arm: Introduce RAS System Registers

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Adding RAS Extension System Registers into the decode tree.  They are
currently unimplemented and produce a warning (not failure) if accessed.

Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11591
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-05-14 14:45:42 +01:00
parent a1b759a29b
commit cb09573e52
2 changed files with 98 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

73
src/arch/arm/miscregs.cc
View File

@@ -1857,6 +1857,34 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
return MISCREG_ESR_EL1;
}
break;
case 3:
switch (op2) {
case 0:
return MISCREG_ERRIDR_EL1;
case 1:
return MISCREG_ERRSELR_EL1;
}
break;
case 4:
switch (op2) {
case 0:
return MISCREG_ERXFR_EL1;
case 1:
return MISCREG_ERXCTLR_EL1;
case 2:
return MISCREG_ERXSTATUS_EL1;
case 3:
return MISCREG_ERXADDR_EL1;
}
break;
case 5:
switch (op2) {
case 0:
return MISCREG_ERXMISC0_EL1;
case 1:
return MISCREG_ERXMISC1_EL1;
}
break;
}
break;
case 4:
@@ -1879,6 +1907,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
switch (op2) {
case 0:
return MISCREG_ESR_EL2;
case 3:
return MISCREG_VSESR_EL2;
}
break;
case 3:
@@ -2104,6 +2134,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
switch (op2) {
case 0:
return MISCREG_ISR_EL1;
case 1:
return MISCREG_DISR_EL1;
}
break;
}
@@ -2118,6 +2150,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
return MISCREG_RVBAR_EL2;
}
break;
case 1:
switch (op2) {
case 1:
return MISCREG_VDISR_EL2;
}
break;
}
break;
case 6:
@@ -3997,6 +4035,41 @@ ISA::initializeMiscRegMetadata()
.unimplemented()
.warnNotFail(impdefAsNop);
// RAS extension (unimplemented)
InitReg(MISCREG_ERRIDR_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERRSELR_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERXFR_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERXCTLR_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERXSTATUS_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERXADDR_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERXMISC0_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_ERXMISC1_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_DISR_EL1)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_VSESR_EL2)
.unimplemented()
.warnNotFail();
InitReg(MISCREG_VDISR_EL2)
.unimplemented()
.warnNotFail();
// Register mappings for some unimplemented registers:
// ESR_EL1 -> DFSR
// RMR_EL1 -> RMR

26
src/arch/arm/miscregs.hh
View File

@@ -696,6 +696,19 @@ namespace ArmISA
// either UNDEFINED or hypervisor trap exception.
MISCREG_IMPDEF_UNIMPL,
// RAS extension (unimplemented)
MISCREG_ERRIDR_EL1,
MISCREG_ERRSELR_EL1,
MISCREG_ERXFR_EL1,
MISCREG_ERXCTLR_EL1,
MISCREG_ERXSTATUS_EL1,
MISCREG_ERXADDR_EL1,
MISCREG_ERXMISC0_EL1,
MISCREG_ERXMISC1_EL1,
MISCREG_DISR_EL1,
MISCREG_VSESR_EL2,
MISCREG_VDISR_EL2,
// Total number of Misc Registers: Physical + Dummy
NUM_MISCREGS
};
@@ -1386,7 +1399,18 @@ namespace ArmISA
"cp14_unimpl",
"cp15_unimpl",
"unknown",
"impl_defined"
"impl_defined",
"erridr_el1",
"errselr_el1",
"erxfr_el1",
"erxctlr_el1",
"erxstatus_el1",
"erxaddr_el1",
"erxmisc0_el1",
"erxmisc1_el1",
"disr_el1",
"vsesr_el2",
"vdisr_el2",
};
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,