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arch-riscv: Fix the srlw and srliw instructions.

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Change-Id: I14ccb0655819887db2306fee1188e1c83a991743
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/11669
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
This commit is contained in:
Austin Harris
2018-07-07 15:43:27 -05:00
committed by Austin Harris
parent 0ee4a54364
commit 98cbcbb54f
1 changed files with 2 additions and 2 deletions
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4
src/arch/riscv/isa/decoder.isa
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@@ -447,7 +447,7 @@ decode QUADRANT default Unknown::unknown() {
}});
0x5: decode SRTYPE {
0x0: srliw({{
Rd = Rs1_uw >> SHAMT5;
Rd_sd = (int32_t)(Rs1_uw >> SHAMT5);
}});
0x1: sraiw({{
Rd_sd = Rs1_sw >> SHAMT5;
@@ -759,7 +759,7 @@ decode QUADRANT default Unknown::unknown() {
}}, IntDivOp);
0x5: decode FUNCT7 {
0x0: srlw({{
Rd_uw = Rs1_uw >> Rs2<4:0>;
Rd_sd = (int32_t)(Rs1_uw >> Rs2<4:0>);
}});
0x1: divuw({{
if (Rs2_uw == 0) {