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cpu: Allow creation of traffic gen from generic SimObjects

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This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.

Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-07-18 14:28:21 +01:00
parent 2fe3d66026
commit a327a6763a
11 changed files with 78 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/cpu/testers/traffic_gen/base.cc
View File

@@ -320,13 +320,13 @@ BaseTrafficGen::regStats()
std::shared_ptr<BaseGen>
BaseTrafficGen::createIdle(Tick duration)
{
return std::shared_ptr<BaseGen>(new IdleGen(*this, duration));
return std::shared_ptr<BaseGen>(new IdleGen(*this, masterID, duration));
}
std::shared_ptr<BaseGen>
BaseTrafficGen::createExit(Tick duration)
{
return std::shared_ptr<BaseGen>(new ExitGen(*this, duration));
return std::shared_ptr<BaseGen>(new ExitGen(*this, masterID, duration));
}
std::shared_ptr<BaseGen>
@@ -335,9 +335,10 @@ BaseTrafficGen::createLinear(Tick duration,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
{
return std::shared_ptr<BaseGen>(new LinearGen(*this,
return std::shared_ptr<BaseGen>(new LinearGen(*this, masterID,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
min_period, max_period,
read_percent, data_limit));
}
@@ -348,9 +349,10 @@ BaseTrafficGen::createRandom(Tick duration,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
{
return std::shared_ptr<BaseGen>(new RandomGen(*this,
return std::shared_ptr<BaseGen>(new RandomGen(*this, masterID,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
min_period, max_period,
read_percent, data_limit));
}
@@ -366,9 +368,10 @@ BaseTrafficGen::createDram(Tick duration,
unsigned int addr_mapping,
unsigned int nbr_of_ranks)
{
return std::shared_ptr<BaseGen>(new DramGen(*this,
return std::shared_ptr<BaseGen>(new DramGen(*this, masterID,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
min_period, max_period,
read_percent, data_limit,
num_seq_pkts, page_size,
@@ -391,9 +394,10 @@ BaseTrafficGen::createDramRot(Tick duration,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
{
return std::shared_ptr<BaseGen>(new DramRotGen(*this,
return std::shared_ptr<BaseGen>(new DramRotGen(*this, masterID,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
min_period, max_period,
read_percent, data_limit,
num_seq_pkts, page_size,
@@ -410,7 +414,7 @@ BaseTrafficGen::createTrace(Tick duration,
{
#if HAVE_PROTOBUF
return std::shared_ptr<BaseGen>(
new TraceGen(*this, duration, trace_file, addr_offset));
new TraceGen(*this, masterID, duration, trace_file, addr_offset));
#else
panic("Can't instantiate trace generation without Protobuf support!\n");
#endif

20
src/cpu/testers/traffic_gen/base_gen.cc
View File

@@ -51,9 +51,8 @@
#include "debug/TrafficGen.hh"
#include "sim/system.hh"
BaseGen::BaseGen(BaseTrafficGen &gen, Tick _duration)
: _name(gen.name()), masterID(gen.masterID),
cacheLineSize(gen.system->cacheLineSize()),
BaseGen::BaseGen(SimObject &obj, MasterID master_id, Tick _duration)
: _name(obj.name()), masterID(master_id),
duration(_duration)
{
}
@@ -81,16 +80,17 @@ BaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd,
return pkt;
}
StochasticGen::StochasticGen(BaseTrafficGen &gen,
Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
StochasticGen::StochasticGen(SimObject &obj,
MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
: BaseGen(gen, _duration),
: BaseGen(obj, master_id, _duration),
startAddr(start_addr), endAddr(end_addr),
blocksize(_blocksize), minPeriod(min_period),
maxPeriod(max_period), readPercent(read_percent),
dataLimit(data_limit)
blocksize(_blocksize), cacheLineSize(cacheline_size),
minPeriod(min_period), maxPeriod(max_period),
readPercent(read_percent), dataLimit(data_limit)
{
if (blocksize > cacheLineSize)
fatal("TrafficGen %s block size (%d) is larger than "

16
src/cpu/testers/traffic_gen/base_gen.hh
View File

@@ -70,9 +70,6 @@ class BaseGen
/** The MasterID used for generating requests */
const MasterID masterID;
/** Cache line size in the simulated system */
const Addr cacheLineSize;
/**
* Generate a new request and associated packet
*
@@ -92,11 +89,11 @@ class BaseGen
/**
* Create a base generator.
*
* @param _name Name to use for status and debug
* @param obj simobject owning the generator
* @param master_id MasterID set on each request
* @param _duration duration of this state before transitioning
*/
BaseGen(BaseTrafficGen &gen, Tick _duration);
BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
virtual ~BaseGen() { }
@@ -140,8 +137,10 @@ class BaseGen
class StochasticGen : public BaseGen
{
public:
StochasticGen(BaseTrafficGen &gen, Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
StochasticGen(SimObject &obj,
MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit);
@@ -155,6 +154,9 @@ class StochasticGen : public BaseGen
/** Blocksize and address increment */
const Addr blocksize;
/** Cache line size in the simulated system */
const Addr cacheLineSize;
/** Request generation period */
const Tick minPeriod;
const Tick maxPeriod;

11
src/cpu/testers/traffic_gen/dram_gen.cc
View File

@@ -49,8 +49,10 @@
#include "debug/TrafficGen.hh"
DramGen::DramGen(BaseTrafficGen &gen, Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
DramGen::DramGen(SimObject &obj,
MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
@@ -58,8 +60,9 @@ DramGen::DramGen(BaseTrafficGen &gen, Tick _duration,
unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
unsigned int nbr_of_ranks)
: RandomGen(gen, _duration, start_addr, end_addr,
_blocksize, min_period, max_period, read_percent, data_limit),
: RandomGen(obj, master_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
isRead(true), pageSize(page_size),
pageBits(floorLog2(page_size / _blocksize)),

10
src/cpu/testers/traffic_gen/dram_gen.hh
View File

@@ -67,11 +67,13 @@ class DramGen : public RandomGen
/**
* Create a DRAM address sequence generator.
*
* @param gen Traffic generator owning this sequence generator
* @param obj SimObject owning this sequence generator
* @param master_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
* @param _blocksize Size used for transactions injected
* @param cacheline_size cache line size in the system
* @param min_period Lower limit of random inter-transaction time
* @param max_period Upper limit of random inter-transaction time
* @param read_percent Percent of transactions that are reads
@@ -85,8 +87,10 @@ class DramGen : public RandomGen
* 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramGen(BaseTrafficGen &gen, Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
DramGen(SimObject &obj,
MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,

14
src/cpu/testers/traffic_gen/dram_rot_gen.hh
View File

@@ -66,11 +66,13 @@ class DramRotGen : public DramGen
* 2) Command type (if applicable)
* 3) Ranks per channel
*
* @param gen Traffic generator owning this sequence generator
* @param obj SimObject owning this sequence generator
* @param master_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
* @param _blocksize Size used for transactions injected
* @param cacheline_size cache line size in the system
* @param min_period Lower limit of random inter-transaction time
* @param max_period Upper limit of random inter-transaction time
* @param read_percent Percent of transactions that are reads
@@ -85,8 +87,9 @@ class DramRotGen : public DramGen
* 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramRotGen(BaseTrafficGen &gen, Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
@@ -94,8 +97,9 @@ class DramRotGen : public DramGen
unsigned int addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
: DramGen(gen, _duration, start_addr, end_addr,
_blocksize, min_period, max_period, read_percent, data_limit,
: DramGen(obj, master_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit,
num_seq_pkts, page_size, nbr_of_banks_DRAM,
nbr_of_banks_util, addr_mapping,
nbr_of_ranks),

4
src/cpu/testers/traffic_gen/exit_gen.hh
View File

@@ -56,8 +56,8 @@ class ExitGen : public BaseGen
public:
ExitGen(BaseTrafficGen &gen, Tick _duration)
: BaseGen(gen, _duration)
ExitGen(SimObject &obj, MasterID master_id, Tick _duration)
: BaseGen(obj, master_id, _duration)
{ }
void enter();

4
src/cpu/testers/traffic_gen/idle_gen.hh
View File

@@ -61,8 +61,8 @@ class IdleGen : public BaseGen
public:
IdleGen(BaseTrafficGen &gen, Tick _duration)
: BaseGen(gen, _duration)
IdleGen(SimObject &obj, MasterID master_id, Tick _duration)
: BaseGen(obj, master_id, _duration)
{ }
void enter();

16
src/cpu/testers/traffic_gen/linear_gen.hh
View File

@@ -71,23 +71,27 @@ class LinearGen : public StochasticGen
* min_period == max_period for a fixed inter-transaction
* time.
*
* @param gen Traffic generator owning this sequence generator
* @param obj SimObject owning this sequence generator
* @param master_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
* @param _blocksize Size used for transactions injected
* @param cacheline_size cache line size in the system
* @param min_period Lower limit of random inter-transaction time
* @param max_period Upper limit of random inter-transaction time
* @param read_percent Percent of transactions that are reads
* @param data_limit Upper limit on how much data to read/write
*/
LinearGen(BaseTrafficGen &gen, Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
LinearGen(SimObject &obj,
MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
: StochasticGen(gen, _duration, start_addr, end_addr,
_blocksize, min_period, max_period, read_percent,
data_limit),
: StochasticGen(obj, master_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
nextAddr(0),
dataManipulated(0)
{ }

11
src/cpu/testers/traffic_gen/random_gen.hh
View File

@@ -79,12 +79,15 @@ class RandomGen : public StochasticGen
* @param read_percent Percent of transactions that are reads
* @param data_limit Upper limit on how much data to read/write
*/
RandomGen(BaseTrafficGen &gen, Tick _duration,
Addr start_addr, Addr end_addr, Addr _blocksize,
RandomGen(SimObject &obj,
MasterID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
: StochasticGen(gen, _duration, start_addr, end_addr, _blocksize,
min_period, max_period, read_percent, data_limit),
: StochasticGen(obj, master_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
dataManipulated(0)
{ }

7
src/cpu/testers/traffic_gen/trace_gen.hh
View File

@@ -152,14 +152,15 @@ class TraceGen : public BaseGen
/**
* Create a trace generator.
*
* @param gen Traffic generator owning this sequence generator
* @param obj SimObject owning this sequence generator
* @param master_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param trace_file File to read the transactions from
* @param addr_offset Positive offset to add to trace address
*/
TraceGen(BaseTrafficGen &gen, Tick _duration,
TraceGen(SimObject &obj, MasterID master_id, Tick _duration,
const std::string& trace_file, Addr addr_offset)
: BaseGen(gen, _duration),
: BaseGen(obj, master_id, _duration),
trace(trace_file),
tickOffset(0),
addrOffset(addr_offset),