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arch-arm: Introduce ARMv8.1 Virtual Timer System Registers

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Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers
into the decode tree. They are currently implemented as a generic timer
and produces a warning if accessed.

Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11592
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-05-17 17:19:53 +01:00
parent cb09573e52
commit e7f6e7cd26
3 changed files with 30 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/arm/isa.cc
View File

@@ -644,6 +644,9 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
return 0; // bits [63:0] RES0 (reserved for future use)
// Generic Timer registers
case MISCREG_CNTHV_CTL_EL2:
case MISCREG_CNTHV_CVAL_EL2:
case MISCREG_CNTHV_TVAL_EL2:
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
@@ -1913,6 +1916,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
break;
// Generic Timer registers
case MISCREG_CNTHV_CTL_EL2:
case MISCREG_CNTHV_CVAL_EL2:
case MISCREG_CNTHV_TVAL_EL2:
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:

16
src/arch/arm/miscregs.cc
View File

@@ -2331,6 +2331,16 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
return MISCREG_CNTHP_CVAL_EL2;
}
break;
case 3:
switch (op2) {
case 0:
return MISCREG_CNTHV_TVAL_EL2;
case 1:
return MISCREG_CNTHV_CTL_EL2;
case 2:
return MISCREG_CNTHV_CVAL_EL2;
}
break;
}
break;
case 7:
@@ -4018,6 +4028,12 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CONTEXTIDR_EL2)
.mon().hyp();
InitReg(MISCREG_CNTHV_CTL_EL2)
.mon().hyp();
InitReg(MISCREG_CNTHV_CVAL_EL2)
.mon().hyp();
InitReg(MISCREG_CNTHV_TVAL_EL2)
.mon().hyp();
// Dummy registers
InitReg(MISCREG_NOP)

16
src/arch/arm/miscregs.hh
View File

@@ -668,14 +668,14 @@ namespace ArmISA
// Introduced in ARMv8.1
MISCREG_TTBR1_EL2, // 600
MISCREG_CNTHV_CTL_EL2, // 601
MISCREG_CNTHV_CVAL_EL2, // 602
MISCREG_CNTHV_TVAL_EL2, // 603
// These MISCREG_FREESLOT are available Misc Register
// slots for future registers to be implemented.
MISCREG_FREESLOT_1, // 601
MISCREG_FREESLOT_2, // 602
MISCREG_FREESLOT_3, // 603
MISCREG_FREESLOT_4, // 604
MISCREG_FREESLOT_5, // 605
MISCREG_FREESLOT_1, // 604
MISCREG_FREESLOT_2, // 605
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
@@ -1385,11 +1385,11 @@ namespace ArmISA
"contextidr_el2",
"ttbr1_el2",
"cnthv_ctl_el2",
"cnthv_cval_el2",
"cnthv_tval_el2",
"freeslot1",
"freeslot2",
"freeslot3",
"freeslot4",
"freeslot5",
"num_phys_regs",