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mem: Add a memory delay simulator

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Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:

  * delayReq(pkt)
  * delayResp(pkt)
  * delaySnoopResp(pkt)

These methods should be specialized to implement delays for specific
packet types.

The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.

The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.

Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Andreas Sandberg
2018-05-02 13:55:10 +01:00
parent f6dd997ef4
commit 0f33b2c1d5
4 changed files with 460 additions and 0 deletions
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57
src/mem/MemDelay.py Normal file
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@@ -0,0 +1,57 @@
# Copyright (c) 2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
from m5.params import *
from MemObject import MemObject
class MemDelay(MemObject):
type = 'MemDelay'
cxx_header = 'mem/mem_delay.hh'
abstract = True
master = MasterPort("Master port")
slave = SlavePort("Slave port")
class SimpleMemDelay(MemDelay):
type = 'SimpleMemDelay'
cxx_header = 'mem/mem_delay.hh'
read_req = Param.Latency("0t", "Read request delay")
read_resp = Param.Latency("0t", "Read response delay")
write_req = Param.Latency("0t", "Write request delay")
write_resp = Param.Latency("0t", "Write response delay")

2
src/mem/SConscript
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@@ -44,6 +44,7 @@ SimObject('SimpleMemory.py')
SimObject('XBar.py')
SimObject('HMCController.py')
SimObject('SerialLink.py')
SimObject('MemDelay.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -68,6 +69,7 @@ Source('tport.cc')
Source('xbar.cc')
Source('hmc_controller.cc')
Source('serial_link.cc')
Source('mem_delay.cc')
if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')

216
src/mem/mem_delay.cc Normal file
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/*
* Copyright (c) 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andreas Sandberg
*/
#include "mem/mem_delay.hh"
#include "params/MemDelay.hh"
#include "params/SimpleMemDelay.hh"
MemDelay::MemDelay(const MemDelayParams *p)
: MemObject(p),
masterPort(name() + "-master", *this),
slavePort(name() + "-slave", *this),
reqQueue(*this, masterPort),
respQueue(*this, slavePort),
snoopRespQueue(*this, masterPort)
{
}
void
MemDelay::init()
{
if (!slavePort.isConnected() || !masterPort.isConnected())
fatal("Memory delay is not connected on both sides.\n");
}
BaseMasterPort&
MemDelay::getMasterPort(const std::string& if_name, PortID idx)
{
if (if_name == "master") {
return masterPort;
} else {
return MemObject::getMasterPort(if_name, idx);
}
}
BaseSlavePort&
MemDelay::getSlavePort(const std::string& if_name, PortID idx)
{
if (if_name == "slave") {
return slavePort;
} else {
return MemObject::getSlavePort(if_name, idx);
}
}
bool
MemDelay::checkFunctional(PacketPtr pkt)
{
return slavePort.checkFunctional(pkt) ||
masterPort.checkFunctional(pkt);
}
MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
: QueuedMasterPort(_name, &_parent,
_parent.reqQueue, _parent.snoopRespQueue),
parent(_parent)
{
}
bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
{
const Tick when = curTick() + parent.delayResp(pkt);
parent.slavePort.schedTimingResp(pkt, when);
return true;
}
void
MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
{
if (parent.checkFunctional(pkt)) {
pkt->makeResponse();
} else {
parent.slavePort.sendFunctionalSnoop(pkt);
}
}
Tick
MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
{
const Tick delay = parent.delaySnoopResp(pkt);
return delay + parent.slavePort.sendAtomicSnoop(pkt);
}
void
MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
{
parent.slavePort.sendTimingSnoopReq(pkt);
}
MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent)
: QueuedSlavePort(_name, &_parent, _parent.respQueue),
parent(_parent)
{
}
Tick
MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
{
const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
return delay + parent.masterPort.sendAtomic(pkt);
}
bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
{
const Tick when = curTick() + parent.delayReq(pkt);
parent.masterPort.schedTimingReq(pkt, when);
return true;
}
void
MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
{
if (parent.checkFunctional(pkt)) {
pkt->makeResponse();
} else {
parent.masterPort.sendFunctional(pkt);
}
}
bool
MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
{
const Tick when = curTick() + parent.delaySnoopResp(pkt);
parent.masterPort.schedTimingSnoopResp(pkt, when);
return true;
}
SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
: MemDelay(p),
readReqDelay(p->read_req),
readRespDelay(p->read_resp),
writeReqDelay(p->write_req),
writeRespDelay(p->write_resp)
{
}
Tick
SimpleMemDelay::delayReq(PacketPtr pkt)
{
if (pkt->isRead()) {
return readReqDelay;
} else if (pkt->isWrite()) {
return writeReqDelay;
} else {
return 0;
}
}
Tick
SimpleMemDelay::delayResp(PacketPtr pkt)
{
if (pkt->isRead()) {
return readRespDelay;
} else if (pkt->isWrite()) {
return writeRespDelay;
} else {
return 0;
}
}
SimpleMemDelay *
SimpleMemDelayParams::create()
{
return new SimpleMemDelay(this);
}

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src/mem/mem_delay.hh Normal file
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/*
* Copyright (c) 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andreas Sandberg
*/
#ifndef __MEM_MEM_DELAY_HH__
#define __MEM_MEM_DELAY_HH__
#include "mem/mem_object.hh"
#include "mem/qport.hh"
struct MemDelayParams;
struct SimpleMemDelayParams;
/**
* This abstract component provides a mechanism to delay
* packets. It can be spliced between arbitrary ports of the memory
* system and delays packets that pass through it.
*
* Specialisations of this abstract class should override at least one
* of delayReq, delayResp, deleySnoopReq, delaySnoopResp. These
* methods receive a PacketPtr as their argument and return a delay in
* Ticks. The base class implements an infinite buffer to hold delayed
* packets until they are ready. The intention is to use this
* component for rapid prototyping of other memory system components
* that introduce a packet processing delays.
*
* NOTE: Packets may be reordered if the delays aren't constant.
*/
class MemDelay : public MemObject
{
public:
MemDelay(const MemDelayParams *params);
void init() override;
protected: // Port interfaces
BaseMasterPort& getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID) override;
BaseSlavePort& getSlavePort(const std::string &if_name,
PortID idx = InvalidPortID) override;
class MasterPort : public QueuedMasterPort
{
public:
MasterPort(const std::string &_name, MemDelay &_parent);
protected:
bool recvTimingResp(PacketPtr pkt) override;
void recvFunctionalSnoop(PacketPtr pkt) override;
Tick recvAtomicSnoop(PacketPtr pkt) override;
void recvTimingSnoopReq(PacketPtr pkt) override;
void recvRangeChange() override {
parent.slavePort.sendRangeChange();
}
bool isSnooping() const override {
return parent.slavePort.isSnooping();
}
private:
MemDelay& parent;
};
class SlavePort : public QueuedSlavePort
{
public:
SlavePort(const std::string &_name, MemDelay &_parent);
protected:
Tick recvAtomic(PacketPtr pkt) override;
bool recvTimingReq(PacketPtr pkt) override;
void recvFunctional(PacketPtr pkt) override;
bool recvTimingSnoopResp(PacketPtr pkt) override;
AddrRangeList getAddrRanges() const override {
return parent.masterPort.getAddrRanges();
}
bool tryTiming(PacketPtr pkt) override { return true; }
private:
MemDelay& parent;
};
bool checkFunctional(PacketPtr pkt);
MasterPort masterPort;
SlavePort slavePort;
ReqPacketQueue reqQueue;
RespPacketQueue respQueue;
SnoopRespPacketQueue snoopRespQueue;
protected:
/**
* Delay a request by some number of ticks.
*
* @return Ticks to delay packet.
*/
virtual Tick delayReq(PacketPtr pkt) { return 0; }
/**
* Delay a response by some number of ticks.
*
* @return Ticks to delay packet.
*/
virtual Tick delayResp(PacketPtr pkt) { return 0; }
/**
* Delay a snoop response by some number of ticks.
*
* @return Ticks to delay packet.
*/
virtual Tick delaySnoopResp(PacketPtr pkt) { return 0; }
};
/**
* Delay packets by a constant time. Delays can be specified
* separately for read requests, read responses, write requests, and
* write responses.
*
* This class does not delay snoops or requests/responses that are
* neither reads or writes.
*/
class SimpleMemDelay : public MemDelay
{
public:
SimpleMemDelay(const SimpleMemDelayParams *params);
protected:
Tick delayReq(PacketPtr pkt) override;
Tick delayResp(PacketPtr pkt) override;
protected: // Params
const Tick readReqDelay;
const Tick readRespDelay;
const Tick writeReqDelay;
const Tick writeRespDelay;
};
#endif //__MEM_MEM_DELAY_HH__