derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Fix incorrect t{0,1}sz field in TTBCR

Browse Source 
The t0sz and t1sz fields in TTBCR only are only three bits wide unlike
aarch64 which has a 6-bit wide field. The higher bits of the
aarch64-equivalent should be treated as RES0.

Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11589
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Andreas Sandberg
2018-06-27 09:35:11 +01:00
parent a77222f8d0
commit f6dd997ef4
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/miscregs.hh
View File

@@ -1722,13 +1722,13 @@ namespace ArmISA
Bitfield<4> pd0;
Bitfield<5> pd1;
// Long-descriptor translation table format
Bitfield<5, 0> t0sz;
Bitfield<2, 0> t0sz;
Bitfield<7> epd0;
Bitfield<9, 8> irgn0;
Bitfield<11, 10> orgn0;
Bitfield<13, 12> sh0;
Bitfield<14> tg0;
Bitfield<21, 16> t1sz;
Bitfield<18, 16> t1sz;
Bitfield<22> a1;
Bitfield<23> epd1;
Bitfield<25, 24> irgn1;