Requests in GPUFS which go to system memory will not generate the
WriteCompleteResp packets that the VIPER protocol would normally created
for device requests which go through the caches. Therefore, we need to
callback the GM pipe handleResponse to complete the access and make
forward progress.
Change-Id: Ic00c430ce420a591fe5743f758b780d93afd2a38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57989
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
In full system mode, the AMDKernelCode object can reside in either the
system memory or in the dGPU device memory. Currently only reading from
the host/system memory is supported. This adds the necessary code to
read from the dGPU device memory.
Change-Id: I887fc706b3f9834db14e40f36fd29dd3d4602925
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57710
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The emulated driver is currently called in a few locations
unconditionally. This changeset adds checks that we are not in full
system before calling any emulated driver function. In full system the
amdgpu driver running on the disk image handles these functions.
Change-Id: Iea3546b574e29c649351c0fce9154530be89e9b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57712
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The amdgpu driver supports reading and writing scalar and vector memory
addresses that reside in system memory. This is commonly used for things
like blit kernels that perform host-to-device or device-to-host copies
using GPU load/store instructions.
This is done by utilizing the system hub device added in a prior
changeset. Memory packets translated by the Scalar or VMEM TLBs will
have the correspoding system request field set from the PTE in the TLB
which can be used in the compute unit to determine if a request is for
system memory or not.
Another important change is to return global memory tokens for system
requests. Since these do not flow through the GPU coalescer where the
token is returned, the token can be returned once the request is known
to be a system request.
Change-Id: I35030e0b3698f10c63a397f96b81267271e3130e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57711
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The two functions are `get_cpu_types_str_set()` which returns a set of
valid CPUTypes as strings, and `get_cpu_type_from_str()` which will
return a CPUType enum given an input string.
The purpose of these functions is to aid and standardize user input
parameters or environment variables.
Test scripts are updated accordingly.
Change-Id: I7cb9263321fe36bc8a7530edfd0d8e8bbd329e0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58491
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
The main restriction with this design is it results in one ISA target
per board. The ISA is declared per core. To make the design simpler it's
assumed a Processor (a collection of cores) are all of the same ISA. As
each board has one processor, this also means a board is typically tied
to one ISA per simulation.
In order to remain backwards compatible and maintain the standard
library APIs, this patch adds a `--main-isa` parameter which will
determine what `gem5.runtime.get_runtime_isa` returns in cases where
mutliple ISAs are compiled in. When setting the ISA in a simulation (via
the Processor or Cores), the user may, as before, choose not to and, in
this case, the `gem5.runtime.get_runtime_isa` function is used.
The `gem5.runtime.get_runtime_isa` function is an intermediate step
which should be removed in future versions of gem5 (users should specify
precisely what ISA they want via configuration scripts). For this reason
it throws a warning when used and should not be heavily relied upon. It
is deprecated.
Change-Id: Ia76541bfa9a5a4b6b86401309281849b49dc724b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55423
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This helper extracts config variables and sets them up for use in
fast model tools. Rework this function for two purposes. First, ensure
that the ['CONF'] subdict is used consistently. It was used in one spot
in that function, but not anywhere else. Avoid those mistakes by
accessing the configuration dict only once, and then reusing the value.
Second, only print the values of those variables if they aren't empty.
That avoids extra log output for values which aren't set up and aren't
being used, while still exposing those values if they are set up. This
will print them even if they aren't being actively used, but are set up
and could be with other changes in the config.
Change-Id: Ia3ea76e6cb6b3347fd082112a1eaa8d594e06ca2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58354
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
If a fast model static library can't be found, we should treat that as
a warning instead of an error, and pass back the original library name
so that it can at least be added and potentially come from somewhere
else.
In practice, this is important because gem5 will be configured by SCons
indirectly in the future, using kconfig based tools that SCons runs on
the user's behalf. If SCons is misconfigured or not configured, this
error can trip, preventing those tools from starting. That creates a
catch 22, since you'd need SCons to fix the config, and SCons can't
run because of the config.
We can avoid that problem by making SCons more lenient, so that it can
still run even if it doesn't find static libraries where it might have
expected to.
Change-Id: Iadfd823b61fe96b937c2650250487d290492f265
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58352
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This held the location of the license file, assuming it actually was a
license file and not a license server URL. If this variable was unset
because the fast model configuration parameters hadn't been set, then
the "File" would resolve to the local directory, and SCons would get
upset that you'd called the same path a directory and a file.
We can avoid this problem by just getting rid of this variable, since
it isn't used anyway.
Change-Id: I2ccda90b85f2c83c73816967d145e6bf45733f89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58351
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This helps specify ordering for libraries that need it. Libraries with
a higher priority will be sorted earlier in the list, which can be
necessary when working with static libraries/archives.
The default value for "priority" is zero. It's only really necessary
to ensure relative ordering of particular pairings of libraries, so
it should be ok to use an absolute integer value for this. If you
need to order relative to a library, there is a good chance you're
adding it, or the place it's added is well known and you can easily
find its priority value. It's also unlikely that there would be a
complex series of interactions between libraries that would make a
more complicated system warranted.
Change-Id: Ie94a35e6563c07f8d462a4a52d0173ea3cf4f8de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58350
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
In Python, "+=" operator for list acts more like append and list assign
doesn't make a copy. This will cause unexpected append to the orignal
list. Since we have multiple env to "declare", these functions will be
called multiple times and could wrongly append duplicated entries in
later calls.
Make a copy before appending the entries from filter to avoid this
problem.
Change-Id: I144d5054e4d93191ebc94b93291ff9a3f8a6c429
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58409
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ProtoBuf files can (and should) be declared to SCons unconditionally,
but then also use a "protobuf" tag. This lets SCons still include them
conditionally when it gathers sources to build certain binaries without
having additional python logic in SConscripts, or manually interpreting
config state.
Change-Id: I9426d647bc2d6c9d7eee7dadba77f75ed83bcaad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58349
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
If we create abstract memories with a sub-page size on a system with
shared backstore, the offset of next mmap might become non-page-align
and cause an invalid argument error.
In this CL, we always upscale the range size to multiple of page before
updating the offset, so the offset is always on page boundary.
Change-Id: I3a6adf312f2cb5a09ee6a24a87adc62b630eac66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58289
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This patch fixes the problem during checkpoing where the mempool is not
restored, but using only the one specified in the config file as a new
execution.
In order to fix that this changes modifyies the serialize/unserialize
functions for mempools and create new funcionts on se_workload to make
sure mempools ends up in the m5.cpt.
We change as well the unserialize mempool function to update
according the checkpoint file so the execution starts with the same
free pages and free pointers.
JIRA: https://gem5.atlassian.net/browse/GEM5-1191
Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56969
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The QCntxt is reused when a queue is unmapped and mapped again. This is
fairly common in GPU full system. If this is not done the readIndex on
the queue context is reset to 1, causing getCommandsFromHost to read
from the wrong slot which is typically an old dispatch packet or an
invalid packet. This causes simulation to stall as the incorrect
completion signal is eventually written.
Change-Id: I65541e559fe04f5eb44b936ca37e3f802262fe6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57670
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The amdgpu driver supports fetching instructions from pages which reside
in system memory rather than device memory. This changeset adds support
to do this by adding the system hub object added in a prior changeset to
the fetch unit and issues requests to the system hub if the system bit
in the memory page's PTE is set. Otherwise, the requestor ID is set to
be device memory and the request is routed through the Ruby network /
GPU caches to fetch the instructions.
Change-Id: Ib2fb47c589fdd5e544ab6493d7dbd8f2d9d7b0e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57652
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.
These variables will also be plumbed into and out of kconfiglib in later
changes.
Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Add an utility class that provides a service for another process
query and get the fd of the corresponding region in gem5's physmem.
Basically, the service works in this way:
1. client connect to the unix socket created by a SharedMemoryServer
2. client send a request {start, end} to gem5
3. the server locates the corresponding shared memory
4. gem5 response {offset} and pass {fd} in ancillary data
mmap fd at offset will provide the client the view into the physical
memory of the request range.
Change-Id: I9d42fd8a41fc28dcfebb45dec10bc9ebb8e21d11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57729
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
For instructions which simply require CPL0 (vs. requiring CPL is < IOPL,
or something else more complicated), this change either switches their
format so that they check that value before being returned, or adds a
comment marking them as privileged if they aren't yet implemented.
This change also makes the mov to/from CR and DR instructions more
particular, and returns an undefined instruction if the CR or DR index
is invalid.
Change-Id: I367d87a380a47428d458bda2ceecc1b983644704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55891
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This value is already floating around, and there is essentially no
overhead for exposing it to the decoder. With that value, we can handle
instructions which generically need to run at CPL0.
Some instructions have other more complicated permissions checks, like
that the CPL needs to have some relation to the IOPL. Those checks will
have to be implemented by the instructions themselves, since the decoder
can't factor in all possible state values.
Change-Id: Ie93f4f13aae002f69330606c515f369c5706c655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55889
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reads to the frame buffer are currently handled by either the MMIO trace
or from the GART table if the address is in the GART aperture. In some
cases the MMIO trace will not contain the address or the data may have
been written previously and be different from the MMIO trace. To handle
this, return the data that was written previously by the driver. The
priority order from lowest to highest is: MMIO trace, device cache,
special framebuffer registers.
Change-Id: Ia45ae19555508fcd780926fedbd7a65c3d294727
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57589
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The driver will check this bit is set after initializing IPs. Currently
the MMIO trace will cause this bit to be set at the correct time,
however this is not portable access different ROCm versions. Therefore
we modify the value to always set the bit indicating interrupts are
enabled.
Change-Id: Iae0baf1936720fbe9835ae4acadbf1b3bdc52896
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57530
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Currently if a Ruby functional access fails to find an address in the
caches, it gives up. For functional page table walks we need to be able
to go all the way to memory. This adds a pointer to the system object
which allows the walker to get a pointer to device memory which can be
used to do a functional access directly to memory bypassing Ruby.
Change-Id: I0ead6e5e130a0d53021c44ae9221b167c6316ab2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57529
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Make the necessary changes to connect Vega pagetable walkers for
full-system mode. Previously the CP and HSA packet processor could only
read AQL packets from system/host memory using proxy port. This allows
for AQL to be read from device memory which is used for non-blit
kernels.
Change-Id: If28eb8be68173da03e15084765e77e92eda178e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53077
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The classes defined by the ISA description are actually just descriptors
which are used to make more specialized Operand classes, and then those
classes are instantiated to represent actual operands in a given
instruction. There they encode the actual index of the register, any
extensions used, etc.
To make defining operand types in the ISA more flexible and to take less
explicit machinery, this change defines a mechanism to allow overriding
individual methods of the operand class. This should for instance make
the read_code and write_code members of those classes unnecessary.
Change-Id: I1a1f787970ba56bd2884a80df4618a77eb454605
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49740
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This patch is fixing the redirectRegVHE method in the following
ways:
* Redirect AArch32 version of timer/counter registers
* Redirect _EL12 registers to _EL1
* Redirect _EL02 registers to _EL0
* Redirect CNTV_*_EL0 and CNTP_*_EL0 registers to
the Secure/Non-secure _EL2
* Redirect CNTVCT_EL0 to CNTPCT_EL0
Change-Id: I34eb317045b2d5a304a29ccf6e6440df68b2a279
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
