cpu: Handle external TLBI Sync requests in TimingCPU

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I4e92f7886a296f119720b8bcda6bea722df76153
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57291
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Samuel Stark
2021-11-02 08:53:02 +00:00
committed by Giacomo Travaglini
parent 38fe886ee3
commit eafc6ea626

View File

@@ -1097,14 +1097,31 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
}
// Making it uniform across all CPUs:
// The CPUs need to be woken up only on an invalidation packet (when using caches)
// or on an incoming write packet (when not using caches)
// It is not necessary to wake up the processor on all incoming packets
// The CPUs need to be woken up only on an invalidation packet
// (when using caches) or on an incoming write packet (when not
// using caches) It is not necessary to wake up the processor on
// all incoming packets
if (pkt->isInvalidate() || pkt->isWrite()) {
for (auto &t_info : cpu->threadInfo) {
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
}
} else if (pkt->req && pkt->req->isTlbiExtSync()) {
// We received a TLBI_EXT_SYNC request.
// In a detailed sim we would wait for memory ops to complete,
// but in our simple case we just respond immediately
auto reply_req = Request::createMemManagement(
Request::TLBI_EXT_SYNC_COMP,
cpu->dataRequestorId());
// Extra Data = the transaction ID of the Sync we're completing
reply_req->setExtraData(pkt->req->getExtraData());
PacketPtr reply_pkt = Packet::createRead(reply_req);
// TODO - reserve some credit for these responses?
if (!sendTimingReq(reply_pkt)) {
panic("Couldn't send TLBI_EXT_SYNC_COMP message");
}
}
}