scons: Add a tag for arm fastmodel and use it.
This avoids some python logic in the SConscript files, and explicit references to the configuration system. Change-Id: If6ee61bb8c23606859e60323b8ca2c5254dbdecc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58356 Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
@@ -25,9 +25,6 @@
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Import('*')
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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protocol_dir = Dir('..').Dir('protocol')
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for name in ('x1', 'x2', 'x3', 'x4'):
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@@ -39,7 +36,8 @@ for name in ('x1', 'x2', 'x3', 'x4'):
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SimObject('FastModelCortexA76.py', sim_objects=[
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'FastModelCortexA76', 'FastModelCortexA76Cluster'] +
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[f'FastModelScxEvsCortexA76x{num}' for num in (1, 2, 3, 4)])
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Source('cortex_a76.cc')
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Source('evs.cc')
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Source('thread_context.cc')
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[f'FastModelScxEvsCortexA76x{num}' for num in (1, 2, 3, 4)],
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tags='arm fastmodel')
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Source('cortex_a76.cc', tags='arm fastmodel')
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Source('evs.cc', tags='arm fastmodel')
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Source('thread_context.cc', tags='arm fastmodel')
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@@ -25,9 +25,6 @@
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Import('*')
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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protocol_dir = Dir('..').Dir('protocol')
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for name in ('x1', 'x2', 'x3', 'x4'):
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@@ -40,7 +37,8 @@ for name in ('x1', 'x2', 'x3', 'x4'):
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SimObject('FastModelCortexR52.py', sim_objects=[
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'FastModelCortexR52', 'FastModelCortexR52Cluster'] +
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[f'FastModelScxEvsCortexR52x{num}' for num in (1, 2, 3, 4)])
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Source('cortex_r52.cc')
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Source('evs.cc')
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Source('thread_context.cc')
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[f'FastModelScxEvsCortexR52x{num}' for num in (1, 2, 3, 4)],
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tags='arm fastmodel')
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Source('cortex_r52.cc', tags='arm fastmodel')
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Source('evs.cc', tags='arm fastmodel')
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Source('thread_context.cc', tags='arm fastmodel')
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@@ -25,13 +25,11 @@
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Import('*')
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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protocol_dir = Dir('..').Dir('protocol')
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ArmFastModelComponent(File('GIC.sgproj'), File('GIC.lisa'),
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protocol_dir.File('SignalInterruptProtocol.lisa')
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).prepare_env(env)
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SimObject('FastModelGIC.py', sim_objects=['SCFastModelGIC', 'FastModelGIC'])
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Source('gic.cc')
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SimObject('FastModelGIC.py', sim_objects=['SCFastModelGIC', 'FastModelGIC'],
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tags='arm fastmodel')
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Source('gic.cc', tags='arm fastmodel')
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@@ -25,13 +25,11 @@
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Import('*')
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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protocol_dir = Dir('..').Dir('protocol')
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ArmFastModelComponent(File('PL330.sgproj'), File('PL330.lisa'),
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protocol_dir.File('SignalInterruptProtocol.lisa')
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).prepare_env(env)
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SimObject('FastModelPL330.py', sim_objects=['FastModelPL330'])
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Source('pl330.cc')
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SimObject('FastModelPL330.py', sim_objects=['FastModelPL330'],
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tags='arm fastmodel')
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Source('pl330.cc', tags='arm fastmodel')
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@@ -48,13 +48,11 @@ from gem5_scons import Transform, warning, error
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import os.path
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if env['CONF']['USE_ARM_FASTMODEL']:
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if not env['CONF']['USE_SYSTEMC']:
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if env['CONF']['USE_SYSTEMC']:
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env.TagImplies('arm fastmodel', 'arm isa')
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else:
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warning('ARM Fast Models require systemc support')
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env['CONF']['USE_ARM_FASTMODEL'] = False
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Return()
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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systemc_home = Dir('#/src/systemc/ext/systemc_home')
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@@ -144,11 +142,11 @@ fm_static_libs = (
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'IrisSupport',
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)
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for lib in fm_static_libs:
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SourceLib(staticify(env, lib))
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SourceLib(staticify(env, lib), tags='arm fastmodel')
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SourceLib('atomic')
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SourceLib('dl')
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SourceLib('rt')
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SourceLib('atomic', tags='arm fastmodel')
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SourceLib('dl', tags='arm fastmodel')
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SourceLib('rt', tags='arm fastmodel')
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class ProjectFileParser(Grammar):
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def __init__(self):
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@@ -399,7 +397,9 @@ class ArmFastModelComponent(object):
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env.Append(LIBPATH=self.libpaths)
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env.AddLocalRPATH(*self.rpaths)
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env.Append(CPPPATH=self.headerpaths)
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env.Prepend(LIBS=self.libs)
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# Put these libraries earlier in the list by setting priority.
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for lib in self.libs:
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SourceLib(lib, priority=1, tags='arm fastmodel')
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def simgen_builder(self, target, source, env):
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cmd = self.simgen_cmd
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@@ -414,10 +414,10 @@ class ArmFastModelComponent(object):
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Export('ArmFastModelComponent')
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PySource('m5', 'arm_fast_model.py')
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Source('fastmodel.cc')
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PySource('m5', 'arm_fast_model.py', tags='arm fastmodel')
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Source('fastmodel.cc', tags='arm fastmodel')
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SimObject('FastModel.py', sim_objects=[
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'AmbaToTlmBridge64', 'AmbaFromTlmBridge64'])
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Source('amba_to_tlm_bridge.cc')
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Source('amba_from_tlm_bridge.cc')
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'AmbaToTlmBridge64', 'AmbaFromTlmBridge64'], tags='arm fastmodel')
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Source('amba_to_tlm_bridge.cc', tags='arm fastmodel')
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Source('amba_from_tlm_bridge.cc', tags='arm fastmodel')
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@@ -25,14 +25,12 @@
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Import('*')
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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SimObject('Iris.py', sim_objects=[
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'IrisTLB', 'IrisMMU', 'IrisInterrupts', 'IrisISA', 'IrisBaseCPU'])
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Source('cpu.cc')
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Source('interrupts.cc')
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Source('isa.cc')
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Source('tlb.cc')
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'IrisTLB', 'IrisMMU', 'IrisInterrupts', 'IrisISA', 'IrisBaseCPU'],
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tags='arm fastmodel')
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Source('cpu.cc', tags='arm fastmodel')
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Source('interrupts.cc', tags='arm fastmodel')
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Source('isa.cc', tags='arm fastmodel')
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Source('tlb.cc', tags='arm fastmodel')
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Source('thread_context.cc')
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Source('thread_context.cc', tags='arm fastmodel')
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@@ -25,10 +25,7 @@
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Import('*')
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if not env['CONF']['USE_ARM_FASTMODEL']:
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Return()
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SimObject('FastModelResetControllerExample.py', sim_objects=[
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'FastModelResetControllerExample'])
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'FastModelResetControllerExample'], tags='arm fastmodel')
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Source('example.cc')
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Source('example.cc', tags='arm fastmodel')
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