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arch-arm: Fix ISA::redirectRegVHE method

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This patch is fixing the redirectRegVHE method in the following
ways:

* Redirect AArch32 version of timer/counter registers
* Redirect _EL12 registers to _EL1
* Redirect _EL02 registers to _EL0
* Redirect CNTV_*_EL0 and CNTP_*_EL0 registers to
the Secure/Non-secure _EL2
* Redirect CNTVCT_EL0 to CNTPCT_EL0

Change-Id: I34eb317045b2d5a304a29ccf6e6440df68b2a279
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-03-17 10:23:31 +00:00
parent 4e1dda069e
commit d982185d6e
1 changed files with 113 additions and 35 deletions
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148
src/arch/arm/isa.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2021 ARM Limited
* Copyright (c) 2010-2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -597,68 +597,146 @@ int
ISA::redirectRegVHE(int misc_reg)
{
const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
if (hcr.e2h == 0x0 || currEL() != EL2)
if (hcr.e2h == 0x0)
return misc_reg;
SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
bool sec_el2 = scr.eel2 && release->has(ArmExtension::FEAT_SEL2);
switch(misc_reg) {
case MISCREG_SPSR_EL1:
return MISCREG_SPSR_EL2;
return currEL() == EL2 ? MISCREG_SPSR_EL2 : misc_reg;
case MISCREG_ELR_EL1:
return MISCREG_ELR_EL2;
return currEL() == EL2 ? MISCREG_ELR_EL2 : misc_reg;
case MISCREG_SCTLR_EL1:
return MISCREG_SCTLR_EL2;
return currEL() == EL2 ? MISCREG_SCTLR_EL2 : misc_reg;
case MISCREG_CPACR_EL1:
return MISCREG_CPTR_EL2;
// case :
// return MISCREG_TRFCR_EL2;
return currEL() == EL2 ? MISCREG_CPTR_EL2 : misc_reg;
// case MISCREG_TRFCR_EL1:
// return currEL() == EL2 ? MISCREG_TRFCR_EL2 : misc_reg;
case MISCREG_TTBR0_EL1:
return MISCREG_TTBR0_EL2;
return currEL() == EL2 ? MISCREG_TTBR0_EL2 : misc_reg;
case MISCREG_TTBR1_EL1:
return MISCREG_TTBR1_EL2;
return currEL() == EL2 ? MISCREG_TTBR1_EL2 : misc_reg;
case MISCREG_TCR_EL1:
return MISCREG_TCR_EL2;
return currEL() == EL2 ? MISCREG_TCR_EL2 : misc_reg;
case MISCREG_AFSR0_EL1:
return MISCREG_AFSR0_EL2;
return currEL() == EL2 ? MISCREG_AFSR0_EL2 : misc_reg;
case MISCREG_AFSR1_EL1:
return MISCREG_AFSR1_EL2;
return currEL() == EL2 ? MISCREG_AFSR1_EL2 : misc_reg;
case MISCREG_ESR_EL1:
return MISCREG_ESR_EL2;
return currEL() == EL2 ? MISCREG_ESR_EL2 : misc_reg;
case MISCREG_FAR_EL1:
return MISCREG_FAR_EL2;
return currEL() == EL2 ? MISCREG_FAR_EL2 : misc_reg;
case MISCREG_MAIR_EL1:
return MISCREG_MAIR_EL2;
return currEL() == EL2 ? MISCREG_MAIR_EL2 : misc_reg;
case MISCREG_AMAIR_EL1:
return MISCREG_AMAIR_EL2;
return currEL() == EL2 ? MISCREG_AMAIR_EL2 : misc_reg;
case MISCREG_VBAR_EL1:
return MISCREG_VBAR_EL2;
return currEL() == EL2 ? MISCREG_VBAR_EL2 : misc_reg;
case MISCREG_CONTEXTIDR_EL1:
return MISCREG_CONTEXTIDR_EL2;
return currEL() == EL2 ? MISCREG_CONTEXTIDR_EL2 : misc_reg;
case MISCREG_CNTKCTL_EL1:
return MISCREG_CNTHCTL_EL2;
return currEL() == EL2 ? MISCREG_CNTHCTL_EL2 : misc_reg;
case MISCREG_CNTP_TVAL:
case MISCREG_CNTP_TVAL_EL0:
return sec_el2? MISCREG_CNTHPS_TVAL_EL2:
MISCREG_CNTHP_TVAL_EL2;
if (ELIsInHost(tc, currEL())) {
return sec_el2 && !scr.ns ? MISCREG_CNTHPS_TVAL_EL2:
MISCREG_CNTHP_TVAL_EL2;
} else {
return misc_reg;
}
case MISCREG_CNTP_CTL:
case MISCREG_CNTP_CTL_EL0:
return sec_el2? MISCREG_CNTHPS_CTL_EL2:
MISCREG_CNTHP_CTL_EL2;
if (ELIsInHost(tc, currEL())) {
return sec_el2 && !scr.ns ? MISCREG_CNTHPS_CTL_EL2:
MISCREG_CNTHP_CTL_EL2;
} else {
return misc_reg;
}
case MISCREG_CNTP_CVAL:
case MISCREG_CNTP_CVAL_EL0:
return sec_el2? MISCREG_CNTHPS_CVAL_EL2:
MISCREG_CNTHP_CVAL_EL2;
if (ELIsInHost(tc, currEL())) {
return sec_el2 && !scr.ns ? MISCREG_CNTHPS_CVAL_EL2:
MISCREG_CNTHP_CVAL_EL2;
} else {
return misc_reg;
}
case MISCREG_CNTV_TVAL:
case MISCREG_CNTV_TVAL_EL0:
return sec_el2? MISCREG_CNTHVS_TVAL_EL2:
MISCREG_CNTHV_TVAL_EL2;
if (ELIsInHost(tc, currEL())) {
return sec_el2 && !scr.ns ? MISCREG_CNTHVS_TVAL_EL2:
MISCREG_CNTHV_TVAL_EL2;
} else {
return misc_reg;
}
case MISCREG_CNTV_CTL:
case MISCREG_CNTV_CTL_EL0:
return sec_el2? MISCREG_CNTHVS_CTL_EL2:
MISCREG_CNTHV_CTL_EL2;
if (ELIsInHost(tc, currEL())) {
return sec_el2 && !scr.ns ? MISCREG_CNTHVS_CTL_EL2:
MISCREG_CNTHV_CTL_EL2;
} else {
return misc_reg;
}
case MISCREG_CNTV_CVAL:
case MISCREG_CNTV_CVAL_EL0:
return sec_el2? MISCREG_CNTHVS_CVAL_EL2:
MISCREG_CNTHV_CVAL_EL2;
if (ELIsInHost(tc, currEL())) {
return sec_el2 && !scr.ns ? MISCREG_CNTHVS_CVAL_EL2:
MISCREG_CNTHV_CVAL_EL2;
} else {
return misc_reg;
}
case MISCREG_CNTVCT:
case MISCREG_CNTVCT_EL0:
return ELIsInHost(tc, currEL()) ? MISCREG_CNTPCT_EL0 : misc_reg;
case MISCREG_SCTLR_EL12:
return MISCREG_SCTLR_EL1;
case MISCREG_CPACR_EL12:
return MISCREG_CPACR_EL1;
case MISCREG_ZCR_EL12:
return MISCREG_ZCR_EL1;
case MISCREG_TTBR0_EL12:
return MISCREG_TTBR0_EL1;
case MISCREG_TTBR1_EL12:
return MISCREG_TTBR1_EL1;
case MISCREG_TCR_EL12:
return MISCREG_TCR_EL1;
case MISCREG_SPSR_EL12:
return MISCREG_SPSR_EL1;
case MISCREG_ELR_EL12:
return MISCREG_ELR_EL1;
case MISCREG_AFSR0_EL12:
return MISCREG_AFSR0_EL1;
case MISCREG_AFSR1_EL12:
return MISCREG_AFSR1_EL1;
case MISCREG_ESR_EL12:
return MISCREG_ESR_EL1;
case MISCREG_FAR_EL12:
return MISCREG_FAR_EL1;
case MISCREG_MAIR_EL12:
return MISCREG_MAIR_EL1;
case MISCREG_AMAIR_EL12:
return MISCREG_AMAIR_EL1;
case MISCREG_VBAR_EL12:
return MISCREG_VBAR_EL1;
case MISCREG_CONTEXTIDR_EL12:
return MISCREG_CONTEXTIDR_EL1;
case MISCREG_CNTKCTL_EL12:
return MISCREG_CNTKCTL_EL1;
// _EL02 registers
case MISCREG_CNTP_TVAL_EL02:
return MISCREG_CNTP_TVAL_EL0;
case MISCREG_CNTP_CTL_EL02:
return MISCREG_CNTP_CTL_EL0;
case MISCREG_CNTP_CVAL_EL02:
return MISCREG_CNTP_CVAL_EL0;
case MISCREG_CNTV_TVAL_EL02:
return MISCREG_CNTV_TVAL_EL0;
case MISCREG_CNTV_CTL_EL02:
return MISCREG_CNTV_CTL_EL0;
case MISCREG_CNTV_CVAL_EL02:
return MISCREG_CNTV_CVAL_EL0;
default:
return misc_reg;
return misc_reg;
}
/*should not be accessible */
return misc_reg;
}
RegVal