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cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd

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This is aligning with the name of the generated memory requests

Change-Id: Ifdfa01477abf7ff597dce3b5cff78f9a27fdcbcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-04-01 21:04:14 +01:00
parent 05f1975832
commit 39ed6e0373
13 changed files with 23 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/arm/insts/tme64ruby.cc
View File

@@ -77,7 +77,7 @@ Tstart64::initiateAcc(ExecContext *xc,
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
fault = xc->initiateSpecialMemCmd(memAccessFlags);
fault = xc->initiateMemMgmtCmd(memAccessFlags);
}
return fault;
@@ -175,7 +175,7 @@ Tcancel64::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Request::Flags memAccessFlags =
Request::STRICT_ORDER|Request::PHYSICAL|Request::HTM_CANCEL;
fault = xc->initiateSpecialMemCmd(memAccessFlags);
fault = xc->initiateMemMgmtCmd(memAccessFlags);
return fault;
}
@@ -231,7 +231,7 @@ MicroTcommit64::initiateAcc(ExecContext *xc,
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
fault = xc->initiateSpecialMemCmd(memAccessFlags);
fault = xc->initiateMemMgmtCmd(memAccessFlags);
return fault;
}

2
src/arch/arm/isa/insts/data64.isa
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@@ -383,7 +383,7 @@ let {{
Request::Flags memAccessFlags =
Request::STRICT_ORDER | Request::TLBI;
fault = xc->initiateSpecialMemCmd(memAccessFlags);
fault = xc->initiateMemMgmtCmd(memAccessFlags);
PendingDvm = true;
}

2
src/arch/arm/isa/insts/misc64.isa
View File

@@ -188,7 +188,7 @@ let {{
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
fault = xc->initiateSpecialMemCmd(memAccessFlags);
fault = xc->initiateMemMgmtCmd(memAccessFlags);
PendingDvm = false;
}

2
src/cpu/checker/cpu.hh
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@@ -242,7 +242,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
};
Fault
initiateSpecialMemCmd(Request::Flags flags) override
initiateMemMgmtCmd(Request::Flags flags) override
{
panic("not yet supported!");
return NoFault;

4
src/cpu/exec_context.hh
View File

@@ -144,13 +144,13 @@ class ExecContext
}
/**
* Initiate a Special memory command with no valid address.
* Initiate a memory management command with no valid address.
* Currently, these instructions need to bypass squashing in the O3 model
* Examples include HTM commands and TLBI commands.
* e.g. tell Ruby we're starting/stopping a HTM transaction,
* or tell Ruby to issue a TLBI operation
*/
virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0;
virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0;
/**
* For atomic-mode contexts, perform an atomic memory write operation.

4
src/cpu/minor/exec_context.hh
View File

@@ -116,9 +116,9 @@ class ExecContext : public gem5::ExecContext
}
Fault
initiateSpecialMemCmd(Request::Flags flags) override
initiateMemMgmtCmd(Request::Flags flags) override
{
panic("ExecContext::initiateSpecialMemCmd() not implemented "
panic("ExecContext::initiateMemMgmtCmd() not implemented "
" on MinorCPU\n");
return NoFault;
}

2
src/cpu/o3/dyn_inst.cc
View File

@@ -410,7 +410,7 @@ DynInst::initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
}
Fault
DynInst::initiateSpecialMemCmd(Request::Flags flags)
DynInst::initiateMemMgmtCmd(Request::Flags flags)
{
const unsigned int size = 8;
return cpu->pushRequest(

2
src/cpu/o3/dyn_inst.hh
View File

@@ -397,7 +397,7 @@ class DynInst : public ExecContext, public RefCounted
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
const std::vector<bool> &byte_enable) override;
Fault initiateSpecialMemCmd(Request::Flags flags) override;
Fault initiateMemMgmtCmd(Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,

4
src/cpu/simple/atomic.hh
View File

@@ -224,9 +224,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU
override;
Fault
initiateSpecialMemCmd(Request::Flags flags) override
initiateMemMgmtCmd(Request::Flags flags) override
{
panic("initiateSpecialMemCmd() is for timing accesses, and "
panic("initiateMemMgmtCmd() is for timing accesses, and "
"should never be called on AtomicSimpleCPU.\n");
}

9
src/cpu/simple/base.hh
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@@ -191,14 +191,13 @@ class BaseSimpleCPU : public BaseCPU
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/**
* Special memory commands such as hardware transactional memory
* commands (HtmCmds) or TLBI commands, e.g. start a
* transaction and commit a transaction, are memory operations but are
* Memory management commands such as hardware transactional memory
* commands or TLB invalidation commands are memory operations but are
* neither really (true) loads nor stores.
* For this reason the interface is extended,
* and initiateSpecialMemCmd() is used to instigate the command.
* and initiateMemMgmtCmd() is used to instigate the command.
*/
virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0;
virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0;
};

4
src/cpu/simple/exec_context.hh
View File

@@ -446,9 +446,9 @@ class SimpleExecContext : public ExecContext
}
Fault
initiateSpecialMemCmd(Request::Flags flags) override
initiateMemMgmtCmd(Request::Flags flags) override
{
return cpu->initiateSpecialMemCmd(flags);
return cpu->initiateMemMgmtCmd(flags);
}
/**

4
src/cpu/simple/timing.cc
View File

@@ -1216,7 +1216,7 @@ TimingSimpleCPU::printAddr(Addr a)
}
Fault
TimingSimpleCPU::initiateSpecialMemCmd(Request::Flags flags)
TimingSimpleCPU::initiateMemMgmtCmd(Request::Flags flags)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@@ -1257,7 +1257,7 @@ TimingSimpleCPU::initiateSpecialMemCmd(Request::Flags flags)
DPRINTF(HtmCpu, "HTMcancel htmUid=%u\n",
t_info.getHtmTransactionUid());
else
panic("initiateSpecialMemCmd: unknown HTM CMD");
panic("initiateMemMgmtCmd: unknown HTM CMD");
}
sendData(req, data, nullptr, true);

2
src/cpu/simple/timing.hh
View File

@@ -325,7 +325,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void finishTranslation(WholeTranslationState *state);
/** hardware transactional memory & TLBI operations **/
Fault initiateSpecialMemCmd(Request::Flags flags) override;
Fault initiateMemMgmtCmd(Request::Flags flags) override;
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
HtmFailureFaultCause) override;