From 39ed6e03734afb4a16afd11294fca3673d8ced7b Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 1 Apr 2022 21:04:14 +0100 Subject: [PATCH] cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd This is aligning with the name of the generated memory requests Change-Id: Ifdfa01477abf7ff597dce3b5cff78f9a27fdcbcc Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58511 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/insts/tme64ruby.cc | 6 +++--- src/arch/arm/isa/insts/data64.isa | 2 +- src/arch/arm/isa/insts/misc64.isa | 2 +- src/cpu/checker/cpu.hh | 2 +- src/cpu/exec_context.hh | 4 ++-- src/cpu/minor/exec_context.hh | 4 ++-- src/cpu/o3/dyn_inst.cc | 2 +- src/cpu/o3/dyn_inst.hh | 2 +- src/cpu/simple/atomic.hh | 4 ++-- src/cpu/simple/base.hh | 9 ++++----- src/cpu/simple/exec_context.hh | 4 ++-- src/cpu/simple/timing.cc | 4 ++-- src/cpu/simple/timing.hh | 2 +- 13 files changed, 23 insertions(+), 24 deletions(-) diff --git a/src/arch/arm/insts/tme64ruby.cc b/src/arch/arm/insts/tme64ruby.cc index 3ddc7357ff..b35433aef1 100644 --- a/src/arch/arm/insts/tme64ruby.cc +++ b/src/arch/arm/insts/tme64ruby.cc @@ -77,7 +77,7 @@ Tstart64::initiateAcc(ExecContext *xc, memAccessFlags = memAccessFlags | Request::NO_ACCESS; } - fault = xc->initiateSpecialMemCmd(memAccessFlags); + fault = xc->initiateMemMgmtCmd(memAccessFlags); } return fault; @@ -175,7 +175,7 @@ Tcancel64::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const Request::Flags memAccessFlags = Request::STRICT_ORDER|Request::PHYSICAL|Request::HTM_CANCEL; - fault = xc->initiateSpecialMemCmd(memAccessFlags); + fault = xc->initiateMemMgmtCmd(memAccessFlags); return fault; } @@ -231,7 +231,7 @@ MicroTcommit64::initiateAcc(ExecContext *xc, memAccessFlags = memAccessFlags | Request::NO_ACCESS; } - fault = xc->initiateSpecialMemCmd(memAccessFlags); + fault = xc->initiateMemMgmtCmd(memAccessFlags); return fault; } diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 5cf8b8af76..922e92358e 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -383,7 +383,7 @@ let {{ Request::Flags memAccessFlags = Request::STRICT_ORDER | Request::TLBI; - fault = xc->initiateSpecialMemCmd(memAccessFlags); + fault = xc->initiateMemMgmtCmd(memAccessFlags); PendingDvm = true; } diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index f98d8949b0..abe30fce63 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -188,7 +188,7 @@ let {{ memAccessFlags = memAccessFlags | Request::NO_ACCESS; } - fault = xc->initiateSpecialMemCmd(memAccessFlags); + fault = xc->initiateMemMgmtCmd(memAccessFlags); PendingDvm = false; } diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index cdb7f19a51..2ca32e6ad9 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -242,7 +242,7 @@ class CheckerCPU : public BaseCPU, public ExecContext }; Fault - initiateSpecialMemCmd(Request::Flags flags) override + initiateMemMgmtCmd(Request::Flags flags) override { panic("not yet supported!"); return NoFault; diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index ece0c9ca04..5fb2cac6f5 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -144,13 +144,13 @@ class ExecContext } /** - * Initiate a Special memory command with no valid address. + * Initiate a memory management command with no valid address. * Currently, these instructions need to bypass squashing in the O3 model * Examples include HTM commands and TLBI commands. * e.g. tell Ruby we're starting/stopping a HTM transaction, * or tell Ruby to issue a TLBI operation */ - virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0; + virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0; /** * For atomic-mode contexts, perform an atomic memory write operation. diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index c95550fca5..d9cf75ffac 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -116,9 +116,9 @@ class ExecContext : public gem5::ExecContext } Fault - initiateSpecialMemCmd(Request::Flags flags) override + initiateMemMgmtCmd(Request::Flags flags) override { - panic("ExecContext::initiateSpecialMemCmd() not implemented " + panic("ExecContext::initiateMemMgmtCmd() not implemented " " on MinorCPU\n"); return NoFault; } diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc index 8eb270a180..0b9a900446 100644 --- a/src/cpu/o3/dyn_inst.cc +++ b/src/cpu/o3/dyn_inst.cc @@ -410,7 +410,7 @@ DynInst::initiateMemRead(Addr addr, unsigned size, Request::Flags flags, } Fault -DynInst::initiateSpecialMemCmd(Request::Flags flags) +DynInst::initiateMemMgmtCmd(Request::Flags flags) { const unsigned int size = 8; return cpu->pushRequest( diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index d4ddb33627..37f6c3951a 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -397,7 +397,7 @@ class DynInst : public ExecContext, public RefCounted Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector &byte_enable) override; - Fault initiateSpecialMemCmd(Request::Flags flags) override; + Fault initiateMemMgmtCmd(Request::Flags flags) override; Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index d7ab9c2f07..6fd790ee2f 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -224,9 +224,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU override; Fault - initiateSpecialMemCmd(Request::Flags flags) override + initiateMemMgmtCmd(Request::Flags flags) override { - panic("initiateSpecialMemCmd() is for timing accesses, and " + panic("initiateMemMgmtCmd() is for timing accesses, and " "should never be called on AtomicSimpleCPU.\n"); } diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 4949ebc8d5..4a56c74f18 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -191,14 +191,13 @@ class BaseSimpleCPU : public BaseCPU void unserializeThread(CheckpointIn &cp, ThreadID tid) override; /** - * Special memory commands such as hardware transactional memory - * commands (HtmCmds) or TLBI commands, e.g. start a - * transaction and commit a transaction, are memory operations but are + * Memory management commands such as hardware transactional memory + * commands or TLB invalidation commands are memory operations but are * neither really (true) loads nor stores. * For this reason the interface is extended, - * and initiateSpecialMemCmd() is used to instigate the command. + * and initiateMemMgmtCmd() is used to instigate the command. */ - virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0; + virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0; }; diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 6f4e26bbf8..443939c661 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -446,9 +446,9 @@ class SimpleExecContext : public ExecContext } Fault - initiateSpecialMemCmd(Request::Flags flags) override + initiateMemMgmtCmd(Request::Flags flags) override { - return cpu->initiateSpecialMemCmd(flags); + return cpu->initiateMemMgmtCmd(flags); } /** diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9e29cded2b..9ce71408d5 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1216,7 +1216,7 @@ TimingSimpleCPU::printAddr(Addr a) } Fault -TimingSimpleCPU::initiateSpecialMemCmd(Request::Flags flags) +TimingSimpleCPU::initiateMemMgmtCmd(Request::Flags flags) { SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -1257,7 +1257,7 @@ TimingSimpleCPU::initiateSpecialMemCmd(Request::Flags flags) DPRINTF(HtmCpu, "HTMcancel htmUid=%u\n", t_info.getHtmTransactionUid()); else - panic("initiateSpecialMemCmd: unknown HTM CMD"); + panic("initiateMemMgmtCmd: unknown HTM CMD"); } sendData(req, data, nullptr, true); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 3dbdcad8c9..ca6c0e26a3 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -325,7 +325,7 @@ class TimingSimpleCPU : public BaseSimpleCPU void finishTranslation(WholeTranslationState *state); /** hardware transactional memory & TLBI operations **/ - Fault initiateSpecialMemCmd(Request::Flags flags) override; + Fault initiateMemMgmtCmd(Request::Flags flags) override; void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause) override;