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arch-x86: Specialize LTR for 64 bit mode.

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Like LDT descriptors, the TR descriptors are 128 bits in 64 bit mode,
and only 64 bits in other modes.

Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55886
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2022-01-23 23:16:18 -08:00
parent 013a90c969
commit cd4c295a22
2 changed files with 41 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View File

@@ -52,7 +52,10 @@
0x0: Inst::LLDT_64(Ew);
default: Inst::LLDT(Ew);
}
0x3: Inst::LTR(Ew);
0x3: decode MODE_SUBMODE {
0x0: Inst::LTR_64(Ew);
default: Inst::LTR(Ew);
}
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
//0x6: jmpe_Ev(); // IA-64

40
src/arch/x86/isa/insts/system/segmentation.py
View File

@@ -157,7 +157,7 @@ def macroop LIDT_16_P
wrlimit idtr, t1
};
def macroop LTR_R
def macroop LTR_64_R
{
.serialize_after
chks reg, t0, TRCheck
@@ -174,7 +174,7 @@ def macroop LTR_R
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_M
def macroop LTR_64_M
{
.serialize_after
ld t5, seg, sib, disp, dataSize=2
@@ -192,7 +192,7 @@ def macroop LTR_M
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_P
def macroop LTR_64_P
{
.serialize_after
rdip t7
@@ -211,6 +211,40 @@ def macroop LTR_P
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_R
{
.serialize_after
chks reg, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
chks reg, t1, TSSCheck
wrdl tr, t1, reg
limm t5, (1 << 9)
or t1, t1, t5
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_M
{
.serialize_after
ld t5, seg, sib, disp, dataSize=2
chks t5, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
chks t5, t1, TSSCheck
wrdl tr, t1, t5
limm t5, (1 << 9)
or t1, t1, t5
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_P
{
panic "LTR in non-64 bit mode doesn't support RIP addressing."
};
def macroop LLDT_64_R
{
.serialize_after