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dev-amdgpu: Always mark interrupts enabled

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The driver will check this bit is set after initializing IPs. Currently
the MMIO trace will cause this bit to be set at the correct time,
however this is not portable access different ROCm versions. Therefore
we modify the value to always set the bit indicating interrupts are
enabled.

Change-Id: Iae0baf1936720fbe9835ae4acadbf1b3bdc52896
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57530
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2021-11-04 10:06:44 -05:00
parent dd90417211
commit c8518e486d
1 changed files with 14 additions and 0 deletions
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14
src/dev/amdgpu/amdgpu_device.cc
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@@ -212,6 +212,20 @@ AMDGPUDevice::readMMIO(PacketPtr pkt, Addr offset)
mmioReader.readFromTrace(pkt, MMIO_BAR, offset);
switch (aperture) {
case NBIO_BASE:
switch (aperture_offset) {
// This is a PCIe status register. At some point during driver init
// the driver checks that interrupts are enabled. This is only
// checked once, so if the MMIO trace does not exactly line up with
// what the driver is doing in gem5, this may still have the first
// bit zero causing driver to fail. Therefore, we always set this
// bit to one as there is no harm to do so.
case 0x3c: // mmPCIE_DATA2 << 2
uint32_t value = pkt->getLE<uint32_t>() | 0x1;
DPRINTF(AMDGPUDevice, "Marking interrupts enabled: %#lx\n", value);
pkt->setLE<uint32_t>(value);
break;
} break;
case GRBM_BASE:
gpuvm.readMMIO(pkt, aperture_offset >> GRBM_OFFSET_SHIFT);
break;