The purpose of the gem5 components library is to provide gem5 users a
standard set of common and useful gem5 components pre-built to add to
their experiments. The gem5 components library adopts a modular
architecture design with the goal of components being easy to add and
remove from designs, and extendable as needed. E.g., any Memory system
should be interchangable with any other, and if not a helpful error
messages should be raised.
Examples of using the gem5 components library can be found in
`configs/example/components-library`.
Important Disclaimer:
This is a pre-alpha release of the gem5 components library. The purpose
of this release is to get some community feedback on this new component
of gem5. Though some testing has been done, we expect regular fixes and
improvements until this is in a stable state.
The components library has been formatted with Python Black; typing has
been checked with MyPy; and the library has been tested with the scripts
in `configs/example/components-libary`. More rigorous tests are to be
added in future revisions.
More detailed documentation will appear in future revisions.
Jira Ticket outlining TODOs and known bugs can be found here:
https://gem5.atlassian.net/browse/GEM5-648
Change-Id: I3492ec4a6d8c59ffbae899ce8e87ab4ffb92b976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47466
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This patch adds support for a gfx902 Vega APU, ripping the
appropriate values for device_id from the ROCm Thunk
(src/topology.c).
Note: gfx902 isn't officially supported by ROCm. This
means that it may not work for all programs. In particular,
rocBLAS is incompatible with gfx902, so anything that uses
rocBLAS won't be able to run with gfx902.
Change-Id: I48893e7cc9c7e52275fdfd22314f371a9db8e90a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47530
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ROCm determines if a device is a dGPU in two ways. The first
is by looking at the device ID. The second is through a flag that
gets set only if the reported cpu_cores_count is 0.
If these don't agree, ROCm breaks when doing memory operations.
Previously, cpu_cores_count was non-zero on the Fiji config.
This patch sets it to 0 to appease ROCm
Change-Id: I0fd0ce724f491ed6a4598188b3799468668585f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47525
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
ROCm 4 iterates through the mem_banks to find an appropriate place to
allocate memory. Previously, Carrizo didn't have any mem_banks, which
resulted in the ROCm 4 runtime erroring out, as it didn't know where to
allocate memory.
The implementation is fairly similar to the implementation used for the
Fiji or Vega configs
Change-Id: I5bb4e89657d44c6cb690fd224ee1bf1d4d6cf2a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46240
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Commit 2c75e58cac ("sim,cpu: Move the remote GDB stub
into the workload.") moved "wait_for_remote_gdb" to the
Workload class. That breaks se.py since it continues to
rely on that being a property of BaseCPU. This ensures
that the property is now set via the current Workload
instance instead.
Also, owing to its boolean nature, the argument should
ideally not expect any additional values. Hence, it is
associated with the "store_true" action.
Change-Id: I4a00b29d283df36ebf833c9125651cd6deb52a4f
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47360
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The flow for Full System amdgpu is the use KVM to boot linux and begin
loading the driver module. However, the amdgpu module requires reading
the VGA ROM located at 0xc0000 in X86. KVM does not support having a
small 128KiB hole at this location, therefore we take a checkpoint and
switch to a timing CPU to continue loading the drivers before the VGA
ROM is read.
This creates a checkpoint just before the first MMIOs. This is indicated
by three interrupts being sent to the PCI device. After three interrupts
in a row are counted a checkpoint exit event occurs. The interrupt
counter is reset if a non-interrupt PCI read is seen.
Change-Id: I23b320abe81ff6e766cb3f604eca2979339938e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46161
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
In PathSearchFunc.__call__(), filename is the name of the file
while filepath contains the relative path to the missing file
relative to $M5_PATH.
Outputing the filepath in the error message makes the error
message more useful as it provides the expected location of
the file as well as the name of the file.
Change-Id: I5f1fdb9e48ac9ae59a26d33331a4a40bc9ff9acd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45105
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ACPI's MADT describes the interrupt system of a processor/system and
partially replaces the Intel MP tables. The config now simply adds the
ACPI variant, so an OS can use either Intel MP or ACPI for interrupt
configuration.
Change-Id: Ie3d293aac0925666f7661a03eab10218f04c8d0c
Signed-off-by: Maximilian Stein <m@steiny.biz>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42825
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This is an initial configuration capable of booting Linux and
registering a PCI device which registers as an AMD Vega 10 (Frontier
Edition) GPU. It it loosely based on the the example/fs.py and gem5 book
full system example scripts. The top-level file is meant to be modular
such that convenience scripts can be created to set arguments
automatically and then call the main run function.
This will evolve over time as more full-system GPU components are added
and the network topology needed for disjoint address spaces is created
for the VIPER protocol.
Change-Id: I7002213ca8de5eb73919e49fb11840a688744012
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44907
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The prior example config for FS fails SMP boot on the KVMX86CPU.
These updates incorporate logic x86-boot-tests/system/
[system.py|run_exit.py] as well as configs/example/arm/
fs_bigLITTLE.py to enable both single processor and SMP boot.
Each KVM VM now uses its own eventq and a non-zero sim_quantum.
Change-Id: I9c73a2f6f2ca604aecd31f45570423c58f85020f
Signed-off-by: Kevin Loughlin <kevlough@umich.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41602
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Viper is checking for the dma's type before making the port assignment.
In FullSystem mode the IDE device is a PortRef and does not have an
attribute 'type.' This handles the various types a bit better and
ensures that IDE device, the protocol tester, and upcoming DMA devices
related to FullSystem can be added.
Change-Id: I6879b25c6aabbbc22b0ee8dc9cbfec6399f70daa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44806
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
GPUCoalescers in FullSystem mode should not be connected to the piobus
since they reside on a completely different RubyPort. There is also no
concept of IO requests from GPU so any request attempting to use the
default port (pio) should fatal. Further, coalescers do not implement
the connectIOPorts function.
This avoids coalescers by checking is_cpu_sequencer, which I believe is
the purpose of that boolean.
Change-Id: I482dd631292ca20e3bcd856489376f9b38457200
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44805
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
GPU MTYPE is currently set using a global config passed to the
PACoalescer. This patch enables MTYPE to be set by the shader on a
per-request bases. In real hardware, the MTYPE is extracted from a
GPUVM PTE during address translation. However, our current simulator
only models x86 page tables which do not have the appropriate bits for
GPU MTYPES. Rather than hacking non-x86 bits into our x86 page table
models, this patch instead keeps an interval tree of all pages that
request custom MTYPES in the driver itself. This is currently
only used to map host pages to the GPU as uncacheable, but is easily
extensible to other MTYPES.
Change-Id: I7daab0ffae42084b9131a67c85cd0aa4bbbfc8d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42216
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
There was a merge error caused by new options being added to this script
while all scripts were being converted from optparse. This fixes the
error.
This also removes the mostly unused setOption / getOption as you can
directly assign a value to an argument after parsing
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba5f0fbf5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44785
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The --restore_simpoint_checkpoint option is a boolean;
however if no default value is supplied, optparse sets the
default value to None
This is not valid for argparse. Argparse recognizes the store_true
action and it is automatically treating the option as a boolean,
hence providing a default=False instead of default=None
Change-Id: I6b09edf6911be71a06001730be1232a1b5c8482c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44765
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
New topology ripped from Fiji to support dGPU. A dGPU flag is added to
the config which is propogated to the driver. The emulated driver is
now able to properly deal with dGPU ioctls and mmaps. For now, dGPU
physical memory is allocated from the host, but this is easy to change
once we get a GPU memory controller up and running.
Change-Id: I594418482b12ec8fb2e4018d8d0371d56f4f51c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42214
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.
Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This patch is adding an extra parameter to the Ruby.create_system
function. The idea is to remove any assumption about cpu configuration
in the ruby scripts.
At the moment the scripts are assuming a flat list of cpu assigned
to the system object. Unfortunately this is not standardized, as
some systems might empoloy a different layout of cpus, like grouping
them in cluster objects.
With this patch we are allowing client scripts to provide the cpu list
as an extra argument
This has the extra benefit of removing the indexing hack
if len(system.cpu) == 1:
which was present in most scripts
Change-Id: Ibc06b920273cde4f7c394d61c0ca664a7143cd27
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43287
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Changes:
1. RiscvBareMetal
The RiscvBareMetal class and API are preserved for backwards
compatibility, but the base class RiscvFSWorkload is removed
as it inherits from the Workload class. However, most needed
functionalities are already implemented in the KernelWorkload
class
2. RiscvLinux
The RiscvLinux class is added. A dtb filename can be specified
to be loaded to the corresponding memory address.
3. HiFive, Clint, Plic, Uart8250, VirtIOMMIO
Devicetree node generation function is added.
4. tlb, faults
Unnecessary includes of arch/riscv/fs_workload are removed.
Change-Id: Ia239b5614bd93d8e794330ead266f6121a4d13cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42053
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
The function had been introduced in the past when we needed to
instantiate either an ArmSystem or a LinuxArmSystem depending on the
workload. Now that the workload object has been introduced in gem5, we
always instantiate an ArmSystem in FS mode, hence we don't need a
function to generate the System object
Change-Id: I79ccf31087b84521cce32da71bc835ff202dc432
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43285
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
We are adding a controller method to MemInterface objects making
them able to generate the appropriate memory controller.
This will bring the following benefits
a) Semplification: It will simplify MemConfig.config_mem
b) Reusability: Scripts not using config_mem
won't have to duplicate the if...else checks
c) Modularity: Users will be able to define their own
dram interfaces without needing to handle the mem_ctrl
mapping in the shared MemConfig.py module
Change-Id: I4b836fd7c91675cf7aacc644f25989484d5be3ec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42074
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Changed format from yaml to plain python. The new py configuration
file, when provided, must specialize the CHI node types defined in
configs/ruby/CHI_config.py (moved from configs/ruby/CHI.py). This
is required in order to setup the node->router bindings when the
CustomMesh topology is used.
See configs/example/noc_config/2x4.py (replaces
configs/example/noc_config/2x4.yaml) for an example.
--noc-config was also renamed to --chi-config, since the CHI node types
can be fully specialized in the configuration file.
Change-Id: Ic0c5407dba3d2483d5c30634c115b5410a5228fd
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
