arch-arm, configs: Remove ArmITB/ArmDTB

Removing ArmITB and ArmDTB makes sense as it implies a fixed 2 TLBs
system; by using the generic ArmTLB class we open up to a more generic
configuration

This is also aligning to the other ISAs

Change-Id: Ifc5cf7c41484d4f45b14d1766833ad4c4f7e9e86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48143
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs/common/cores/arm/HPI.py

@@ -1328,15 +1328,9 @@ class HPI_FUPool(MinorFUPool):
         HPI_MiscFU() # 6
         ]
 
-class HPI_DTB(ArmDTB):
-    size = 256
-
-class HPI_ITB(ArmITB):
-    size = 256
-
 class HPI_MMU(ArmMMU):
-    itb = HPI_ITB()
-    dtb = HPI_DTB()
+    itb = ArmTLB(entry_type="instruction", size=256)
+    dtb = ArmTLB(entry_type="data", size=256)
 
 class HPI_WalkCache(Cache):
     data_latency = 4

src/arch/arm/ArmMMU.py

@@ -35,7 +35,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects.ArmTLB import ArmITB, ArmDTB, ArmStage2TLB
+from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
 from m5.objects.BaseMMU import BaseMMU
 from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
@@ -62,8 +62,9 @@ class ArmMMU(BaseMMU):
     type = 'ArmMMU'
     cxx_class = 'gem5::ArmISA::MMU'
     cxx_header = 'arch/arm/mmu.hh'
-    itb = ArmITB()
-    dtb = ArmDTB()
+
+    itb = ArmTLB(entry_type="instruction")
+    dtb = ArmTLB(entry_type="data")
 
     sys = Param.System(Parent.any, "system object parameter")
 

src/arch/arm/ArmTLB.py

@@ -51,9 +51,3 @@ class ArmTLB(BaseTLB):
 class ArmStage2TLB(ArmTLB):
     size = 32
     is_stage2 = True
-
-class ArmITB(ArmTLB):
-    entry_type = "instruction"
-
-class ArmDTB(ArmTLB):
-    entry_type = "data"