Commit Graph

5217 Commits

Author SHA1 Message Date
Jerin Joy
70fd98e807 arch-riscv: Added the Zbs bitmanip instructions
Added the bclr, bclri, bext, bexti, binv, binvi, bset, bseti
instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I126d659d973b250b642bd56b3b149f0ee6a3323e
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58632
Reviewed-by: Luming Wang <wlm199558@126.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-13 20:09:59 +00:00
Jerin Joy
df886bc8c1 arch-riscv: Added the Zbc bitmanip instructions
Added clmul, clmulh, clmulr instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I98dc76ddde052f56e32eabed12af87039def665b
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58631
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 20:09:59 +00:00
Jerin Joy
aee1622a6c arch-riscv: Added the Zba and Zbb bitmanip instructions
Zba instructions added:
add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw

Zbb instructions added:
andn, orn, xnor, clz, clzw, ctz, ctzw, cpop, cpopw, max, maxu, min,
minu, sext.b, sext.h, zext.h, rol, rolw, ror, rori, roriw, rorw, orc.b, rev8

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I056719f62eee89e0f085d1bf1fa182f9dfe614d8
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58630
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 20:09:59 +00:00
Yu-hsin Wang
72255064d6 fastmodel: Export more CortexR52 reset pin
Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 08:44:03 +00:00
Yu-hsin Wang
9dce95844a fastmodel: Export more CortexA76 reset pin
Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58812
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 08:44:03 +00:00
Gabe Black
7392cd470e scons: Ensure the fast model license count is always at least 1.
Even though the default value for the license count is 1, it seems that
if fast model is disabled, kconfig will set it to 0. When creating a
cycle using itertools over a list with zero elements, it will raise a
StopIteration.

Even though we don't actually try to build any fast model components
in that case, we do still set them up with a license slot. If the
cycle iterator is essentially broken, that will prevent that from
working and break the build.

This change forces the license count to be at least 1, even if fast
model is disabled and the license count may be set to 0 in the config.

Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 02:16:13 +00:00
Gabe Black
7cc384c308 arch: Eliminate the now unused read_code and write_code args.
Also eliminate the buildReadCode and buildWriteCode methods.

Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-12 23:50:52 +00:00
Gabe Black
cfe3ed47a6 arch-x86: Override make(Read|Write) instead of (read|write)_code.
Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-04-12 23:50:38 +00:00
Matthew Poremba
b64467025d arch-vega: Implement SOP2 S_MUL_HI instructions
Two new 32-bit signed and unsigned variants of S_MUL were added in
gfx900 which operate similar to S_MUL expect they shift the product by
32 bits after multiplication. Tested with Histogram HIP-Sample and
b+tree in rodinia 3.0 HIP port.

Change-Id: I1bed32b17ccda7aa47f3b59528eb3304912d3610
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58473
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 17:06:43 +00:00
Matthew Poremba
e3f65393fd dev-amdgpu,arch-vega: Implement TLB invalidation logic
Add logic to collect pointers to all GPU TLBs in full system. Implement
the invalid TLBs PM4 packet. The invalidate is done functionally since
there is really no benefit to simulate it with timing and there is no
support in the TLB to do so. This allow application with much larger
data sets which may reuse device memory pages to work in gem5 without
possibly crashing due to a stale translation being leftover in the TLB.

Change-Id: Ia30cce02154d482d8f75b2280409abb8f8375c24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58470
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 17:12:32 +00:00
Chia-You Chen
fb173e4d2c fastmodel: use global option 'num_jobs' instead of hardcoded number
Change-Id: I2d3f0855c8475cd44b1012fddf6b695621b2347f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58689
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-07 08:09:42 +00:00
Giacomo Travaglini
39ed6e0373 cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd
This is aligning with the name of the generated memory requests

Change-Id: Ifdfa01477abf7ff597dce3b5cff78f9a27fdcbcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-05 09:24:16 +00:00
Gabe Black
3b6ea3dfa9 scons: Add a tag for arm fastmodel and use it.
This avoids some python logic in the SConscript files, and explicit
references to the configuration system.

Change-Id: If6ee61bb8c23606859e60323b8ca2c5254dbdecc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58356
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
a5509c580c scons: Only warn about not finding fast model libs if it's enabled.
These warnings could be confusing and aren't useful if it's not.

Change-Id: Ie660f639a3d8ee3406153ceb771b1ba5d0df9225
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58355
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
3ae3b1a62f scons: Rework the fastmodel extract_var helper.
This helper extracts config variables and sets them up for use in
fast model tools. Rework this function for two purposes. First, ensure
that the ['CONF'] subdict is used consistently. It was used in one spot
in that function, but not anywhere else. Avoid those mistakes by
accessing the configuration dict only once, and then reusing the value.

Second, only print the values of those variables if they aren't empty.
That avoids extra log output for values which aren't set up and aren't
being used, while still exposing those values if they are set up. This
will print them even if they aren't being actively used, but are set up
and could be with other changes in the config.

Change-Id: Ia3ea76e6cb6b3347fd082112a1eaa8d594e06ca2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58354
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
4c6790ada6 scons: Stop the fast model project file parser from writing files.
PLY tries to write these little files into the SCons installation
directory, which it shouldn't even if it was allowed to. This avoids
a bunch of annoying messages about not having enough permission.

Change-Id: Ifd4eda9dd9f8518b3fd075e8a46de1b6c12c2127
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58353
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
d9a51177fc scons: Tone down a fast model error into a warning.
If a fast model static library can't be found, we should treat that as
a warning instead of an error, and pass back the original library name
so that it can at least be added and potentially come from somewhere
else.

In practice, this is important because gem5 will be configured by SCons
indirectly in the future, using kconfig based tools that SCons runs on
the user's behalf. If SCons is misconfigured or not configured, this
error can trip, preventing those tools from starting. That creates a
catch 22, since you'd need SCons to fix the config, and SCons can't
run because of the config.

We can avoid that problem by making SCons more lenient, so that it can
still run even if it doesn't find static libraries where it might have
expected to.

Change-Id: Iadfd823b61fe96b937c2650250487d290492f265
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58352
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
f56d43eadf scons: Get rid of an unused fast model variable.
This held the location of the license file, assuming it actually was a
license file and not a license server URL. If this variable was unset
because the fast model configuration parameters hadn't been set, then
the "File" would resolve to the local directory, and SCons would get
upset that you'd called the same path a directory and a file.

We can avoid this problem by just getting rid of this variable, since
it isn't used anyway.

Change-Id: I2ccda90b85f2c83c73816967d145e6bf45733f89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58351
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
886154b958 arch: Split up src/dest register ID creation.
This will allow us to selectively change the RegID of an operand to, for
instance, convert it to InvalidRegClass just as a source so it never
actually gets read.

Change-Id: I9f8117cbb2088f8150080f815cdb5cb84bd7218e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49747
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 23:52:35 +00:00
Gabe Black
e6c0ba97db scons: Put all config variables in an env['CONF'] sub-dict.
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 20:31:21 +00:00
Gabe Black
ee5c751fb5 arch-arm: Override makeRead and makeWrite in the ISA description.
Do that instead of using read_code or write_code.

Change-Id: I3f78f7a81c040336327e326b7196524ff6bedb10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49742
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 14:05:37 +00:00
Gabe Black
64d00f83c4 arch-x86: Ensure moving to %cs faults even in real mode.
It's always illegal to try to use the "mov" instruction to move a
selector into %cs. That was implemented for normal mov-s, but not for
the real mode version.

Change-Id: Ida8ec323fd7428ece583ad01cd5095d5f9630c9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55825
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
141d44b979 arch-x86: Consider CPL in the decoder logic.
For instructions which simply require CPL0 (vs. requiring CPL is < IOPL,
or something else more complicated), this change either switches their
format so that they check that value before being returned, or adds a
comment marking them as privileged if they aren't yet implemented.

This change also makes the mov to/from CR and DR instructions more
particular, and returns an undefined instruction if the CR or DR index
is invalid.

Change-Id: I367d87a380a47428d458bda2ceecc1b983644704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55891
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
00dd1b8ffc arch-x86: Add some formats for CPL0 only instructions.
These are essentially the same as the Inst and CondInst formats, except
it adds a CPL check. If the CPL check fails, a new instruction will be
returned which is only a vehicle for delivering a GP fault.

Change-Id: Ie1e7fb6a6c04082437c4d4a25adc3e03be09ac72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55890
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
283ea24c8e arch-x86: Expose the current CPL to the decoder.
This value is already floating around, and there is essentially no
overhead for exposing it to the decoder. With that value, we can handle
instructions which generically need to run at CPL0.

Some instructions have other more complicated permissions checks, like
that the CPL needs to have some relation to the IOPL. Those checks will
have to be implemented by the instructions themselves, since the decoder
can't factor in all possible state values.

Change-Id: Ie93f4f13aae002f69330606c515f369c5706c655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55889
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
cd4c295a22 arch-x86: Specialize LTR for 64 bit mode.
Like LDT descriptors, the TR descriptors are 128 bits in 64 bit mode,
and only 64 bits in other modes.

Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55886
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
013a90c969 arch-x86: Specialize LLDT for 64 bit and non-64 bit.
In 64 bit mode the LLDT has a 128 bit descriptor which takes up two
slots. In any other mode, the descriptor is still 64 bits.

Change-Id: I88d3758a66dec3482153df5ec08565427d6c9269
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55884
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Matthew Poremba
dd90417211 arch-vega: Bypass Ruby for functional page walks
Currently if a Ruby functional access fails to find an address in the
caches, it gives up. For functional page table walks we need to be able
to go all the way to memory. This adds a pointer to the system object
which allows the walker to get a pointer to device memory which can be
used to do a functional access directly to memory bypassing Ruby.

Change-Id: I0ead6e5e130a0d53021c44ae9221b167c6316ab2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57529
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 19:51:29 +00:00
Gabe Black
225b515f48 arch: Add a mechanism to override methods of the Operand classes.
The classes defined by the ISA description are actually just descriptors
which are used to make more specialized Operand classes, and then those
classes are instantiated to represent actual operands in a given
instruction. There they encode the actual index of the register, any
extensions used, etc.

To make defining operand types in the ISA more flexible and to take less
explicit machinery, this change defines a mechanism to allow overriding
individual methods of the operand class. This should for instance make
the read_code and write_code members of those classes unnecessary.

Change-Id: I1a1f787970ba56bd2884a80df4618a77eb454605
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49740
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-03-25 18:50:02 +00:00
Giacomo Travaglini
cee3f3286a arch-arm: _NS used in AArch32 if EL3 is AArch64
This is extending the behaviour of a previous patch [1] to EL0,
as CNTP is user (EL0) accessible

[1]: https://gem5-review.googlesource.com/9941

Change-Id: I54b493f32209ea53674e9025bbaba65e8134961e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58118
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 16:07:30 +00:00
Giacomo Travaglini
d982185d6e arch-arm: Fix ISA::redirectRegVHE method
This patch is fixing the redirectRegVHE method in the following
ways:

* Redirect AArch32 version of timer/counter registers
* Redirect _EL12 registers to _EL1
* Redirect _EL02 registers to _EL0
* Redirect CNTV_*_EL0 and CNTP_*_EL0 registers to
the Secure/Non-secure _EL2
* Redirect CNTVCT_EL0 to CNTPCT_EL0

Change-Id: I34eb317045b2d5a304a29ccf6e6440df68b2a279
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 16:07:30 +00:00
Giacomo Travaglini
4e1dda069e arch-arm: Move ISA::redirectRegVHE to .cc file
Change-Id: Icb773dc8bc5864d4ab02676783af66a828201253
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58116
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 16:07:30 +00:00
Giacomo Travaglini
2cab6b8d65 arch-arm: Fix RW permission access for _EL12 registers
_EL12 registers are supposed to be used in VHE only to access _EL1
registers. They are not accessible at EL1

Change-Id: I33c0a2b689e523d05712f0242da48e1b73580d6d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58114
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:51:56 +00:00
Giacomo Travaglini
1f568c26e4 arch-arm: Use uint64_t for AArch64 MiscReg operands
At the moment those operands are using uint32_t (uw) variables,
therefore losing the content of the 32 most significant bits

This is not a problem for some of them (like CPTR_EL2, CPTR_EL3)
as [63:32] bits are RES0 for now.
HCR_EL2 on the other hand holds meaningful bits in [63:32],
HCR_EL.E2H being a notable example. With this patch we
are then fixing a bug in VHE (which relies on E2H)

Change-Id: I3e31009ad3dec8d8ea1c1057a189f7dcc2c3a54c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58113
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:51:56 +00:00
Giacomo Travaglini
9e65dcaeec arch-arm, dev-arm: Implement EL2 Secure Virtual Timer
Change-Id: Ie4d4ff27b6375593ca4a6f6ae2a5e428ada943be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58112
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:51:37 +00:00
Giacomo Travaglini
e6797303c4 arch-arm, dev-arm: Implement EL2 Secure Physical Timer
Change-Id: I052f72695e670fad492079ab912268d05c797100
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58111
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:50:15 +00:00
Giacomo Travaglini
f1dce36f97 arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer
Change-Id: I0cc499e1309c35d946c5b9231846263f97bfa2b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-24 16:04:58 +00:00
Matthew Poremba
9cbdf75295 dev-amdgpu: Add VM class for apertures, TranslationGens
Create a VM class to reduce clutter in the amdgpu_device.* files. This
new file is in charge of reading/writting MMIOs related to VM contexts
and apertures. It also provides ranges checks for various apertures and
breaks out the MMIO interface so that there are not overloaded macro
definitions in the device MMIO methods.

The new translation generator classes for the various apertures are also
added to this class.

Change-Id: Ic224c1aa485685685b1136a46eed50bcf99d2350
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53066
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-24 14:59:57 +00:00
Gabe Black
c11dc40f06 arch-arm,base: Use SourceLib() in a few simple spots.
There are a couple places where SourceLib(), an interface to SCons's
LIB variable that respects tags, can be used simply in existing
SConscripts. Do that so that SourceLib is used, and as an example if
someone wants to see it in action.

Change-Id: Idb27da17724990093252b710f5f9fde8351a4bc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58070
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-23 20:39:28 +00:00
Luming Wang
b3f1e5f9d7 sim-se: add getrandom() syscall support
getrandom() was introduced in version 3.17 of the Linux kernel.
This commit implements getrandom() for Gem5 SE mode.

Change-Id: I86bfeee52048184dbf72330284933b70daab5850
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57809
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-03-22 02:05:32 +00:00
Gabe Black
36618ad057 arch-x86: Add some missing checks to STI and CLI.
Also make sure those instructions won't truncate the flags register.

Change-Id: Id55a4454480cd20ca462c08b93043254a9962dfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55892
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:38:12 +00:00
Gabe Black
4d970c59b5 arch:arch-x86: Fix style of some classes in the ucode assembler.
Change-Id: I13091707f4e44980ad9a3df022fbbfbafb1d0969
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56332
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:37:33 +00:00
Gabe Black
02cfdcfcc9 arch,arch-x86: Consolidate the add_microop method.
This was defined in the Micro_Container base class, and then again in
each subclass. The base definition was different and less complete than
the others, but the others were identical. Replace the base class
definition with the definition in the subclasses, and delete the ones in
the subclasses.

Change-Id: Ib2d1ce72958ec299115efb6efced2bd14c08467c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56330
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:36:57 +00:00
Gabe Black
e13d482f3f arch-x86: Remove __init__ from the X86MicrocodeRom class.
This is just setting up an empty dict the base class already sets up.

Change-Id: I22b00799f3424f9ced784c3d25771b979865e53d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56329
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:36:36 +00:00
Gabe Black
2eb3ac3880 arch: Switch to a new state to process macrocoop headers.
The "header" of a macroop definition is the part after "def rom" but
before the "{". This is pretty minimal now, but will be more complex
once macros are introduced.

Change-Id: I002d6501a015f46be6ae28b8d2a5e6064438da32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56328
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:36:20 +00:00
Gabe Black
8beab79f19 arch-x86: Use push_state in the microcode assembler.
Use push_state and pop_state in the microcode assembler to enter/exit
the params state. That will make that state usable in other contexts,
rather than forcing the lexer into the asm state afterwards.

Change-Id: Id80747db6e52a6f6f15ebe36ec54524fa3405581
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56327
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:36:20 +00:00
Gabe Black
9f0cb266cd arch-x86: Implement IntCSCheck for legacy mode.
Change-Id: Ic011b796cbccec030ffcb52ee4033ceaee6bf8fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56324
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-19 13:36:00 +00:00
Matthew Poremba
f64f05eff6 arch-vega: Mark global instructions executed as global
The executed_as field is currently not set for global memory
instructions. This results in the default of SC_NONE, causing the status
vector to be all zeros. The GM pipe sees this and completes the
instruction immediately rather than issuing memory requests. This is
fixed by marking the instruction as executed as SC_GLOBAL always. Flat
instructions use resolvedFlatSegment for this, however since global
instructions are known to be global we can set this field directly. This
results in the expected issuing of memory requests to GPU memory.

Change-Id: Ic23102853ccd49a41e2f083b7bb24f033dfed18a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57829
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-18 22:44:28 +00:00
Gabe Black
72d67e6426 arch-vega: Replace deprecated Stats namespace recently reintroduced.
The deprecated "Stats" namespace was recently reintroduced to the vega
TLB code. Replace it with the new statistics namespace.

Change-Id: Ie5daf288176ce7e8aadd27b84a70baf4cbc72dff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57949
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-18 20:19:37 +00:00
Giacomo Travaglini
d7854cce3b arch-arm: Implement DSB Shareable as a DVM op
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I52c965817dd9d70feca31d1ec2981ad3a090e6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56607
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-18 12:01:23 +00:00