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fastmodel: Export more CortexR52 reset pin

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Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Yu-hsin Wang
2022-04-08 18:26:48 +08:00
parent 9dce95844a
commit 72255064d6
8 changed files with 32 additions and 7 deletions
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2
src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
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@@ -114,6 +114,8 @@ class FastModelCortexR52Cluster(SimObject):
ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
top_reset = IntSinkPin('This signal resets timer and interrupt controller.')
dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross Trigger ' \
'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
"CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")

3
src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
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@@ -158,7 +158,8 @@ CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "spi") {
return evs->gem5_getPort(if_name, idx);
} else if (if_name == "ext_slave" || if_name == "top_reset") {
} else if (if_name == "ext_slave" || if_name == "top_reset" ||
if_name == "dbg_reset") {
assert(idx == InvalidPortID);
return evs->gem5_getPort(if_name, idx);
} else {

8
src/arch/arm/fastmodel/CortexR52/evs.cc
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@@ -96,9 +96,10 @@ template <class Types>
ScxEvsCortexR52<Types>::ScxEvsCortexR52(
const sc_core::sc_module_name &mod_name, const Params &p) :
Base(mod_name),
params(p),
ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
top_reset(p.name + ".top_reset", 0)
top_reset(p.name + ".top_reset", 0),
dbg_reset(p.name + ".dbg_reset", 0),
params(p)
{
for (int i = 0; i < CoreCount; i++)
corePins.emplace_back(new CorePins(this, i));
@@ -109,6 +110,7 @@ ScxEvsCortexR52<Types>::ScxEvsCortexR52(
}
top_reset.signal_out.bind(Base::top_reset);
dbg_reset.signal_out.bind(Base::dbg_reset);
clockRateControl.bind(this->clock_rate_s);
signalInterrupt.bind(this->signal_interrupt);
@@ -144,6 +146,8 @@ ScxEvsCortexR52<Types>::gem5_getPort(const std::string &if_name, int idx)
return this->ext_slave;
} else if (if_name == "top_reset") {
return this->top_reset;
} else if (if_name == "dbg_reset") {
return this->dbg_reset;
} else if (if_name == "spi") {
return *this->spis.at(idx);
} else if (if_name.substr(0, 3) == "ppi") {

10
src/arch/arm/fastmodel/CortexR52/evs.hh
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@@ -119,14 +119,16 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
std::vector<std::unique_ptr<ClstrInt>> spis;
CortexR52Cluster *gem5CpuCluster;
const Params &params;
AmbaTarget ext_slave;
SignalSender top_reset;
SignalSender dbg_reset;
CortexR52Cluster *gem5CpuCluster;
const Params &params;
public:
ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);

4
src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
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@@ -45,9 +45,12 @@ component CortexR52x1
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
// Reset signals.
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
// Clocks.
@@ -77,6 +80,7 @@ component CortexR52x1
slave port<Signal> poweron_reset[1];
slave port<Signal> halt[1];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[1];
slave port<ExportedClockRateControl> clock_rate_s

4
src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
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@@ -45,9 +45,12 @@ component CortexR52x2
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
// Reset signals.
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
// Clocks.
@@ -78,6 +81,7 @@ component CortexR52x2
slave port<Signal> poweron_reset[2];
slave port<Signal> halt[2];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[2];
slave port<ExportedClockRateControl> clock_rate_s

4
src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
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@@ -45,9 +45,12 @@ component CortexR52x3
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
// Reset signals.
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
// Clocks.
@@ -79,6 +82,7 @@ component CortexR52x3
slave port<Signal> poweron_reset[3];
slave port<Signal> halt[3];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[3];
slave port<ExportedClockRateControl> clock_rate_s

4
src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
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@@ -45,9 +45,12 @@ component CortexR52x4
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
// Reset signals.
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
// Clocks.
@@ -80,6 +83,7 @@ component CortexR52x4
slave port<Signal> poweron_reset[4];
slave port<Signal> halt[4];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[4];
slave port<ExportedClockRateControl> clock_rate_s