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arch-x86: Override make(Read|Write) instead of (read|write)_code.

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Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-08-22 00:18:47 -07:00
parent 4978bf8d5a
commit cfe3ed47a6
1 changed files with 18 additions and 9 deletions
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27
src/arch/x86/isa/operands.isa
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@@ -55,20 +55,29 @@ def operand_types {{
let {{
class IntReg(IntRegOp):
def __init__(self, idx, id, *args, **kwargs):
def __init__(self, idx, id, data_size='dataSize', *args, **kwargs):
super().__init__('uqw', idx, 'IsInteger', id, *args, **kwargs)
self.attrs['data_size'] = data_size
class PickedReg(IntReg):
def __init__(self, idx, id, size='dataSize'):
super().__init__(idx, id,
read_code='pick(xc->getRegOperand(this, %(op_idx)s), '
'%(reg_idx)s, ' + size + ')')
@overrideInOperand
def makeRead(self, predRead, op_idx):
return f'{self.base_name} = pick(xc->getRegOperand(' \
f'this, {op_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
def __init__(self, idx, id, data_size='dataSize'):
super().__init__(idx, id, data_size)
class SignedPickedReg(IntReg):
def __init__(self, idx, id, size='dataSize'):
super().__init__(idx, id,
read_code='signedPick(xc->getRegOperand(this, '
'%(op_idx)s), %(reg_idx)s, ' + size + ')')
@overrideInOperand
def makeRead(self, predRead, op_idx):
return f'{self.base_name} = signedPick(xc->getRegOperand(' \
f'this, {op_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
def __init__(self, idx, id, data_size='dataSize'):
super().__init__(idx, id, data_size)
class FloatReg(FloatRegOp):
def __init__(self, idx, id):