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arch-x86: Implement IntCSCheck for legacy mode.

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Change-Id: Ic011b796cbccec030ffcb52ee4033ceaee6bf8fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56324
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2022-01-26 08:39:35 -08:00
parent a8aa175c7f
commit 9f0cb266cd
1 changed files with 3 additions and 5 deletions
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8
src/arch/x86/isa/microops/regop.isa
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@@ -1533,14 +1533,12 @@ let {{
break;
}
case SegIntCSCheck:
if (m5reg.mode == LongMode) {
if (desc.type.codeOrData != 1) {
fault = std::make_shared<GeneralProtection>(selector);
} else if (m5reg.mode == LongMode) {
if (desc.l != 1 || desc.d != 0) {
fault = std::make_shared<GeneralProtection>(selector);
}
} else {
fault = std::make_shared<GenericISA::M5PanicFault>(
"Interrupt CS "
"checks not implemented in legacy mode.\\n");
}
break;
case SegTRCheck: