Commit Graph

18129 Commits

Author SHA1 Message Date
Matt Sinclair
3b48aa4d4c tests: fix bug in weekly regression
66a056b8 changed the weekly regression to use a single docker for
all GPU tests, to reduce how many times gem5 needed to be compiled.
However, in my local testing of that patch, gem5-resources was not
deleted until after the docker was created -- which causes a problem
when gem5-resources does not exist already from a prior run, since
the creation of the dockerfile requires it for HACC.  This commit
fixes this problem by moving the pull of gem5-resources to be before
anything else related to the GPU happens.

Change-Id: I006860204d03807d95628aa5dcf6e82d202fef9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51907
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-22 19:11:09 +00:00
Austin Harris
d2a684c5bd tests: Add a test for forking and switching cpus
This tests forking gem5 and simulating the child with a different cpu.
The test boots linux with the KVM cpu and then forks gem5. Each child
simulation switches to the specified cpu and simulates to completion
while the parents waits for the children to finish before also
simulating to completion.

Change-Id: I68d7515bf125c855eefc62ba4798cd7c745ef2b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50467
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-22 14:58:49 +00:00
Giacomo Travaglini
309e48c0cb arch-arm: Add fchmodat implementation to the Syscall Table
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I6ce4770aea0456423cf5a37171fbd8e4469b3e98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51748
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-10-22 13:51:16 +00:00
Giacomo Travaglini
16253e494e arch: Fixed Packed register view for VecPredReg
A bug in the VecPredRegContainer::as method was introduced by
a past commit [1]. The commit was not properly handling the case of
a Packed representation

If Packed == true -> NumElement = NumBits instead of
NumElements = NumBits / sizeof(VecElem)

This patch is fixing it

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/42000

Change-Id: I308769c3938d0fac84316936f732a6c383146484
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51867
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-22 11:50:29 +00:00
Gabe Black
645e315180 scons: Copy the value of "tags" before adding "add_tags" to it.
Otherwise the tags in "add_tags" are added into the original, modifying
it for the caller.

Change-Id: I6a82168d54f80ec9f919825edebe7f0ef154c5ae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51830
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-22 11:39:00 +00:00
Giacomo Travaglini
535963c2d0 arch-arm: Fix codying style in TableWalker descriptors
Change-Id: Ib46e937ace35cbd3dcae777956fa024195e2136c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51808
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-22 08:53:59 +00:00
Gabe Black
9f73802ea2 arch: Correct the direction of the arch->gem5 lib tag implication.
The arch implies gem5 lib, and not the other way around. Or in other
words, if, for example, x86 is the ISA, the having the tag 'x86 isa'
would imply that that file also has the tag 'gem5 lib'. Having the tag
'gem5 lib' would not imply 'x86 isa'.

This worked out because when testing for a single tag, we were using
with_any_tags, and 'gem5 lib' would expand to 'gem5 lib' and 'x86 isa'.
Then we would match files which were non-specific and used 'gem5 lib',
or files which had more specifically used 'x86 isa' only. Files which
used, for instance, 'arm isa', would not meet either criteria of the
implied "or".

Change-Id: I301d1bbbbcac1594371584d4b0d5d291b7b77fc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51827
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-10-21 19:57:33 +00:00
Gabe Black
741cb727ca scons: Resolve tags for source files as well as for filters.
The tags for source files need to be resolved as well as the tags for
the filters themselves.

For example, the 'x86 isa' tag could imply 'gem5 lib'. If we filter for
all files which include the tag 'gem5 lib', we would also want to get
all the files that used the tag 'x86 isa' by itself, since that would
imply 'gem5 lib' as well.

Change-Id: Ie513778cc5b8ac1f1893728b14e84cabdaabf0e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51828
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-10-21 19:57:12 +00:00
Matthew Poremba
5eb4f5fe11 configs: Breakup GPU_VIPER create_system code
In order to have more fine grained control over which SLICC controllers
are part of which Ruby network in a disjoint configuration, the
create_system function in GPU_VIPER is broken up into multiple construct
calls for each SLICC machine type in the protocol. By default this does
not change anything functionally. A future config will use the construct
calls to explicitly set which network (CPU or GPU) the controller is in.

Change-Id: Ic038b300c5c3732e96992ef4bfe14e43fa0ea824
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51847
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 17:07:26 +00:00
Giacomo Travaglini
2f88afdc52 sim-se: Implement fchmodat syscall
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Id3b738fa50d0739da5df856c87a8e172ec7a423a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51747
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 09:37:06 +00:00
Giacomo Travaglini
847f642f0e arch-arm: Add TxSZ to PageTableOps::index
This patch is adding the input address (IA) size (TSZ) to the
index method, as it is limiting the number of bits used to
determine the descriptor index from the input address

Change-Id: Ibc8f9ce94ea0ce06093bd90546ca1a906518b700
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51807
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 08:06:44 +00:00
Giacomo Travaglini
1b6c050ebf arch-arm, dev-arm: Use PageTableOps in Arm TableWalker
As the VMSA is shared between the CPU MMU and the SMMU, we move the
PageTableOps data structures to the arch/arm/pagetable.hh/cc sources.

Both MMUs will make use of them

Change-Id: I3a1113f6ef56f8d879aff2df50a01037baca82ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51672
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 08:06:44 +00:00
Jason Lowe-Power
526b03407a tests: Add RISC-V Ruby boot tests
Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51450
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-21 01:33:34 +00:00
Jason Lowe-Power
5dc776399d python,configs: Add Ruby support to RISC-V board
Take out guards stopping the RISC-V board from being configured with
Ruby and update the I/O config with a check for Ruby. Also, add a
comment in the example file that Ruby is now supported.

Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51449
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-21 01:33:34 +00:00
Jason Lowe-Power
14aece4d8f python: Generalize ruby components in library
The Ruby protocols in the components library had some special cases for
x86 that ended up breaking other ISAs (RISC-V in my testing). This
change generalizes those scripts slightly so they will work with both
x86 and RISC-V

Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51448
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-21 01:33:34 +00:00
Jason Lowe-Power
3e32fd3b33 mem-ruby: Add RISC-V atomic support to Ruby
RISC-V atomics carry a atomic functor that needs to be executed in the
cache hierarchy. To implement this in Ruby, we execute the functor in
the hitCallback function. Note that these functions are slightly
different than the atomic functions used in the GPU model and the GPU
coalescer even though they have similar semantics.

This change was tested with RISC-V Linux boot which has a few atomics
and linux boot finishes successfully. Previously, the boot got stuck
after the incorrect atomic operation.

Change-Id: I47a69c05ad9f4267d0220023289116e62b5231be
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51447
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-10-21 01:33:34 +00:00
Gabe Black
2af3045e17 cpu: Move FuncUnit.py, its .cc and StaticInstFlags.py above Return.
These two files can be used even with the NULL ISA since they don't
depend on anything that would require a NULL ISA specific definition.

Change-Id: Ie7d83fccf39218c40bd741c76a1c6c0ac7fe2f87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-20 23:32:33 +00:00
Gabe Black
f65a704296 arch: Only build GPU switching headers if building the GPU.
Otherwise, SCons may discover an include which is guarded with BUILD_GPU
(like GPUCoalescer in mem/ruby/profiler/Profiler.cc), but not understand
that BUILD_GPU is not true. It will then follow the includes and find
generated headers which it will then generate, specifically X86 headers
for X86TLB and X86Pagetable param structs.

If not using x86, for instance if building the NULL isa, it may not be
possible to generate those headers because those objects are not visible
to SCons.

Change-Id: I955d0ef6ffb146eeb99bb052d29abe835cac5d9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51829
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-20 22:44:08 +00:00
Jason Lowe-Power
8f33e9e34e python: Updates to improve debugging output
This changeset updates SimObject and Proxy so that certain errors are
easier to diagnose. In SimObject, the warn() statement could cause
another exception, so it's split into two statements. In Proxy, it is
helpful to know which attribute is referenced when there's a mistake.

Change-Id: I3704a247b8b40e18ffc5e4a6241a74829313c07e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51787
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-20 20:12:32 +00:00
Jason Lowe-Power
56494ed699 python: Add check to SimObject for __init__
When extending a SimObject by subclassing, if you don't call
`super().__init__()` you get a confusing infinite recursion error. The
infinite recursion occurs because SimObject overrides `__getattr__`. So,
if an attribute is accessed that is set in SimObject.__init__ but that
function hasn't been called there's a problem.

This patch adds another member variable to track if __init__ has been
called. This member variable is set to False in the *meta class*  so
that it will always be available, even if __init__ has not been called.
There is one check for whether init has been called in the __getattr__
function. This is where I have experienced prior issues. This function
could be called from other SimObject functions, if needed.

With this change, a helpful error is shown telling the user to be sure
to call super().__init__ in the specific class that is missing the call.

Note: I have been bitten by this an embarrassing number of times. A
helpful error message would have saved me many hours.

Change-Id: Id919c540b23fc2783e203ef625bce3000ba808a9
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51568
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-20 20:12:11 +00:00
Giacomo Travaglini
6d336c5635 arch-arm: Add futimesat implementation to the Syscall Table
Change-Id: I3096c5c1ed38cd4cfe9ca6e3c570f408557769eb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51060
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-20 15:10:45 +00:00
Giacomo Travaglini
1c708f76f1 sim-se: Implement futimesat syscall
Change-Id: I0cfb577b77663f8e4fac5c68633bdd69c4c8e2ea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51059
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-20 15:10:45 +00:00
Giacomo Travaglini
4808a22dae arch-arm: Add utimes implementation to the Syscall Table
Change-Id: If618bd4d746daa42e33ac91721ba2b23c6880bf6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51058
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-20 15:10:45 +00:00
Giacomo Travaglini
3627659ccb arch-arm: Add mknodat implementation to the Syscall Table
Change-Id: Ib01443f5304da511ff41010d35bdda71e20e3f93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51057
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-20 15:10:45 +00:00
Giacomo Travaglini
b4f73b8965 sim-se: Implement mknodat syscall
JIRA: https://gem5.atlassian.net/browse/GEM5-1098

Change-Id: Ic6b6b9350bcffdaed368373a6bffe4f9ece5feee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51056
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-20 15:10:45 +00:00
Giacomo Travaglini
a680b98eaf configs: Assign the host gid to the Process.gid in SE configs
Some syscalls (like chown) can make use of the current process group id
(gid) to setup file ownership. If we just provide the default fake gid
([1]) we will encounter some problems when executing the syscall on the
host.

Example (guest) program:

gid_t prc_gid = getgid();
int res = chown(..., prc_gid);

By assigning the host gid to the guest we are sure we can successfully
execute syscalls from the gem5 process

[1]: https://github.com/gem5/gem5/blob/v21.1.0.2/src/sim/Process.py#L52

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ia09f44916def03f68f7605d72f323f03ec71bbe1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51767
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-20 09:27:34 +00:00
Nathanael Premillieu
7eb8fb927f python: remove SimObject children on NULL assignment
Before this commit, on assigning NULL to an 'attr' that is a SimObject,
the corresponding children SimObject was not set to NULL.

This makes some SimObject being initialized in the c++ world
even if they are not needed.

This commit set the children to NULL in that case.

Change-Id: I2030d9d1b80c020fa28e50c0eca4f87b756763d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51647
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-20 07:13:46 +00:00
Matt Sinclair
66a056b828 tests: add HACC to weekly regression
This commit adds HACC (a GPU HPC workload) to the weekly regression
tests.  HACC requires a number of environment variables to be set, so
to avoid setting all of them manually, we use a specific Dockerfile for
it.  To avoid compiling gem5 once for this docker and once for the other
GPU tests in the weekly regression, this commit also updates the weekly
regression such that all GPU weekly regression tests use HACC's docker
for their tests.

Change-Id: I9adabbca01537f031cbc491ddf1d3e7dd155f3f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51708
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-20 01:31:40 +00:00
Gabe Black
73025695c7 scons: Use tags to gate ISA files and not env['TARGET_ISA'].
Change-Id: Ib81a4c570fbb050fa7d82919edacfed004c6800e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50336
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-19 20:41:03 +00:00
Gabe Black
9f92ec90ba configs,dev: Rename the riscv version of VirtIOMMIO with a Riscv prefix.
This device and the file it's in have the same name as one already
defined by arm. This is basically ok when those are mutually exclusive,
but can't coexist when both ISAs can be included at the same time. This
is because the file name would put them both under
m5.objects.VirtIOMMIO, and the name of the object itself would conflict
when importing * from m5.objects.

Change-Id: I558676b7d64cc68adb2d81b070a1816aa0bea6ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-10-19 20:41:03 +00:00
Bobby R. Bruce
0d1c80ccdb configs,tests: Add Ubuntu boot example for the gem5 library
Change-Id: I5d8c0f424e661123458c0d3d55159838d4fd951d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50888
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-19 17:27:00 +00:00
Bobby R. Bruce
06401fa80f configs,tests: Add "Hello world" example for the gem5 library
Change-Id: Ifeb33f5425952aac113a04f8e27306476a6fc381
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50887
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-19 17:27:00 +00:00
Gabe Black
305a81aae7 arch: Consolidate common debug flags.
Consolidate debug flags which are defined separately in multiple ISAs in
arch/SConscript instead. This will prevent conflicts when more than one
ISA can be compiled at a time.

Change-Id: I70862c403d19f04bbcbabd74dd751ca92d1ed942
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50334
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-19 10:53:44 +00:00
Gabe Black
04c9473551 scons: Make debug flags respect tags.
Debug flags can have their own tags which will apply to the .cc file
they create.

Change-Id: I16911252176a5a8df0e56c0e37a3c11b4cf1dd7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50333
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-10-19 10:53:44 +00:00
Gabe Black
038bf7075a scons: Use unions to prevent debug flag destruction.
When an object is a field in a union, it's the programmer's
resposibility to destroy it from the union's destructor. We can simply
neglect to do that and avoid having to use new to create the flags.

Also, we can define the flags as inline variables (a c++17 feature), and
then create a constexpr references to them. This lets us refer to debug
flags in constexpr objects, although we can't interact with them at, for
instance, construciton time or we'd lose our own constexpr-ness since
the actual object is not constexpr.

In c++20 we would hypothetically be able to use constexpr with new and
delete, but there may be additional restrictions that would make this
particular use impossible. Also this avoids leaking memory, which, even
though it's intentional, may confuse tools like valgrind.

Also, we need to ensure that all headers are included in some source
file so that they exist in the final executable, so that they show up in
the help, can be enabled/disabled, etc.

Change-Id: Ia43111d938e7af7140b1c17dd68135f426d0a1e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49783
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-19 10:53:44 +00:00
Giacomo Travaglini
1b2083fc53 arch-arm: Add mknod implementation to the Syscall Table
Change-Id: Ie5af5c4223e015d04aadda125f3131683a06463f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51055
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-19 08:48:49 +00:00
Giacomo Travaglini
dcf4e11a15 arch-arm: Add mkdirat implementation to the Syscall Table
Change-Id: I1323faf583b1dd1192515f6e598e1616dc14de11
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51054
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-19 08:48:49 +00:00
Giacomo Travaglini
a82146153a sim-se: Implement mkdirat syscall
JIRA: https://gem5.atlassian.net/browse/GEM5-1098

Change-Id: I0a9a5895ddbd337e055fe83f894d0aa67d705779
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51053
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-19 08:48:49 +00:00
Matt Sinclair
7ccb819665 tests: simplify weekly regression
DNNMark and LULESH were both cloning and removing gem5-resources as part
of their tests, since they were committed separately/in parallel.  Clean
this up so we only remove and pull gem5-resources once now in the weekly
regression script.

Change-Id: I5ab1410b0934bf20ed817e379f4e494aa53bfa44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51707
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-19 04:34:29 +00:00
Gabe Black
a1554370ff cpu: Eliminate the unused hasBranchTarget method in StaticInst.
This was once used to implement GDB single stepping back when it was
reimplemented for each ISA, but has not been used since 2014 when that
code was refactored.

Change-Id: If37ccfec2c43a33320d753c68892aa6fefd16b4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51531
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: ZHENGRONG WANG <seanyukigeek@gmail.com>
2021-10-19 00:48:36 +00:00
Giacomo Travaglini
6c9792d333 arch-arm: EL2&0 invalidations do not depend on VMID
When the PE is executing in host mode (HCR.E2H = HCR.TGE = 1)
The invalidation shouldn't depend on the current VMID

Change-Id: I3433485cc8f8dedb657139bcc3d71e05e9d7e4f1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51671
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
655349a9ca arch-arm: Use EL2&0 regime for invalidation only if EL2 enabled
Change-Id: I467a27e48d077cea5e56afae08f9e0e72f529cfc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51670
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
f49a15e00f arch-arm: Define a Lookup structure to simplify TLB code
The lookup/matching function signatures have been constantly amended to
include new parameters. We are replacing the parameter list with a
single lookup structure. This will make it easier to add new forms of
lookups and to propagate them through the MMU/TLB code

Change-Id: Ic45a64d778460b6d308551333c9dc230a02ecb6e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51669
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
b29349671c arch-arm: EL2/EL3 TLB invalidations should ignore the ASID
By using the TLBIMVAA class we invalidate for every ASID

Change-Id: Ie53747067275b01eab42d49b5fa518334a86ac53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51668
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
8fe7a740e3 arch-arm: Do not always print 0 stats in ArmTLB
We shouldn't print all TLB stats regardless of their value

For example there is no need to print the number of
read/write hits/misses/accesses in a instruction only TLB as
it will always inevitably be zero

With this patch we are flagging them as nozero, in order
to suppress their printing in the final stats file.
We are still printing them (regardless of their value) in the
unified TLB type

Change-Id: I54e57d856ceb451f6bacdd175a61768d030862aa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51667
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-18 13:47:18 +00:00
Matt Sinclair
118677218d mem-ruby: fix typo in GPU VIPER TCC comment
72ee6d1a fixed a deadlock in the GPU VIPER TCC.  However, it
inadvertently added a typo to the comments explaining the change.  This
commit fixes that.

Change-Id: Ibba835aa907be33fc3dd8e576ad2901d5f8f509c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51687
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-17 04:07:49 +00:00
Bobby R. Bruce
7455087ca4 python: Improve the print statements in downloader.py
Most importantly, these print statements now make clear to the user
where the resources are being downloaded to.

Change-Id: Id2661d2567a7ea5ee3157142dc91e814e3e2edaf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51370
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-15 18:21:33 +00:00
Bobby R. Bruce
a3f6cac410 python: Set a default resource dir to download to
Prior to this patch the downloader would download resources to the
user's pwd unless explictly stated otherwise. This patch checks the
environment variable `GEM5_RESOURCE_DIR` for a resource directory and if
this is not set, it will default to `~/.cache/gem5`.

Change-Id: I672479a37342d2a97e8ac6404775f3fd969b07b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51369
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-15 18:21:33 +00:00
Gabe Black
5c8c981cdd arch-sparc: Fix the build for SPARC.
The fp_enable_check mechanism was removed recently, but the removal was
only partial for SPARC which broke its build. This change completes the
removal by finishing the necessary code substitutions.

Change-Id: I3a6a6cd679b08556e5e4a2a2c4e98168ee7fe1fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51673
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-15 10:13:42 +00:00
Gabe Black
18cb3af215 cpu,tests: Replace the deprecated Stats namespace with statistics.
The gups traffic generator was checked in recently and uses the
deprecated namespace. This change updates it.

Change-Id: I5e6f593aac086e6ef251f11fc50c0e3d3e545d06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51674
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-15 09:39:46 +00:00