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Author SHA1 Message Date
Éder F. Zulian
ed5b0c30fe doc improved 2018-07-20 09:42:04 +02:00
Éder F. Zulian
82d4c164f0 DRAMSylva refactored 
DRAMSylva (or parts of it) will be possibly used in auto tests.
 2018-07-19 13:32:55 +02:00
Éder F. Zulian
d0c889da06 Doc updated 2018-07-17 16:40:27 +02:00
Matthias Jung
5c88afbc96 CI: Simple GitLab CI file added 
For a more complex example I refer to the petrinet CI setup
 2018-07-16 22:50:07 +02:00
Éder F. Zulian
d0e0835387 doc updated 2018-07-13 15:57:34 +02:00
Éder F. Zulian
dc4c6c2399 new files added to project 2018-07-12 18:51:15 +02:00
Éder F. Zulian
a48b1a2c51 doc updated 2018-07-12 18:24:27 +02:00
Éder F. Zulian
389d947621 doc updated 2018-07-12 18:19:57 +02:00
Éder F. Zulian
19ac04774b DRAMSylva - Using json for configs 2018-07-12 11:29:03 +02:00
Éder F. Zulian
f42f95f217 Doc improved 2018-07-12 09:26:01 +02:00
Éder F. Zulian
c2a0e9ddd1 Doc improved 2018-07-12 09:22:09 +02:00
Éder F. Zulian
a3ce6f3d26 Doc improved 2018-07-12 08:30:51 +02:00
Éder F. Zulian
10723f588f fix 2018-07-11 18:01:20 +02:00
Éder F. Zulian
3827dd413a Improvement 2018-07-11 10:24:51 +02:00
Éder F. Zulian
19919dc9bc Improvements 2018-07-11 10:14:09 +02:00
Éder F. Zulian
18930e0a43 Storing and using clkMhz from mem. spec. 2018-07-10 17:26:45 +02:00
Éder F. Zulian
f9ef97f361 changes in rgr default config 2018-07-10 17:19:51 +02:00
Éder F. Zulian
6c712fc941 ControllerCoreRGRNumARIntREFI --> ControllerCoreRefNumARCmdsIntREFI 
Documentation updated.
 2018-07-10 16:02:04 +02:00
Éder F. Zulian
8971ea5769 coding style 2018-07-10 12:51:49 +02:00
Éder F. Zulian
7c538cdcd0 Refresh Manager Bankwise - several improvements 
Considering initial PRE time for planning next REF when necessary.
Postpone burst for a bank shall not be interrupted.
Correct number of additional REF are pulled-in/postponed for a bank.
Alignment to tREFI.
 2018-07-10 12:50:22 +02:00
Éder F. Zulian
8faec705e0 Refresh Manager - several improvements 
Considering initial PRE time for planning next REF when necessary.
Postpone burst shall not be interrupted.
Correct number of additional REF are pulled-in/postponed.
Alignment to tREFI.
 2018-07-10 11:37:54 +02:00
Éder F. Zulian
c6e66305c1 Standard nomenclature for refresh related configs. 
ControllerCoreRef* for refresh general configs.
ControllerCoreRGR* for RGR specific configs.
 2018-07-10 09:44:48 +02:00
Éder F. Zulian
af0520faae Improvements 2018-07-10 08:42:36 +02:00
Éder F. Zulian
e4ba855563 Initial displacement 2018-07-10 08:24:00 +02:00
Éder F. Zulian
0d22844ef8 coding style 2018-07-09 17:16:04 +02:00
Éder F. Zulian
ebc0a0ef72 Pullin test, ref alignment, several improvements 2018-07-09 17:09:39 +02:00
Éder F. Zulian
d4848de9e2 Fix after manual merge 2018-07-09 09:21:49 +02:00
Matthias Jung
e8e4899642 GRP Scheduler introduced. 
GRP is a simple read write grouper. However, it is not aware of the
row-buffer and therfore it is just optimizing w.r.t to tWTR peanelty.
For the functionality of row buffer management we refer to the
FR_FCFS_GRP.  This scheduler is mainly intersting for ConGen based
applications.
 2018-07-08 16:16:43 +02:00
Matthias Jung
e422aee1c8 Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2018-07-08 14:06:32 +02:00
Matthias Jung
1b39dc1705 Preparation for FIFO RD-WR-Grouper 2018-07-08 14:05:47 +02:00
Éder F. Zulian
7ca6396766 Doc improved 2018-07-05 13:12:39 +02:00
Éder F. Zulian
9b237be228 RecordableController and RecordableDram 2018-07-05 11:39:04 +02:00
fzeder
5c6df18a4f Merge pull request #194 from jfeldman/Bugfix/power_plot 
Power plot changed
 2018-07-05 08:47:35 +02:00
Éder F. Zulian
d579060e8e Doc improved 2018-07-05 08:19:31 +02:00
Éder F. Zulian
2e307d00e8 Doc improved 2018-07-05 08:09:36 +02:00
Éder F. Zulian
2cc7127317 coding style 2018-07-03 15:10:39 +02:00
Éder F. Zulian
6c5c49179a Commit of the following: 
Changed stlPlayer to template class.
Integrated the relative stl player.
 2018-07-03 15:03:36 +02:00
fzeder
03760b964c Merge pull request #201 from jfeldman/Bugfix/address_decoder_private 
Make static methods for instance handling private in derived classes.
 2018-07-03 14:02:50 +02:00
Éder F. Zulian
f88e88a81f improvements 2018-07-03 13:00:34 +02:00
Éder F. Zulian
e088380a64 coding style 2018-07-03 11:29:21 +02:00
Éder F. Zulian
0ace967a67 Refresh modes 1X, 2X and 4X - tRFC 2018-07-03 11:24:06 +02:00
Éder F. Zulian
a787b7bb5b coding style 2018-07-03 10:59:20 +02:00
Éder F. Zulian
3bcd0335e1 select next refresh (analyzer) 
it was broken since... (?)
 2018-07-03 10:57:08 +02:00
Éder F. Zulian
00e57139f0 indentation 2018-07-02 12:15:56 +02:00
Éder F. Zulian
88f604b7bf Doc improved 2018-07-02 12:11:14 +02:00
Éder F. Zulian
6b8a123675 coding style 2018-07-02 07:59:22 +02:00
Éder F. Zulian
81914bc25f Improvement 2018-07-02 07:58:03 +02:00
Éder F. Zulian
8f9751f30f Refresh modes 1X, 2X and 4X. 2018-07-02 07:50:28 +02:00
Éder F. Zulian
af6d1d1439 Default simulation properly set 2018-06-28 15:12:22 +02:00
Éder F. Zulian
0a992391d2 Following changes: 
Show rgr related config during initialization.
ORGR in traceAnalyzer.
Submodule drampower set properly (point to rgr branch).
New config for row increment (selective ref.).
Specific simulations NO REF. and AR with close page policy.
Simulation files ddr4 1, 2, 4 x mode open, close page policy, no ref, ar, rgr, orgr.
New config for number of auto-ref. cmds in 64 ms.
New traces for ddr4.
New spec for dd4 16Gb after Christian's corrections.
Initial offset for bankwise logic (if zeroed, for research).
ORGR/RGR.
Flex. ORGR/RGR.
Bankwise flex. refresh.
Small schanges.
RGR flex test files.
Doc updated.
 2018-06-28 14:35:14 +02:00