derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Improvements

Browse Source
This commit is contained in:
Éder F. Zulian
2018-07-10 08:42:36 +02:00
parent e4ba855563
commit af0520faae
1 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
DRAMSys/library/src/controller/core/refresh/RGR.cpp
View File

@@ -70,7 +70,6 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
previousState[b] = ST_REFRESH;
nextState[b] = ST_REFRESH;
setUpDummy(rps[b], b);
nextPlannedRefreshs[b] = SC_ZERO_TIME;
}
#if INITIAL_DISPLACEMENT == TRUE
if (bwl) {
@@ -79,8 +78,12 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs;
}
}
#else
for (Bank b : ccore.getBanks()) {
nextPlannedRefreshs[b] = SC_ZERO_TIME;
}
#endif
if (ccore.config.BankwiseLogic) {
if (bwl) {
for (Bank b : ccore.getBanks()) {
planNextRefresh(b, tREFIx, false);
}
@@ -265,4 +268,3 @@ void RGR::printDebugMessage(std::string msg)
{
DebugManager::getInstance().printDebugMessage(this->name(), msg);
}