From af0520faae73844dc1b43c39c03e41a063d80b1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Tue, 10 Jul 2018 08:42:36 +0200 Subject: [PATCH] Improvements --- DRAMSys/library/src/controller/core/refresh/RGR.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index 9bb9d9dc..c8e0abcc 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -70,7 +70,6 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), previousState[b] = ST_REFRESH; nextState[b] = ST_REFRESH; setUpDummy(rps[b], b); - nextPlannedRefreshs[b] = SC_ZERO_TIME; } #if INITIAL_DISPLACEMENT == TRUE if (bwl) { @@ -79,8 +78,12 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs; } } +#else + for (Bank b : ccore.getBanks()) { + nextPlannedRefreshs[b] = SC_ZERO_TIME; + } #endif - if (ccore.config.BankwiseLogic) { + if (bwl) { for (Bank b : ccore.getBanks()) { planNextRefresh(b, tREFIx, false); } @@ -265,4 +268,3 @@ void RGR::printDebugMessage(std::string msg) { DebugManager::getInstance().printDebugMessage(this->name(), msg); } -