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Initial displacement

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This commit is contained in:
Éder F. Zulian
2018-07-10 08:24:00 +02:00
parent 0d22844ef8
commit e4ba855563
1 changed files with 13 additions and 10 deletions
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23
DRAMSys/library/src/controller/core/refresh/RGR.cpp
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@@ -39,6 +39,10 @@
#include "../TimingCalculation.h"
#include "../../../common/Utils.h"
#define TRUE 1
#define FALSE 0
#define INITIAL_DISPLACEMENT FALSE
using namespace std;
RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
@@ -59,14 +63,6 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
pullInEnabled = ccore.config.ControllerCoreEnableRefPullIn;
maxpostpone = ccore.config.ControllerCoreMaxPostponedARCmd * m;
maxpullin = ccore.config.ControllerCoreMaxPulledInARCmd * m;
#if 0
if (bwl) {
for (Bank b : ccore.getBanks()) {
auto nbs = ccore.config.memSpec.NumberOfBanks;
nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs;
}
}
#endif
for (Bank b : ccore.getBanks()) {
pulledin[b] = 0;
postponed[b] = 0;
@@ -76,6 +72,14 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
setUpDummy(rps[b], b);
nextPlannedRefreshs[b] = SC_ZERO_TIME;
}
#if INITIAL_DISPLACEMENT == TRUE
if (bwl) {
auto nbs = ccore.config.memSpec.NumberOfBanks;
for (Bank b : ccore.getBanks()) {
nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs;
}
}
#endif
if (ccore.config.BankwiseLogic) {
for (Bank b : ccore.getBanks()) {
planNextRefresh(b, tREFIx, false);
@@ -230,8 +234,7 @@ void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t)
}
break;
default:
SC_REPORT_FATAL(this->name(),
"Invalid state in RGR flexible refresh FSM. Stop.");
SC_REPORT_FATAL(this->name(), "RGR flex FSM invalid state.");
break;
}
planNextRefresh(bwl ? b : ccore.getBanks()[0], nrt, align);