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ControllerCoreRGRNumARIntREFI --> ControllerCoreRefNumARCmdsIntREFI

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Documentation updated.
This commit is contained in:
Éder F. Zulian
2018-07-10 16:02:04 +02:00
parent 8971ea5769
commit 6c712fc941
10 changed files with 16 additions and 16 deletions
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2
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
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@@ -15,7 +15,7 @@
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- New commands using starndard timing values -->
<!--

7
DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
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@@ -11,9 +11,10 @@
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
@@ -40,7 +41,7 @@
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="1"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>

2
DRAMSys/library/resources/configs/simulator/orgr.xml
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@@ -12,7 +12,7 @@
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- NEW COMMANDS USING STARNDARD TIMING VALUES -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>

2
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml
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@@ -12,7 +12,7 @@
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRGR value="1"/>

2
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml
View File

@@ -12,7 +12,7 @@
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>

2
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml
View File

@@ -12,7 +12,7 @@
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRGR value="1"/>

2
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml
View File

@@ -12,7 +12,7 @@
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>

3
DRAMSys/library/src/controller/core/ControllerCore.cpp
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@@ -89,9 +89,6 @@ ControllerCore::ControllerCore(sc_module_name /*name*/,
refreshManager = new RGR("RGR", *this);
assert(config.getTrasb() <= config.memSpec.tRAS);
assert(config.getTrasb() >= config.memSpec.tRCD);
if (config.memSpec.tRRD_L != config.memSpec.tRRD_S) {
cout << "double check assertions" << endl;
}
assert(config.getTrrdb_L() <= config.memSpec.tRRD_L);
assert(config.getTrrdb_S() <= config.memSpec.tRRD_S);
assert(config.getTrpb() <= config.memSpec.tRP);

2
DRAMSys/library/src/controller/core/configuration/Configuration.cpp
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@@ -206,7 +206,7 @@ void Configuration::setParameter(std::string name, std::string value)
RefMode = string2int(value);
if (RefMode != 1 && RefMode != 2 && RefMode != 4)
SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str());
} else if (name == "ControllerCoreRGRNumARIntREFI")
} else if (name == "ControllerCoreRefNumARCmdsIntREFI")
NumAR = string2int(value);
else if (name == "ControllerCoreRGRB0")
RGRB0 = string2bool(value);

8
README.md
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@@ -714,9 +714,10 @@ Below, the sub-configurations are listed and explained.
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
@@ -809,8 +810,9 @@ Below, the sub-configurations are listed and explained.
- *ControllerCoreRGR* (boolean)
- "1": enables row granular refresh feature (RGR)
- "0": normal operation
- *ControllerCoreRGRNumARIntREFI* (unsigned int)
- Number of AR commands to to be issued in a refresh period tREFI
- *ControllerCoreRefNumARCmdsIntREFI* (unsigned int)
- Number of AR commands to to be issued in a refresh period tREFI in 1X
mode
- *ControllerCoreRGRRowInc* (unsigned int)
- Row increment for each AR command (selective refresh)
- *ControllerCoreRGRB0* (boolean)