From 6c712fc9415c166595863e7d9519a8cb2af9ef15 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= <zulian@eit.uni-kl.de>
Date: Tue, 10 Jul 2018 16:02:04 +0200
Subject: [PATCH] ControllerCoreRGRNumARIntREFI -->
 ControllerCoreRefNumARCmdsIntREFI

Documentation updated.
---
 .../resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml  | 2 +-
 DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml  | 7 ++++---
 DRAMSys/library/resources/configs/simulator/orgr.xml      | 2 +-
 .../configs/simulator/orgr_4b_opt_timings_ddr3.xml        | 2 +-
 .../configs/simulator/orgr_4b_std_timings_ddr3.xml        | 2 +-
 .../configs/simulator/orgr_8b_opt_timings_ddr3.xml        | 2 +-
 .../configs/simulator/orgr_8b_std_timings_ddr3.xml        | 2 +-
 DRAMSys/library/src/controller/core/ControllerCore.cpp    | 3 ---
 .../src/controller/core/configuration/Configuration.cpp   | 2 +-
 README.md                                                 | 8 +++++---
 10 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
index cf1427fb..d6410aea 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
@@ -15,7 +15,7 @@
 
     <ControllerCoreRefDisable value="0"/>
     <ControllerCoreRGR value="1"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
     <ControllerCoreRGRRowInc value="1"/>
     <!-- New commands using starndard timing values -->
     <!--
diff --git a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
index 34e89dc9..bb8b64ae 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
@@ -11,9 +11,10 @@
     <ControllerCoreRefDisable value="0"/>
 	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
     <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
 	<!-- RGR -->
-    <ControllerCoreRGR value="0"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRGR value="1"/>
     <ControllerCoreRGRRowInc value="1"/>
 	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
     <ControllerCoreRGRB0  value="1"/>
@@ -40,7 +41,7 @@
     <ControllerCoreRGRtRCBInClkCycles value="37"/>
     <ControllerCoreRGRtFAWBInClkCycles value="0"/>
 	<!-- Postpone, pull-in -->
-    <ControllerCoreRefEnablePostpone value="1"/>
+    <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
diff --git a/DRAMSys/library/resources/configs/simulator/orgr.xml b/DRAMSys/library/resources/configs/simulator/orgr.xml
index 487a44a8..6598d8f3 100644
--- a/DRAMSys/library/resources/configs/simulator/orgr.xml
+++ b/DRAMSys/library/resources/configs/simulator/orgr.xml
@@ -12,7 +12,7 @@
 
     <ControllerCoreRefDisable value="0"/>
     <ControllerCoreRGR value="1"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
     <!-- NEW COMMANDS USING STARNDARD TIMING VALUES -->
     <ControllerCoreRGR value="1"/>
     <ControllerCoreRGRtRASBInClkCycles value="20"/>
diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml
index f69b11c5..5bea53cb 100644
--- a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml
+++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml
@@ -12,7 +12,7 @@
 
     <ControllerCoreRefDisable value="0"/>
     <ControllerCoreRGR value="1"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
     <!-- New commands using starndard timing values -->
     <!--
     <ControllerCoreRGR value="1"/>
diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml
index 77c526e1..ce0d2ea0 100644
--- a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml
+++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml
@@ -12,7 +12,7 @@
 
     <ControllerCoreRefDisable value="0"/>
     <ControllerCoreRGR value="1"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
     <!-- New commands using starndard timing values -->
     <ControllerCoreRGR value="1"/>
     <ControllerCoreRGRtRASBInClkCycles value="20"/>
diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml
index 331f7f9a..bec58f50 100644
--- a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml
+++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml
@@ -12,7 +12,7 @@
 
     <ControllerCoreRefDisable value="0"/>
     <ControllerCoreRGR value="1"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
     <!-- New commands using starndard timing values -->
     <!--
     <ControllerCoreRGR value="1"/>
diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml
index d43a9eb0..e8a7bc95 100644
--- a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml
+++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml
@@ -12,7 +12,7 @@
 
     <ControllerCoreRefDisable value="0"/>
     <ControllerCoreRGR value="1"/>
-    <ControllerCoreRGRNumARIntREFI value="8192"/>
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
     <!-- New commands using starndard timing values -->
     <ControllerCoreRGR value="1"/>
     <ControllerCoreRGRtRASBInClkCycles value="20"/>
diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp
index f28f8e2a..63069368 100644
--- a/DRAMSys/library/src/controller/core/ControllerCore.cpp
+++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp
@@ -89,9 +89,6 @@ ControllerCore::ControllerCore(sc_module_name /*name*/,
         refreshManager = new RGR("RGR", *this);
         assert(config.getTrasb() <= config.memSpec.tRAS);
         assert(config.getTrasb() >= config.memSpec.tRCD);
-        if (config.memSpec.tRRD_L != config.memSpec.tRRD_S) {
-            cout << "double check assertions" << endl;
-        }
         assert(config.getTrrdb_L() <= config.memSpec.tRRD_L);
         assert(config.getTrrdb_S() <= config.memSpec.tRRD_S);
         assert(config.getTrpb() <= config.memSpec.tRP);
diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp
index b7a62027..e4ae238c 100644
--- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp
+++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp
@@ -206,7 +206,7 @@ void Configuration::setParameter(std::string name, std::string value)
         RefMode = string2int(value);
         if (RefMode != 1 && RefMode != 2 && RefMode != 4)
             SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str());
-    } else if (name == "ControllerCoreRGRNumARIntREFI")
+    } else if (name == "ControllerCoreRefNumARCmdsIntREFI")
         NumAR = string2int(value);
     else if (name == "ControllerCoreRGRB0")
         RGRB0 = string2bool(value);
diff --git a/README.md b/README.md
index f6355d62..11d12777 100644
--- a/README.md
+++ b/README.md
@@ -714,9 +714,10 @@ Below, the sub-configurations are listed and explained.
       <ControllerCoreRefDisable value="0"/>
       <!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
       <ControllerCoreRefMode value="1"/>
+      <!-- Number of AR commands in a tREFI in 1X mode -->
+      <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
       <!-- RGR -->
       <ControllerCoreRGR value="0"/>
-      <ControllerCoreRGRNumARIntREFI value="8192"/>
       <ControllerCoreRGRRowInc value="1"/>
       <!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
       <ControllerCoreRGRB0  value="1"/>
@@ -809,8 +810,9 @@ Below, the sub-configurations are listed and explained.
   - *ControllerCoreRGR* (boolean)
     - "1": enables row granular refresh feature (RGR)
     - "0": normal operation
-  - *ControllerCoreRGRNumARIntREFI* (unsigned int)
-    - Number of AR commands to to be issued in a refresh period tREFI
+  - *ControllerCoreRefNumARCmdsIntREFI* (unsigned int)
+    - Number of AR commands to to be issued in a refresh period tREFI in 1X
+      mode
   - *ControllerCoreRGRRowInc* (unsigned int)
     - Row increment for each AR command (selective refresh)
   - *ControllerCoreRGRB0* (boolean)