Matthias Jung
7f67a82287
added error model to the configs
2015-04-09 10:33:02 +02:00
Matthias Jung
0f8ad59a1e
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system into ehses-master
...
Conflicts:
dram/dramSys/dramSys.pro
2015-04-09 10:32:06 +02:00
gernhard2
beddeccb64
Fixed bug in Fifostrict that caused deadlock
2015-02-17 09:22:58 +01:00
gernhard2
f11adf51dc
Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.
...
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
Peter Ehses
e84a3cc99b
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system
...
Conflicts:
dram/dramSys/dramSys.pro
dram/resources/configs/amconfigs/am_wideio.xml
dram/resources/configs/memconfigs/fr_fcfs.xml
dram/src/common/xmlAddressdecoder.cpp
dram/src/controller/core/configuration/ConfigurationLoader.cpp
dram/src/simulation/Simulation.cpp
dram/src/simulation/Simulation.h
dram/src/simulation/TracePlayer.h
2014-12-02 15:25:48 +01:00
Peter Ehses
905e75ca32
included errormodel which is presented in DATE paper
2014-12-02 14:44:46 +01:00
Janik Schlemminger
f35cc43186
gute frage^^
2014-10-08 21:04:44 +02:00
Janik Schlemminger
6ce8935097
fix on fifo hack
2014-09-08 14:59:28 +02:00
Janik Schlemminger
33a13d6bfd
status quo .. jetzt wirds tricky
2014-09-07 00:04:19 +02:00
Janik Schlemminger
938dbb3fdb
print mapping
2014-09-06 20:21:43 +02:00
Janik Schlemminger
30b1fbbd0c
added no powerdown option
2014-09-06 16:59:46 +02:00
Matthias Jung
e110d45e0e
Added Zoom by keys - and +
...
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
Conflicts:
dram/src/simulation/SimulationManager.cpp
2014-09-06 01:16:13 +02:00
Janik Schlemminger
2aa07bbbe6
Quick and Dirty XML - Refactoring necessary
2014-09-04 23:35:54 +02:00
Matthias Jung
8d864afb44
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-09-04 15:35:30 +02:00
Matthias Jung
1c7643b9b6
Changed analysis scripts
2014-09-04 15:35:01 +02:00
Janik Schlemminger
610dc6e6a5
changed fifo scheduler to strictly keep the order
2014-09-04 11:19:40 +02:00
Janik Schlemminger
320331164b
xml extended, sim config introduced
2014-09-03 18:52:32 +02:00
Janik Schlemminger
85a574fd5b
Configuration refactoring
2014-08-30 19:22:48 +02:00
Janik Schlemminger
fdc723a1bc
Merge branch 'master' of https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system
2014-08-29 13:10:01 +02:00
Janik Schlemminger
fcd029c6d8
Traceplayer now tolerates new lines in the Tracefiles
2014-08-29 12:23:13 +02:00
Janik Schlemminger
df6637b114
splitting config and memspec
2014-08-29 10:25:32 +02:00
Janik Schlemminger
efc6094c13
memspec class
2014-08-27 09:43:42 +02:00
Matthias Jung
ea64dd8cea
Mapping will automatically generated
2014-08-07 15:16:40 +02:00
Matthias Jung
b008875fca
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-08-07 13:57:37 +02:00
Matthias Jung
fbf79645aa
Added some new metric scripts and Trace analysys tools
2014-08-07 13:36:27 +02:00
Robert Gernhardt
8e29063f76
added config for read/write grouper
2014-08-07 12:11:48 +02:00
Robert Gernhardt
b1142c4796
traceplayer can now parse data of write commands. Reorder buffer inserted
2014-08-07 12:06:04 +02:00
Janik Schlemminger
47580bcba3
added read/write grouper memconfig
2014-08-06 10:30:49 +02:00
Robert Gernhardt
767d03dfe9
modified rd/grouper
2014-08-06 10:02:56 +02:00
Robert Gernhardt
0bba004266
modified rd/write grouper
2014-08-06 09:37:42 +02:00
Janik Schlemminger
15f07b0017
precharge allchecker tRas, simulation memory
2014-08-05 19:33:16 +02:00
Janik Schlemminger
c88486d842
memcpy bug
2014-08-05 00:07:22 +02:00
Robert Gernhardt
fff7b9cd34
merged
2014-08-04 18:30:52 +02:00
Robert Gernhardt
bd245a9d90
reorder buffer
2014-08-04 18:27:33 +02:00
Matthias Jung
dc96ffd052
metrics: memory utilization
2014-08-04 13:02:52 +02:00
Janik Schlemminger
2f9cd66a73
Powerdowns bankwise have own command in protocoll now. one command for all banks on bank 0.
2014-07-30 23:37:56 +02:00
Janik Schlemminger
eb98c22188
merge
2014-07-30 22:10:28 +02:00
Janik Schlemminger
76ab26e2d7
refresh splitted in REFA REFB
2014-07-30 03:01:06 +02:00
Matthias Jung
d402933502
New metric "memory utilization" defined
2014-07-29 16:21:07 +02:00
Robert Gernhardt
8af2f3b898
renamed colum to column in addressmapping. Error with large values on data bus should be resolved
2014-07-28 10:53:17 +02:00
Matthias Jung
793cf882fe
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-07-15 22:49:33 +02:00
Matthias Jung
8b4e3fa4bf
Integrated LibDRAMPower. Before you start you have to run the install_prerequisites.sh
2014-07-15 22:47:02 +02:00
Janik Schlemminger
dc9d1b4b1f
address decoder simplified
2014-07-15 14:35:13 +02:00
Janik Schlemminger
c135d7c31b
Traceplayer has a clock now
2014-07-15 00:10:49 +02:00
Robert Gernhardt
c77048ac93
renamed some stuff
2014-07-14 23:17:18 +02:00
Robert Gernhardt
2b427ecb6e
also shows clks now in tooltip in analyzer
2014-07-11 09:22:34 +02:00
robert
b8febb434f
minor refactoring
2014-07-06 10:34:46 +02:00
robert
e128263833
minor refactoring
2014-07-01 13:58:55 +02:00
robert
37c147ba2f
added debug message capabilities to scheduler
2014-07-01 11:01:52 +02:00
robert
2b062b86ff
changed scheduler interface. Fixed bug with terminateSimulation
2014-06-20 15:49:07 +02:00
