Lukas Steiner
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ccfe1f45af
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Small bugfix in LPDDR4 checker, some method renaming.
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2019-11-25 23:44:54 +01:00 |
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Lukas Steiner
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7380edfac2
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Small code refactoring.
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2019-11-25 00:18:51 +01:00 |
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Lukas Steiner
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fa301d2bb4
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Staggered power-down working, adapt per-bank refresh.
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2019-11-22 01:01:08 +01:00 |
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Lukas Steiner
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7997648521
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Fixed position of power-down entry trigger.
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2019-11-21 23:29:55 +01:00 |
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Lukas Steiner
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037cd4f334
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Removed old controller core files.
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2019-11-21 21:38:52 +01:00 |
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Lukas Steiner
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4bd9987c9c
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Staggered power-down with all-bank refresh is working.
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2019-11-21 17:21:54 +01:00 |
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Lukas Steiner
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9d7f17451a
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Included interface and dummy for power-down manager.
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2019-11-21 00:03:15 +01:00 |
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Lukas Steiner
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6e6d839bd1
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First version of power down working, added some helper functions for enum Command.
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2019-11-20 00:30:27 +01:00 |
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Lukas Steiner (2)
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bddec3022a
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Some preparations for power down.
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2019-11-18 19:16:42 +01:00 |
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Lukas Steiner (2)
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e970ad194e
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Correction of timing dependency WR -<> RDA.
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2019-10-17 15:47:27 +02:00 |
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Lukas Steiner (2)
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5f7cb7a326
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Included memspec, dram and checker for GDDR5, GDDR5X and GDDR6.
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2019-10-17 15:00:28 +02:00 |
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Lukas Steiner
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a3fa363a87
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Bugfix for triggering controllerMethod() multiple times at the same time.
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2019-10-15 20:26:49 +02:00 |
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Lukas Steiner (2)
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2aa5d125c7
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Fixed BM deadlock.
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2019-10-15 16:09:59 +02:00 |
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Lukas Steiner (2)
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04a59c8bd2
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Changed MemSpec::getExecutionTime() for different tRCDs.
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2019-10-15 16:03:34 +02:00 |
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Lukas Steiner
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ed29186adc
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Included HBM2 example, fixed fifo strict issue with HBM2's command buses.
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2019-10-11 20:35:45 +02:00 |
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Lukas Steiner
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f4803f4b8c
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Included checker for HBM2.
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2019-10-10 18:17:21 +02:00 |
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Lukas Steiner (2)
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606d273bee
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Included memspec and dram component for HBM2.
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2019-10-10 15:21:58 +02:00 |
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Lukas Steiner (2)
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256abe449c
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Included CheckerWideIO2, tPPD fix in CheckerLPDDR4.
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2019-10-09 09:49:46 +02:00 |
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Lukas Steiner (2)
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a5b00ea3be
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Further inclusion of WideIO2.
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2019-10-08 15:27:18 +02:00 |
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Lukas Steiner (2)
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65db413a20
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Included MemSpecWideIO2, some adaptions for all memspecs.
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2019-10-08 14:14:42 +02:00 |
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Lukas Steiner (2)
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932027112e
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Adapted timing checkers of DDR4 and WideIO to new refresh.
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2019-10-07 15:37:23 +02:00 |
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Lukas Steiner
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86d5082434
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Further improvements in refresh managers.
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2019-10-06 20:54:30 +02:00 |
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Lukas Steiner
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d1f6bc6233
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Improved flexible refresh, implemented first version of bankwise flexible refresh.
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2019-10-06 18:56:13 +02:00 |
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Lukas Steiner
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aa6a205872
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Implemented first version of flexible refresh (only REFA).
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2019-10-04 21:46:29 +02:00 |
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Lukas Steiner
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b22cfa4a94
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Improved controller method, some code and output formatting.
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2019-10-03 19:04:34 +02:00 |
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Lukas Steiner
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6e71e435c5
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Implemented first version of new bankwise refresh.
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2019-10-02 21:55:19 +02:00 |
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Lukas Steiner
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4328f4550b
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Updated CheckerLPDDR4 for new refresh, some renaming.
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2019-10-02 21:54:05 +02:00 |
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Lukas Steiner
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f4a018cfb3
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Fixed display of rankwise commands.
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2019-10-02 17:46:37 +02:00 |
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Lukas Steiner
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abb9a37096
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Added numberOfRanks to database.
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2019-10-02 16:08:10 +02:00 |
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Lukas Steiner
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7868af4b51
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Implemented first version of new refresh (no REFB).
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2019-10-01 20:53:01 +02:00 |
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Lukas Steiner
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04ec683b57
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Included LPDDR4 timing checker and example.
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2019-09-26 21:31:17 +02:00 |
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Lukas Steiner
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4950a2587e
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Included LPDDR4 memspec and Dram, changed structure of MemSpec.h, removed ScheduledCommand.
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2019-09-26 16:55:20 +02:00 |
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Lukas Steiner
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8b7760a585
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LPDDR4 address mapping and memspec.
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2019-09-26 16:49:40 +02:00 |
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Lukas Steiner (2)
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47949922f3
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Included LPDDR4 memspec.
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2019-09-26 13:26:17 +02:00 |
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Lukas Steiner (2)
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cfbce483bd
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Included timing checker for DDR4.
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2019-09-24 15:18:37 +02:00 |
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Lukas Steiner (2)
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2690755024
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Included JEDEC based memspecs, address mapping and simulation for DDR4.
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2019-09-24 15:17:25 +02:00 |
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Lukas Steiner (2)
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149bfee201
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Corrected refresh mode (1x, 2x and 4x) for DDR4.
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2019-09-24 15:16:09 +02:00 |
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Lukas Steiner (2)
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805490d05c
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Correction of address mappings.
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2019-09-24 14:14:56 +02:00 |
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Lukas Steiner
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fc10f72773
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Minor changes in address mapping and configuration.
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2019-09-23 22:16:56 +02:00 |
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Lukas Steiner (2)
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102b0667fd
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Added bankgroups to address decoding.
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2019-09-23 20:07:00 +02:00 |
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Lukas Steiner (2)
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bda10dca2f
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Individual memspec files for different DRAMs.
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2019-09-23 14:31:47 +02:00 |
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Lukas Steiner (2)
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c1b741d89b
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Changed directory of configuration, added attribute unused to suppress warnings.
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2019-09-23 13:24:47 +02:00 |
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Lukas Steiner (2)
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650e1d405b
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Removed ScheduledCommand dependencies.
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2019-09-23 10:23:02 +02:00 |
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Lukas Steiner
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5fe5529c7c
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Included various command lengths.
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2019-09-20 17:35:01 +02:00 |
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Lukas Steiner
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97542d5f97
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Included missing memory allocation in Dram.
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2019-09-19 14:46:55 +02:00 |
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Lukas Steiner
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d06d9eec2c
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Changed data structures of timing checkers from ScheduledCommand to sc_time.
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2019-09-19 14:45:38 +02:00 |
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Lukas Steiner
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b918f0f9ea
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Added ranks to tdb files and TraceAnalyzer.
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2019-09-18 18:24:10 +02:00 |
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Lukas Steiner
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330b07d0e7
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Changed data structures of Address Decoder for speedup.
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2019-09-18 16:39:38 +02:00 |
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Lukas Steiner
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6eef8ff1e6
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Rank inclusion part 2.
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2019-09-17 21:31:57 +02:00 |
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Lukas Steiner
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5d7495383e
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Changed internal data structures from std::map to std::vector for faster access.
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2019-09-17 18:16:52 +02:00 |
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