derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
204 Commits 1 Branch 0 Tags
aa615dae63a9382d3cbcf0800e908e693387597b
Commit Graph

204 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Matthias Jung
aa615dae63 Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2015-02-17 21:52:39 +01:00
Matthias Jung
c9a01d9a33 added better metric for utilisation 2015-02-17 21:50:15 +01:00
gernhard2
beddeccb64 Fixed bug in Fifostrict that caused deadlock 2015-02-17 09:22:58 +01:00
gernhard2
f11adf51dc Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer. 
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
 2015-02-16 08:21:27 +01:00
Janik Schlemminger
badcc37118 debug bums raus 2014-10-08 21:12:01 +02:00
Janik Schlemminger
f35cc43186 gute frage^^ 2014-10-08 21:04:44 +02:00
Janik Schlemminger
e105d54045 added fix for bankgroups and ranks in addressdecoder 2014-09-10 16:10:07 +02:00
Janik Schlemminger
5a7efb4d88 merged 2014-09-08 15:03:10 +02:00
Janik Schlemminger
6ce8935097 fix on fifo hack 2014-09-08 14:59:28 +02:00
Matthias Jung
9fb90e9015 Experimantal change for a big FIFO 2014-09-08 13:09:52 +02:00
Janik Schlemminger
33a13d6bfd status quo .. jetzt wirds tricky 2014-09-07 00:04:19 +02:00
Janik Schlemminger
938dbb3fdb print mapping 2014-09-06 20:21:43 +02:00
Janik Schlemminger
30b1fbbd0c added no powerdown option 2014-09-06 16:59:46 +02:00
Matthias Jung
e110d45e0e Added Zoom by keys - and + 
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system

Conflicts:
	dram/src/simulation/SimulationManager.cpp
 2014-09-06 01:16:13 +02:00
Janik Schlemminger
2aa07bbbe6 Quick and Dirty XML - Refactoring necessary 2014-09-04 23:35:54 +02:00
Matthias Jung
8d864afb44 Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2014-09-04 15:35:30 +02:00
Matthias Jung
1c7643b9b6 Changed analysis scripts 2014-09-04 15:35:01 +02:00
Janik Schlemminger
610dc6e6a5 changed fifo scheduler to strictly keep the order 2014-09-04 11:19:40 +02:00
Janik Schlemminger
320331164b xml extended, sim config introduced 2014-09-03 18:52:32 +02:00
Matthias Jung
1807ef00f4 Added nbrOfColumns member variable 2014-09-03 15:11:46 +02:00
Matthias Jung
9cddd32a01 Changed #ifndef of trace generators' header file 2014-09-03 11:53:09 +02:00
Matthias Jung
7abf3c9958 Refactored TlmPacketGenerator in TraceGenerator 2014-09-03 11:39:41 +02:00
Janik Schlemminger
c5971ba2f5 merged conflicts 2014-09-03 10:37:39 +02:00
Janik Schlemminger
8722808a90 made traceplayer generic, so that different kind of traceplayers are supported 2014-09-03 10:27:04 +02:00
Janik Schlemminger
85a574fd5b Configuration refactoring 2014-08-30 19:22:48 +02:00
Janik Schlemminger
fdc723a1bc Merge branch 'master' of https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system 2014-08-29 13:10:01 +02:00
Janik Schlemminger
fcd029c6d8 Traceplayer now tolerates new lines in the Tracefiles 2014-08-29 12:23:13 +02:00
Janik Schlemminger
df6637b114 splitting config and memspec 2014-08-29 10:25:32 +02:00
Matthias Jung
540eb5445e Merge pull request #2 from ehses/master 
Fixed for new drampower library
 2014-08-28 09:58:23 +02:00
Peter Ehses
2ef6d35f97 Fixed for new drampower library 2014-08-28 09:53:47 +02:00
Janik Schlemminger
efc6094c13 memspec class 2014-08-27 09:43:42 +02:00
Matthias Jung
ea64dd8cea Mapping will automatically generated 2014-08-07 15:16:40 +02:00
Matthias Jung
b008875fca Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2014-08-07 13:57:37 +02:00
Matthias Jung
fbf79645aa Added some new metric scripts and Trace analysys tools 2014-08-07 13:36:27 +02:00
Robert Gernhardt
8e29063f76 added config for read/write grouper 2014-08-07 12:11:48 +02:00
Robert Gernhardt
b1142c4796 traceplayer can now parse data of write commands. Reorder buffer inserted 2014-08-07 12:06:04 +02:00
Janik Schlemminger
47580bcba3 added read/write grouper memconfig 2014-08-06 10:30:49 +02:00
Robert Gernhardt
767d03dfe9 modified rd/grouper 2014-08-06 10:02:56 +02:00
Robert Gernhardt
0bba004266 modified rd/write grouper 2014-08-06 09:37:42 +02:00
Janik Schlemminger
15f07b0017 precharge allchecker tRas, simulation memory 2014-08-05 19:33:16 +02:00
Matthias Jung
e38a872a11 added adressmapping to output filename 2014-08-05 19:02:48 +02:00
Matthias Jung
114bcf370f Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 
Conflicts:
	dram/src/simulation/Dram.h
 2014-08-05 17:01:46 +02:00
Matthias Jung
327608b691 commented out the saving part 2014-08-05 16:59:22 +02:00
Matthias Jung
609e568fbc Added the tRAS timing constraint into the precharge checker 2014-08-05 16:58:15 +02:00
Janik Schlemminger
72bdce7a26 destructor 2014-08-05 00:22:03 +02:00
Janik Schlemminger
c88486d842 memcpy bug 2014-08-05 00:07:22 +02:00
Robert Gernhardt
fff7b9cd34 merged 2014-08-04 18:30:52 +02:00
Robert Gernhardt
bd245a9d90 reorder buffer 2014-08-04 18:27:33 +02:00
Matthias Jung
fe9f9ad233 changes on project file 2014-08-04 17:46:29 +02:00
Matthias Jung
6704dc2871 First approach for saving data, but there is an error with the memcopy in Dram.h 2014-08-04 17:31:25 +02:00