Commit Graph

2501 Commits

Author SHA1 Message Date
bf048c2fa3 Remove tests in TraceAnalyzer 2022-05-10 09:32:15 +02:00
9590642c03 Numerous enhancements
Fixed a crash in TA
Renamed Ranks to PC in pseudo-channel mode
Make diagrams red for better readability
2022-05-10 09:17:26 +02:00
Iron Prando da Silva
1fc4b238fe Refactored query string out of dependency tracker to individual device configuration objects. 2022-05-10 09:08:32 +02:00
052e80b716 Fix HBM3 Memspec and AM 2022-05-10 08:44:32 +02:00
Lukas Steiner
e9942d5aa2 First working implementation. 2022-05-09 13:09:19 +02:00
Lukas Steiner
5fcafe9862 Update readme. 2022-05-05 11:46:50 +00:00
Lukas Steiner
92d043c29e Update readme. 2022-05-05 11:11:47 +02:00
Lukas Steiner
d41f3d8578 Adapt TA to new database format (2). 2022-05-03 16:00:16 +02:00
Lukas Steiner
14588dbb77 Adapt TA to new database format (1). 2022-05-02 17:44:56 +02:00
Lukas Steiner
489fa5f02b Remove unused END phases. 2022-05-02 14:24:18 +02:00
Lukas Steiner
26d7e3e83e Simplify recording. 2022-05-02 11:33:08 +02:00
Iron Prando
9aaf095d7c Merge branch 'iron-devMergeDeps' into 'develop'
Merging current modifications from the dependencies branch

See merge request ems/astdm/modeling.dram/dram.sys!353
2022-05-02 07:14:22 +00:00
Iron Prando da Silva
a3e1f9469d Added missing copyright notice. 2022-05-02 09:03:40 +02:00
a048cba98c Add generated HBM3 TimingChecker and add sample memspec 2022-04-29 15:08:47 +02:00
Lukas Steiner
777d87c194 Change database format (2). 2022-04-29 11:09:35 +02:00
Lukas Steiner
f168782361 Change database format 1. 2022-04-28 17:35:40 +02:00
Lukas Steiner
844eaa390a Integrate new extensions. 2022-04-27 11:13:35 +02:00
Lukas Steiner
7c1642bc58 Add new dram extensions. 2022-04-26 11:10:30 +02:00
Lukas Steiner
ef29af81e3 Bugfix, instantiate address decoder. 2022-04-20 16:57:23 +02:00
Lukas Steiner
d56f62fd6d Give controller access to address decoder. 2022-04-20 16:36:02 +02:00
3e9b2bd329 Add support for non-integer command lengths in simulator and TraceAnalyzer 2022-04-20 12:47:52 +02:00
a3b0738364 Add skeleton for HBM3 implementation 2022-04-20 12:47:50 +02:00
Iron Prando da Silva
4a4494845a Merge branch 'iron-TA-DependencyDrawing2' into iron-devMergeDeps 2022-04-19 08:55:11 +02:00
Lukas Steiner
38057667b0 Fix gem5 coupling. 2022-04-08 11:39:59 +02:00
Iron Prando da Silva
2836d9379b Correcting dependency capture from REFP2B phases. 2022-04-07 10:13:35 +02:00
Lukas Steiner
5bfe667f4e Bugfix: Call end_of_simulation() of base class. 2022-04-06 16:59:16 +02:00
Lukas Steiner
2e4be049ac Add hazard warning, const members. 2022-04-06 14:46:40 +02:00
Lukas Steiner
b4c70b3e92 Merge branch 'bug/missing_config' into 'develop'
Add missing config parameters, fix BM issue.

See merge request ems/astdm/modeling.dram/dram.sys!352
2022-04-06 12:09:45 +00:00
Lukas Steiner
bd60e8c8dd Remove config singleton. 2022-04-06 13:55:43 +02:00
Lukas Steiner
917d8dacc4 Pointer to reference. 2022-04-06 11:31:42 +02:00
Lukas Steiner
576691cd65 Adapt BM to avoid ACT without RD/WR. 2022-04-04 16:46:01 +02:00
Lukas Steiner
9c9b31416d Add missing config parameters. 2022-04-04 15:37:50 +02:00
Iron Prando da Silva
319b774509 Added LPDDR5. Not tested. 2022-04-04 11:31:42 +02:00
Lukas Steiner
c14e00dd47 Merge branch 'work/traceanalyzer_pseudochannel' into 'develop'
Seperated Data Bus for PseudoChannelMode

See merge request ems/astdm/modeling.dram/dram.sys!351
2022-04-04 09:28:18 +00:00
Lukas Steiner
1bda9f7dd4 Fix metrics for HBM PC mode. 2022-04-04 10:54:08 +02:00
fac18ed81b Adapt GeneralInfo to new pseudoChannelsPerChannel parameter 2022-04-01 18:06:15 +02:00
2d310789f1 Seperated Data Bus for PseudoChannelMode 2022-04-01 17:54:39 +02:00
Lukas Steiner
4b59b5a4a7 Merge branch 'work/traceanalyzer_rowmodel' into 'develop'
Introduce a model/view based approach for the TraceSelector

See merge request ems/astdm/modeling.dram/dram.sys!324
2022-04-01 12:12:37 +00:00
Lukas Steiner
4346fc72cb Adapt metric for separate command buses. 2022-03-31 17:02:02 +02:00
Iron Prando da Silva
193726c04a Rebasing on develop. 2022-03-24 11:25:39 +01:00
Iron Prando da Silva
6d3daac1f9 Corrected pools time tracking. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
5e147dcd24 Removed incorrect if check for pool dependency. TODO correct pool time dependency direction. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
ea736e5861 Added 'bank in group' granularity for ddr5. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
c00b54329a Renamed some objects from suffix IF to suffix Base. Added a small readme to the 'dramTimeDependencies' folder. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
6850cd1422 Added copyright notice. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
866ccd7764 Modified DDR5 to comply with time checker. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
addb7aae31 Added DDR5 dependencies. Must be double checked. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
9eda19eb00 Added LPDDR4 dependencies. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
20f783ad38 Added HBM2 dependencies. 2022-03-24 10:46:29 +01:00
Iron Prando da Silva
3a0f56f2b2 Removed throw from ConfigurationFactory::possiblePhases. 2022-03-24 10:46:29 +01:00