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Simplify recording.

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This commit is contained in:
Lukas Steiner
2022-05-02 11:33:08 +02:00
parent 777d87c194
commit 26d7e3e83e
6 changed files with 53 additions and 102 deletions
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63
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -50,7 +50,8 @@ using namespace sc_core;
using namespace tlm;
TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) :
name(name), config(config), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME)
name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0),
simulationTimeCoveredByRecording(SC_ZERO_TIME)
{
currentDataBuffer = &recordingDataBuffer[0];
storageDataBuffer = &recordingDataBuffer[1];
@@ -114,9 +115,10 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth)
executeSqlStatement(insertBandwidthStatement);
}
void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &time,
TimeInterval intervalOnDataStrobe)
void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase, const sc_time& delay)
{
const sc_time& currentTime = sc_time_stamp();
if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end())
introduceTransactionSystem(trans);
@@ -124,32 +126,55 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase
{
assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name);
// TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = time;
if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF)
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay
+ memSpec.getCommandLength(Command(phase));
else
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay;
}
else if (phase == BEGIN_REQ || phase == BEGIN_RESP)
{
std::string phaseName = getPhaseName(phase).substr(6);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, time);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay);
}
else if (phase == BEGIN_PDNA || phase == BEGIN_PDNP || phase == BEGIN_SREF)
{
std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"
const ControllerExtension& extension = ControllerExtension::getExtension(trans);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName),
std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)),
std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)),
extension.getRank(), extension.getBankGroup(), extension.getBank(),
extension.getRow(), extension.getColumn(), extension.getBurstLength());
}
else
{
std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"
const ControllerExtension& extension = ControllerExtension::getExtension(trans);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName), time,
TimeInterval intervalOnDataStrobe;
if (phaseHasDataStrobe(phase))
{
intervalOnDataStrobe = memSpec.getIntervalOnDataStrobe(Command(phase), trans);
intervalOnDataStrobe.start = currentTime + intervalOnDataStrobe.start;
intervalOnDataStrobe.end = currentTime + intervalOnDataStrobe.end;
}
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName),
std::move(TimeInterval(currentTime + delay, currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))),
std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(),
extension.getRow(), extension.getColumn(), extension.getBurstLength());
}
if (currentTransactionsInSystem.at(&trans).cmd == 'X')
{
if (phase == END_REFAB
|| phase == END_RFMAB
|| phase == END_REFPB
|| phase == END_RFMPB
|| phase == END_REFP2B
|| phase == END_RFMP2B
|| phase == END_REFSB
|| phase == END_RFMSB
if (phase == BEGIN_REFAB
|| phase == BEGIN_RFMAB
|| phase == BEGIN_REFPB
|| phase == BEGIN_RFMPB
|| phase == BEGIN_REFP2B
|| phase == BEGIN_RFMP2B
|| phase == BEGIN_REFSB
|| phase == BEGIN_RFMSB
|| phase == END_PDNA
|| phase == END_PDNP
|| phase == END_SREF)
@@ -161,7 +186,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase
removeTransactionFromSystem(trans);
}
simulationTimeCoveredByRecording = time;
simulationTimeCoveredByRecording = currentTime + delay;
}
void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time &time)
@@ -230,16 +255,16 @@ void TlmRecorder::terminateRemainingTransactions()
{
std::string beginPhase = transaction->second.recordedPhases.front().name;
if (beginPhase == "PDNA")
recordPhase(*(transaction->first), END_PDNA, sc_time_stamp());
recordPhase(*(transaction->first), END_PDNA, SC_ZERO_TIME);
else if (beginPhase == "PDNP")
recordPhase(*(transaction->first), END_PDNP, sc_time_stamp());
recordPhase(*(transaction->first), END_PDNP, SC_ZERO_TIME);
else if (beginPhase == "SREF")
recordPhase(*(transaction->first), END_SREF, sc_time_stamp());
recordPhase(*(transaction->first), END_SREF, SC_ZERO_TIME);
else
removeTransactionFromSystem(*transaction->first);
}
else
recordPhase(*(transaction->first), END_RESP, sc_time_stamp());
recordPhase(*(transaction->first), END_RESP, SC_ZERO_TIME);
}
}

14
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -76,8 +76,7 @@ public:
traces = std::move(_traces);
}
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &time,
TimeInterval intervalOnDataStrobe = {sc_core::SC_ZERO_TIME, sc_core::SC_ZERO_TIME});
void recordPhase(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay);
void recordPower(double timeInSeconds, double averagePower);
void recordBufferDepth(double timeInSeconds, const std::vector<double> &averageBufferDepth);
void recordBandwidth(double timeInSeconds, double averageBandwidth);
@@ -86,10 +85,10 @@ public:
private:
const Configuration& config;
const MemSpec& memSpec;
struct Transaction
{
//Transaction() = default;
Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd,
const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) :
id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration),
@@ -98,22 +97,19 @@ private:
uint64_t id = 0;
uint64_t address = 0;
unsigned int dataLength = 0;
//unsigned int burstLength = 0; // TODO: move to phase
char cmd = 'X';
//ArbiterExtension arbiterExtension; // TODO: remove
//ControllerExtension controllerExtension; // TODO: move to phase
sc_core::sc_time timeOfGeneration;
//TimeInterval timeOnDataStrobe; // TODO: move to phase
Thread thread;
Channel channel;
struct Phase
{
// for BEGIN_REQ and BEGIN_RESP
Phase(std::string name, const sc_core::sc_time& begin) : name(std::move(name)),
interval(begin, sc_core::SC_ZERO_TIME) {}
Phase(std::string name, const sc_core::sc_time& begin, TimeInterval intervalOnDataStrobe, Rank rank,
Phase(std::string name, TimeInterval interval, TimeInterval intervalOnDataStrobe, Rank rank,
BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength) :
name(std::move(name)), interval(begin, sc_core::SC_ZERO_TIME),
name(std::move(name)), interval(std::move(interval)),
intervalOnDataStrobe(std::move(intervalOnDataStrobe)), rank(rank), bankGroup(bankGroup), bank(bank),
row(row), column(column), burstLength(burstLength) {}
std::string name;

28
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -58,10 +58,8 @@ ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Con
tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
// Important: delay must not be increased by nb_transport_fw
tlm_sync_enum returnValue = Controller::nb_transport_fw(trans, phase, delay);
recordPhase(trans, phase, delay);
return returnValue;
tlmRecorder.recordPhase(trans, phase, delay);
return Controller::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &,
@@ -73,30 +71,10 @@ tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &,
void ControllerRecordable::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay)
{
recordPhase(payload, phase, delay);
tlmRecorder.recordPhase(payload, phase, delay);
tSocket->nb_transport_bw(payload, phase, delay);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)
{
sc_time recTime = delay + sc_time_stamp();
NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID();
NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID();
NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID();
NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID();
NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID();
NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID();
NDEBUG_UNUSED(uint64_t id) = ControllerExtension::getExtension(trans).getChannelPayloadID();
PRINTDEBUGMESSAGE(name(), "Recording " + getPhaseName(phase) + " thread " +
std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string(
bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " +
std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string());
tlmRecorder.recordPhase(trans, phase, recTime);
}
void ControllerRecordable::controllerMethod()
{
if (enableWindowing)

1
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -58,7 +58,6 @@ protected:
void controllerMethod() override;
private:
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay);
TlmRecorder& tlmRecorder;
sc_core::sc_event windowEvent;

47
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -79,55 +79,10 @@ template<class BaseDram>
tlm_sync_enum DramRecordable<BaseDram>::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
{
recordPhase(payload, phase, delay);
tlmRecorder.recordPhase(payload, phase, delay);
return BaseDram::nb_transport_fw(payload, phase, delay);
}
template<class BaseDram>
void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)
{
sc_time recTime = sc_time_stamp() + delay;
// These are terminating phases recorded by the DRAM. The execution
// time of the related command must be taken into consideration.
if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF)
recTime += this->memSpec.getCommandLength(Command(phase));
NDEBUG_UNUSED(unsigned thr) = ArbiterExtension::getExtension(trans).getThread().ID();
NDEBUG_UNUSED(unsigned ch) = ArbiterExtension::getExtension(trans).getChannel().ID();
NDEBUG_UNUSED(unsigned bg) = ControllerExtension::getExtension(trans).getBankGroup().ID();
NDEBUG_UNUSED(unsigned bank) = ControllerExtension::getExtension(trans).getBank().ID();
NDEBUG_UNUSED(unsigned row) = ControllerExtension::getExtension(trans).getRow().ID();
NDEBUG_UNUSED(unsigned col) = ControllerExtension::getExtension(trans).getColumn().ID();
PRINTDEBUGMESSAGE(this->name(), "Recording " + getPhaseName(phase) + " thread " +
std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string(
bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " +
std::to_string(col) + " at " + recTime.to_string());
Command command(phase);
if (phaseHasDataStrobe(phase))
{
TimeInterval intervalOnDataStrobe = this->memSpec.getIntervalOnDataStrobe(command, trans);
intervalOnDataStrobe.start = intervalOnDataStrobe.start + recTime;
intervalOnDataStrobe.end = intervalOnDataStrobe.end + recTime;
tlmRecorder.recordPhase(trans, phase, recTime, std::move(intervalOnDataStrobe));
}
else
{
tlmRecorder.recordPhase(trans, phase, recTime);
}
if (phaseNeedsEnd(phase))
{
recTime += this->memSpec.getExecutionTime(Command(phase), trans);
tlmRecorder.recordPhase(trans, getEndPhase(phase), recTime);
}
}
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for visualization purposes.
template<class BaseDram>

2
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -57,8 +57,6 @@ private:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_core::sc_time &delay) override;
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay);
TlmRecorder& tlmRecorder;
sc_core::sc_time powerWindowSize;