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Add hazard warning, const members.

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This commit is contained in:
Lukas Steiner
2022-04-06 14:46:40 +02:00
parent b4c70b3e92
commit 2e4be049ac
21 changed files with 66 additions and 81 deletions
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10
DRAMSys/library/src/controller/BankMachine.cpp
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@@ -41,12 +41,10 @@ using namespace sc_core;
using namespace tlm;
BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
: scheduler(scheduler), checker(checker), bank(bank), memSpec(*config.memSpec)
{
rank = Rank(bank.ID() / memSpec.banksPerRank);
bankgroup = BankGroup(bank.ID() / memSpec.banksPerGroup);
refreshManagement = config.refreshManagement;
}
: scheduler(scheduler), checker(checker), memSpec(*config.memSpec), bank(bank),
bankgroup(BankGroup(bank.ID() / memSpec.banksPerGroup)), rank(Rank(bank.ID() / memSpec.banksPerRank)),
refreshManagement(config.refreshManagement)
{}
CommandTuple::Type BankMachine::getNextCommand()
{

8
DRAMSys/library/src/controller/BankMachine.h
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@@ -72,13 +72,13 @@ protected:
Command nextCommand = Command::NOP;
Row openRow;
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
Rank rank = Rank(0);
BankGroup bankgroup = BankGroup(0);
Bank bank;
const Bank bank;
const BankGroup bankgroup;
const Rank rank;
bool blocked = false;
bool sleeping = false;
unsigned refreshManagementCounter = 0;
bool refreshManagement = false;
const bool refreshManagement = false;
bool keepTrans = false;
};

8
DRAMSys/library/src/controller/Controller.cpp
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@@ -70,18 +70,14 @@ using namespace sc_core;
using namespace tlm;
Controller::Controller(const sc_module_name& name, const Configuration& config) :
ControllerIF(name, config)
ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw),
phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw)
{
SC_METHOD(controllerMethod);
sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEvent;
ranksNumberOfPayloads = std::vector<unsigned>(memSpec.ranksPerChannel);
thinkDelayFw = config.thinkDelayFw;
thinkDelayBw = config.thinkDelayBw;
phyDelayFw = config.phyDelayFw;
phyDelayBw = config.phyDelayBw;
// reserve buffer for command tuples
readyCommands.reserve(memSpec.banksPerChannel);

8
DRAMSys/library/src/controller/Controller.h
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@@ -71,10 +71,10 @@ protected:
std::unique_ptr<SchedulerIF> scheduler;
sc_core::sc_time thinkDelayFw;
sc_core::sc_time thinkDelayBw;
sc_core::sc_time phyDelayFw;
sc_core::sc_time phyDelayBw;
const sc_core::sc_time thinkDelayFw;
const sc_core::sc_time thinkDelayBw;
const sc_core::sc_time phyDelayFw;
const sc_core::sc_time phyDelayBw;
private:
unsigned totalNumberOfPayloads = 0;

4
DRAMSys/library/src/controller/ControllerRecordable.cpp
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@@ -42,12 +42,12 @@ using namespace tlm;
ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Configuration& config,
TlmRecorder& tlmRecorder)
: Controller(name, config), tlmRecorder(tlmRecorder),
activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing)
activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing),
windowSizeTime(config.windowSize * memSpec.tCK)
{
if (enableWindowing)
{
sensitive << windowEvent;
windowSizeTime = config.windowSize * memSpec.tCK;
slidingAverageBufferDepth = std::vector<sc_time>(scheduler->getBufferDepth().size());
windowAverageBufferDepth = std::vector<double>(scheduler->getBufferDepth().size());
windowEvent.notify(windowSizeTime);

6
DRAMSys/library/src/controller/ControllerRecordable.h
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@@ -62,15 +62,15 @@ private:
TlmRecorder& tlmRecorder;
sc_core::sc_event windowEvent;
sc_core::sc_time windowSizeTime;
const sc_core::sc_time windowSizeTime;
sc_core::sc_time nextWindowEventTime;
std::vector<sc_core::sc_time> slidingAverageBufferDepth;
std::vector<double> windowAverageBufferDepth;
sc_core::sc_time lastTimeCalled = sc_core::SC_ZERO_TIME;
uint64_t lastNumberOfBeatsServed = 0;
sc_core::sc_time activeTimeMultiplier;
bool enableWindowing;
const sc_core::sc_time activeTimeMultiplier;
const bool enableWindowing;
};
#endif // CONTROLLERRECORDABLE_H

8
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp
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@@ -46,16 +46,12 @@ using namespace tlm;
RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker)
: bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), checker(checker),
memSpec(*config.memSpec)
memSpec(*config.memSpec), maxPostponed(static_cast<int>(config.refreshMaxPostponed)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin)), refreshManagement(config.refreshManagement)
{
timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalAB(),
rank, memSpec.ranksPerChannel);
setUpDummy(refreshPayload, 0, rank);
maxPostponed = static_cast<int>(config.refreshMaxPostponed);
maxPulledin = -static_cast<int>(config.refreshMaxPulledin);
refreshManagement = config.refreshManagement;
}
CommandTuple::Type RefreshManagerAllBank::getNextCommand()

6
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h
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@@ -71,11 +71,11 @@ private:
unsigned activatedBanks = 0;
int flexibilityCounter = 0;
int maxPostponed = 0;
int maxPulledin = 0;
const int maxPostponed;
const int maxPulledin;
bool sleeping = false;
bool refreshManagement = false;
const bool refreshManagement;
};
#endif // REFRESHMANAGERALLBANK_H

7
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.cpp
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@@ -46,7 +46,9 @@ RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config,
std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank,
const CheckerIF& checker)
: powerDownManager(powerDownManager), checker(checker), memSpec(*config.memSpec)
: powerDownManager(powerDownManager), checker(checker), memSpec(*config.memSpec),
maxPostponed(static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerRank / 2)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerRank / 2))
{
timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalP2B(), rank,
memSpec.ranksPerChannel);
@@ -68,9 +70,6 @@ RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config,
remainingBankMachines = allBankMachines;
currentIterator = remainingBankMachines.begin();
currentRefreshPayload = &refreshPayloads[currentIterator->front()];
maxPostponed = static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerRank / 2);
maxPulledin = -static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerRank / 2);
}
CommandTuple::Type RefreshManagerPer2Bank::getNextCommand()

4
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.h
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@@ -75,8 +75,8 @@ private:
std::list<std::vector<BankMachine*>>::iterator currentIterator;
int flexibilityCounter = 0;
int maxPostponed = 0;
int maxPulledin = 0;
const int maxPostponed = 0;
const int maxPulledin = 0;
bool sleeping = false;
bool skipSelection = false;

7
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp
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@@ -44,7 +44,9 @@ using namespace tlm;
RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker)
: powerDownManager(powerDownManager), checker(checker), memSpec(*config.memSpec)
: powerDownManager(powerDownManager), checker(checker), memSpec(*config.memSpec),
maxPostponed(static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerRank)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerRank))
{
timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalPB(), rank,
memSpec.ranksPerChannel);
@@ -56,9 +58,6 @@ RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, std::v
remainingBankMachines = allBankMachines;
currentIterator = remainingBankMachines.begin();
maxPostponed = static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerRank);
maxPulledin = -static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerRank);
}
CommandTuple::Type RefreshManagerPerBank::getNextCommand()

4
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h
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@@ -74,8 +74,8 @@ private:
std::list<BankMachine*>::iterator currentIterator;
int flexibilityCounter = 0;
int maxPostponed = 0;
int maxPulledin = 0;
const int maxPostponed;
const int maxPulledin;
bool sleeping = false;
bool skipSelection = false;

10
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp
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@@ -46,7 +46,10 @@ RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config,
std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank,
const CheckerIF& checker)
: powerDownManager(powerDownManager), checker(checker), memSpec(*config.memSpec)
: powerDownManager(powerDownManager), checker(checker), memSpec(*config.memSpec),
maxPostponed(static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerGroup)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerGroup)),
refreshManagement(config.refreshManagement)
{
timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalSB(), rank,
memSpec.ranksPerChannel);
@@ -72,11 +75,6 @@ RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config,
remainingBankMachines = allBankMachines;
currentIterator = remainingBankMachines.begin();
maxPostponed = static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerGroup);
maxPulledin = -static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerGroup);
refreshManagement = config.refreshManagement;
}
CommandTuple::Type RefreshManagerSameBank::getNextCommand()

6
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h
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@@ -73,13 +73,13 @@ private:
std::list<std::vector<BankMachine *>>::iterator currentIterator;
int flexibilityCounter = 0;
int maxPostponed = 0;
int maxPulledin = 0;
const int maxPostponed;
const int maxPulledin;
bool sleeping = false;
bool skipSelection = false;
bool refreshManagement = false;
const bool refreshManagement;
};
#endif // REFRESHMANAGERSAMEBANK_H

2
DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfs.cpp
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@@ -51,6 +51,8 @@ SchedulerGrpFrFcfs::SchedulerGrpFrFcfs(const Configuration& config)
bufferCounter = std::make_unique<BufferCounterReadWrite>(config.requestBufferSize);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared)
bufferCounter = std::make_unique<BufferCounterShared>(config.requestBufferSize);
SC_REPORT_WARNING("SchedulerGrpFrFcfs", "Hazard detection not yet implemented!");
}
bool SchedulerGrpFrFcfs::hasBufferSpace() const

8
DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp
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@@ -40,7 +40,8 @@
using namespace tlm;
SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) : lowWatermark(0), highWatermark(0)
SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config)
:lowWatermark(config.lowWatermark), highWatermark(config.highWatermark)
{
readBuffer = std::vector<std::list<tlm_generic_payload *>>(config.memSpec->banksPerChannel);
writeBuffer = std::vector<std::list<tlm_generic_payload *>>(config.memSpec->banksPerChannel);
@@ -52,11 +53,10 @@ SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) : lowWat
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared)
bufferCounter = std::make_unique<BufferCounterShared>(config.requestBufferSize);
lowWatermark = config.lowWatermark;
highWatermark = config.highWatermark;
if (lowWatermark == 0 || highWatermark == 0 || lowWatermark == highWatermark)
SC_REPORT_FATAL("SchedulerGrpFrFcfsWm", "Invalid watermark configuration.");
SC_REPORT_WARNING("SchedulerGrpFrFcfsWm", "Hazard detection not yet implemented!");
}
bool SchedulerGrpFrFcfsWm::hasBufferSpace() const

4
DRAMSys/library/src/controller/scheduler/SchedulerGrpFrFcfsWm.h
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@@ -64,8 +64,8 @@ private:
std::vector<std::list<tlm::tlm_generic_payload*>> readBuffer;
std::vector<std::list<tlm::tlm_generic_payload*>> writeBuffer;
std::unique_ptr<BufferCounterIF> bufferCounter;
unsigned lowWatermark;
unsigned highWatermark;
const unsigned lowWatermark;
const unsigned highWatermark;
bool writeMode = false;
};

18
DRAMSys/library/src/simulation/AddressDecoder.h
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@@ -53,17 +53,15 @@ struct DecodedAddress
bankgroup(bankgroup), bank(bank),
row(row), column(column), byte(bytes) {}
DecodedAddress()
: channel(0), rank(0), bankgroup(0),
bank(0), row(0), column(0), byte(0) {}
DecodedAddress() = default;
unsigned channel;
unsigned rank;
unsigned bankgroup;
unsigned bank;
unsigned row;
unsigned column;
unsigned byte;
unsigned channel = 0;
unsigned rank = 0;
unsigned bankgroup = 0;
unsigned bank = 0;
unsigned row = 0;
unsigned column = 0;
unsigned byte = 0;
};
class AddressDecoder

3
DRAMSys/library/src/simulation/Arbiter.cpp
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@@ -52,6 +52,7 @@ Arbiter::Arbiter(const sc_module_name &name, const Configuration& config,
tCK(config.memSpec->tCK),
arbitrationDelayFw(config.arbitrationDelayFw),
arbitrationDelayBw(config.arbitrationDelayBw),
bytesPerBeat(config.memSpec->dataBusWidth / 8),
addressOffset(config.addressOffset)
{
iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);
@@ -59,8 +60,6 @@ Arbiter::Arbiter(const sc_module_name &name, const Configuration& config,
tSocket.register_transport_dbg(this, &Arbiter::transport_dbg);
addressDecoder.print();
bytesPerBeat = config.memSpec->dataBusWidth / 8;
}
ArbiterSimple::ArbiterSimple(const sc_module_name& name, const Configuration& config,

10
DRAMSys/library/src/simulation/Arbiter.h
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@@ -88,12 +88,12 @@ protected:
tlm::tlm_phase &phase, sc_core::sc_time &bwDelay);
unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans);
sc_core::sc_time tCK;
sc_core::sc_time arbitrationDelayFw;
sc_core::sc_time arbitrationDelayBw;
const sc_core::sc_time tCK;
const sc_core::sc_time arbitrationDelayFw;
const sc_core::sc_time arbitrationDelayBw;
unsigned bytesPerBeat;
uint64_t addressOffset;
const unsigned bytesPerBeat;
const uint64_t addressOffset;
};
class ArbiterSimple final : public Arbiter

6
DRAMSys/library/src/simulation/dram/Dram.h
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@@ -58,10 +58,10 @@ protected:
const MemSpec& memSpec;
// Data Storage:
Configuration::StoreMode storeMode;
bool powerAnalysis;
const Configuration::StoreMode storeMode;
const bool powerAnalysis;
unsigned char *memory;
bool useMalloc;
const bool useMalloc;
std::unique_ptr<libDRAMPower> DRAMPower;