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Added LPDDR5. Not tested.

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This commit is contained in:
Iron Prando da Silva
2022-04-04 11:31:42 +02:00
parent 193726c04a
commit 319b774509
13 changed files with 700 additions and 10 deletions
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4
DRAMSys/traceAnalyzer/CMakeLists.txt
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@@ -140,6 +140,10 @@ add_executable(TraceAnalyzer
businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp
businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp
businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp
businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp
businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
businessObjects/dramTimeDependencies/phasedependenciestracker.cpp

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp
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@@ -69,6 +69,7 @@ QString StringMapper::getIDStr(StringMapper::Identifier id) {
{StringMapper::Identifier::RDA, "RDA"},
{StringMapper::Identifier::WRA, "WRA"},
{StringMapper::Identifier::REFPB, "REFPB"},
{StringMapper::Identifier::REFP2B, "REFP2B"},
{StringMapper::Identifier::PRESB, "PRESB"},
{StringMapper::Identifier::RFMAB, "RFMAB"},
{StringMapper::Identifier::REFSB, "REFSB"},
@@ -108,6 +109,7 @@ StringMapper::Identifier StringMapper::getIDEnum(const QString& id) {
{"RDA", StringMapper::Identifier::RDA},
{"WRA", StringMapper::Identifier::WRA},
{"REFPB", StringMapper::Identifier::REFPB},
{"REFP2B", StringMapper::Identifier::REFP2B},
{"PRESB", StringMapper::Identifier::PRESB},
{"RFMAB", StringMapper::Identifier::RFMAB},
{"REFSB", StringMapper::Identifier::REFSB},

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h
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@@ -67,6 +67,7 @@ class StringMapper {
RDA,
WRA,
REFPB,
REFP2B,
PRESB,
RFMAB,
REFSB,

9
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
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@@ -53,6 +53,9 @@ std::shared_ptr<ConfigurationBase> ConfigurationFactory::make(const TraceDB& tdb
} else if (deviceName == "DDR5") {
return std::make_shared<DDR5Configuration>(tdb);
} else if (deviceName == "LPDDR5") {
return std::make_shared<LPDDR5Configuration>(tdb);
} else {
// TODO maybe throw?
throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
@@ -80,6 +83,9 @@ const std::vector<QString> ConfigurationFactory::possiblePhases(const TraceDB& t
} else if (deviceName == "DDR5") {
return TimeDependenciesInfoDDR5::getPossiblePhases();
} else if (deviceName == "LPDDR5") {
return TimeDependenciesInfoLPDDR5::getPossiblePhases();
} else {
// TODO maybe throw?
// throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
@@ -107,6 +113,9 @@ bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) {
} else if (deviceName == "DDR5") {
return true;
} else if (deviceName == "LPDDR5") {
return true;
} else {
return false;
}

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h
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@@ -44,6 +44,7 @@
#include "specialized/HBM2Configuration.h"
#include "specialized/LPDDR4Configuration.h"
#include "specialized/DDR5Configuration.h"
#include "specialized/LPDDR5Configuration.h"
#include "data/tracedb.h"

51
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp Normal file
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@@ -0,0 +1,51 @@
/*
* Copyright (c) 2022, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Iron Prando da Silva
*/
#include "LPDDR5Configuration.h"
#include <memory>
LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) {
mDeviceDeps = std::make_shared<TimeDependenciesInfoLPDDR5>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
}
std::shared_ptr<DBPhaseEntryBase> LPDDR5Configuration::makePhaseEntry(const QSqlQuery& query) const {
auto phase = std::make_shared<LPDDR5DBPhaseEntry>(query);
auto device = std::dynamic_pointer_cast<TimeDependenciesInfoLPDDR5>(mDeviceDeps);
phase->bankOffsetREFP2B = device->getPer2BankOffset();
return phase;
}

48
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h Normal file
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@@ -0,0 +1,48 @@
/*
* Copyright (c) 2022, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Iron Prando da Silva
*/
#pragma once
#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h"
class LPDDR5Configuration : public ConfigurationBase {
public:
LPDDR5Configuration(const TraceDB& tdb);
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

83
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp Normal file
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@@ -0,0 +1,83 @@
/*
* Copyright (c) 2022, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Iron Prando da Silva
*/
#include "LPDDR5dbphaseentry.h"
LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) {
id = query.value(0).toLongLong();
phaseName = StringMapper(query.value(1).toString());
phaseBegin = query.value(2).toLongLong();
phaseEnd = query.value(3).toLongLong();
transact = query.value(4).toLongLong();
tBank = query.value(5).toLongLong();
tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
}
bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
bool isREFP2B = dep.phaseDep == StringMapper::Identifier::REFP2B;
bool const skipOnIntraBankAndDifferentBanks = {
dep.depType == DependencyType::IntraBank
&& (
(tBank != other->tBank)
|| (isREFP2B && tBank != (other->tBank - bankOffsetREFP2B))
)
};
bool const skipOnIntraBankgroupAndDifferentBankgroup = {
dep.depType == DependencyType::IntraBankGroup
&& tBankgroup != other->tBankgroup
};
bool const skipOnIntraRankAndDifferentRanks = {
dep.depType == DependencyType::IntraRank
&& tRank != other->tRank
};
bool const skipOnInterRankAndSameRank = {
dep.depType == DependencyType::InterRank
&& tRank == other->tRank
&& !isCmdPool
};
return !(
skipOnIntraBankAndDifferentBanks
|| skipOnIntraBankgroupAndDifferentBankgroup
|| skipOnIntraRankAndDifferentRanks
|| skipOnInterRankAndSameRank
);
}

49
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h Normal file
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@@ -0,0 +1,49 @@
/*
* Copyright (c) 2022, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Iron Prando da Silva
*/
#pragma once
#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
class LPDDR5DBPhaseEntry : public DBPhaseEntryBase {
public:
LPDDR5DBPhaseEntry(const QSqlQuery&);
size_t tBankgroup;
size_t tRank;
size_t bankOffsetREFP2B;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
};

12
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp
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@@ -180,14 +180,14 @@ DependencyMap TimeDependenciesInfoDDR4::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
{tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"},
{tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"}, //
{tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"},
{tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"},
{tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
{tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"},
{tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"},
{tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
{tWRRD_L, "WR", DependencyType::IntraBank, "tWRRD_L"},
{tWRRD_L, "WR", DependencyType::IntraBank, "tWRRD_L"}, //
{tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"},
{tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"},
{tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
@@ -207,14 +207,14 @@ DependencyMap TimeDependenciesInfoDDR4::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
{tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
{tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"},
{tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, //
{tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"}, //
{tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
{tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"},
{tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"}, //
{tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
{tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"},
{tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"}, //
{tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"},
{tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"},
{tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},

8
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp
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@@ -175,7 +175,7 @@ DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD, "RD", DependencyType::IntraBank, "tCCD"},
{tCCD, "RD", DependencyType::IntraBank, "tCCD"}, //
{tCCD, "RD", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
{tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
@@ -197,7 +197,7 @@ DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
{tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, //
{tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
{tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
@@ -286,7 +286,7 @@ DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const {
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, //
{tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
{tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
@@ -385,7 +385,7 @@ DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tSR, "SREFEN", DependencyType::IntraRank, "tSR"},
{tXP, "SRPDEX", DependencyType::IntraRank, "tXP"},
{tXP, "SRPDEX", DependencyType::IntraRank, "tXP"}, //
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)

357
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp Normal file
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@@ -0,0 +1,357 @@
/* Generated by JetBrains MPS */
#include "TimeDependenciesInfoLPDDR5.h"
using namespace std;
TimeDependenciesInfoLPDDR5::TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
mInitializeValues();
}
void TimeDependenciesInfoLPDDR5::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
per2BankOffset = mMemspecJson["memarchitecturespec"].toObject()["per2BankOffset"].toInt();
tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt();
tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt();
tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt();
tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt();
tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt();
tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt();
tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt();
tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt();
tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
tRBTP = tCK * mMemspecJson["memtimingspec"].toObject()["RBTP"].toInt();
BL_n_min_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_16"].toInt();
BL_n_min_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_32"].toInt();
BL_n_max_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_16"].toInt();
BL_n_max_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_32"].toInt();
BL_n_S_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_16"].toInt();
BL_n_S_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_32"].toInt();
BL_n_L_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_16"].toInt();
BL_n_L_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_32"].toInt();
tWCK2DQO = tCK * mMemspecJson["memtimingspec"].toObject()["WCK2DQO"].toInt();
tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
tpbR2act = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2act"].toInt();
tpbR2pbR = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2pbR"].toInt();
tBURST16 = (uint) (16 / (float) dataRate) * tCK;
tBURST32 = (uint) (32 / (float) dataRate) * tCK;
mPools.insert({
"CMD_BUS", {
1, {
{"ACT", 2 * tCK},
{"RD", tCK},
{"WR", tCK},
{"RDA", tCK},
{"WRA", tCK},
{"PREPB", tCK},
{"PREAB", tCK},
{"REFAB", tCK},
{"REFPB", tCK},
{"REFP2B", tCK},
}
}
});
mPools.insert({
"NAW", {
4, {
{"ACT", tFAW},
{"REFPB", tFAW},
{"REFP2B", tFAW},
}
}
});
}
const std::vector<QString> TimeDependenciesInfoLPDDR5::getPossiblePhases() {
return {
"ACT",
"RD",
"WR",
"PREPB",
"RDA",
"WRA",
"REFPB",
"REFP2B",
"REFAB",
"PREAB",
};
}
DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
DependencyMap dmap;
dmap.emplace(
piecewise_construct,
forward_as_tuple("ACT"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
{tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
{BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK"},
{BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK"},
{tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"},
{tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"},
{tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"},
{tpbR2act - tCK, "REFPB", DependencyType::IntraRank, "tpbR2act - tCK"},
{tpbR2act - tCK, "REFP2B", DependencyType::IntraRank, "tpbR2act - tCK"},
{tRFCpb - tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - tCK"},
{tRFCpb - tCK, "REFP2B", DependencyType::IntraBank, "tRFCpb - tCK"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
{0, "NAW", DependencyType::IntraRank, "tFAW"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("RD"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("WR"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PREPB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP"},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR"},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("RDA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("WRA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("REFAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PREAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
{BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
{tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("REFPB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
{tpbR2pbR, "REFPB", DependencyType::IntraRank, "tpbR2pbR"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
{0, "NAW", DependencyType::IntraRank, "tFAW"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("REFP2B"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"},
{tpbR2pbR, "REFP2B", DependencyType::IntraRank, "tpbR2pbR"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
{0, "NAW", DependencyType::IntraRank, "tFAW"},
}
)
);
return dmap;
}

85
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h Normal file
View File

@@ -0,0 +1,85 @@
/* Generated by JetBrains MPS */
#pragma once
#include "../dramtimedependenciesbase.h"
class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase {
public:
TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint clk);
static const std::vector<QString> getPossiblePhases();
uint getPer2BankOffset() { return per2BankOffset; }
protected:
void mInitializeValues() override;
DependencyMap mSpecializedGetDependencies() const override;
protected:
uint burstLength;
uint dataRate;
uint per2BankOffset;
uint tRCD;
uint tRPpb;
uint tRPab;
uint tRAS;
uint tRCpb;
uint tRCab;
uint tCL;
uint tCWL;
uint tAL;
uint tRL;
uint tRPRE;
uint tWPRE;
uint tWL;
uint tCCD_S;
uint tCCD_L;
uint tRRD;
uint tFAW;
uint tWTR_S;
uint tWTR_L;
uint tRTP;
uint tWR;
uint tRFCab;
uint tRFCpb;
uint tXS;
uint tXSDLL;
uint tXP;
uint tCKE;
uint tCKESR;
uint tPD;
uint tPRPDEN;
uint tREFPDEN;
uint tRTRS;
uint tRBTP;
uint BL_n_min_16;
uint BL_n_min_32;
uint BL_n_max_16;
uint BL_n_max_32;
uint BL_n_S_16;
uint BL_n_S_32;
uint BL_n_L_16;
uint BL_n_L_32;
uint tWCK2DQO;
uint tPPD;
uint tpbR2act;
uint tpbR2pbR;
uint tBURST16;
uint tBURST32;
uint tRDWR;
uint tRDWR_R;
uint tWRRD_S;
uint tWRRD_L;
uint tWRRD_R;
uint tRDAACT;
uint tWRPRE;
uint tWRAACT;
uint tRDPDEN;
uint tWRPDEN;
uint tWRAPDEN;
};