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Added LPDDR4 dependencies.

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This commit is contained in:
Iron Prando da Silva
2022-03-08 10:50:26 +01:00
parent 20f783ad38
commit 9eda19eb00
10 changed files with 570 additions and 2 deletions
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5
DRAMSys/traceAnalyzer/CMakeLists.txt
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@@ -131,7 +131,10 @@ add_executable(TraceAnalyzer
businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp
businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp
businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp
businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp
businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp
businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp
businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
businessObjects/dramTimeDependencies/phasedependenciestracker.cpp

9
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
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@@ -47,6 +47,9 @@ std::shared_ptr<ConfigurationIF> ConfigurationFactory::make(const TraceDB& tdb)
} else if (deviceName == "HBM2") {
return std::make_shared<HBM2Configuration>(tdb);
} else if (deviceName == "LPDDR4") {
return std::make_shared<LPDDR4Configuration>(tdb);
} else {
// TODO maybe throw?
throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
@@ -68,6 +71,9 @@ const std::vector<QString> ConfigurationFactory::possiblePhases(const TraceDB& t
} else if (deviceName == "HBM2") {
return TimeDependenciesInfoHBM2::getPossiblePhases();
} else if (deviceName == "LPDDR4") {
return TimeDependenciesInfoLPDDR4::getPossiblePhases();
} else {
// TODO maybe throw?
// throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
@@ -89,6 +95,9 @@ bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) {
} else if (deviceName == "HBM2") {
return true;
} else if (deviceName == "LPDDR4") {
return true;
} else {
return false;
}

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h
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@@ -38,9 +38,12 @@
#include <memory>
#include "configurationIF.h"
#include "specialized/DDR3Configuration.h"
#include "specialized/DDR4Configuration.h"
#include "specialized/HBM2Configuration.h"
#include "specialized/LPDDR4Configuration.h"
#include "data/tracedb.h"
class ConfigurationFactory {

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h
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@@ -2,7 +2,7 @@
#pragma once
#include "businessObjects/dramTimeDependencies/configurations/configurationIF.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h"
// #include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h"

12
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp Normal file
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@@ -0,0 +1,12 @@
#include "LPDDR4Configuration.h"
LPDDR4Configuration::LPDDR4Configuration(const TraceDB& tdb) {
// mDeviceDeps = std::make_shared<LPDDR4TimeDependencies>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
mDeviceDeps = std::make_shared<TimeDependenciesInfoLPDDR4>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
}
std::shared_ptr<DBPhaseEntryIF> LPDDR4Configuration::makePhaseEntry(const QSqlQuery& query) const {
return std::make_shared<LPDDR4DBPhaseEntry>(query);
}

14
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h Normal file
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@@ -0,0 +1,14 @@
#pragma once
#include "businessObjects/dramTimeDependencies/configurations/configurationIF.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h"
class LPDDR4Configuration : public ConfigurationIF {
public:
LPDDR4Configuration(const TraceDB& tdb);
std::shared_ptr<DBPhaseEntryIF> makePhaseEntry(const QSqlQuery&) const override;
};

36
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp Normal file
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@@ -0,0 +1,36 @@
#include "LPDDR4dbphaseentry.h"
LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) {
id = query.value(0).toLongLong();
phaseName = StringMapper(query.value(1).toString());
phaseBegin = query.value(2).toLongLong();
phaseEnd = query.value(3).toLongLong();
transact = query.value(4).toLongLong();
tBank = query.value(5).toLongLong();
// tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
}
bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryIF> otherPhase) const {
auto other = std::dynamic_pointer_cast<LPDDR4DBPhaseEntry>(otherPhase);
if (!other) return false;
bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
bool const skipOnIntraBankAndDifferentBanks = {
dep.depType == DependencyType::IntraBank
&& tBank != other->tBank
};
bool const skipOnIntraRankAndDifferentRanks = {
dep.depType == DependencyType::IntraRank
&& tRank != other->tRank
};
bool const skipOnInterRankAndSameRank = {
dep.depType == DependencyType::InterRank
&& tRank == other->tRank
&& !isCmdPool
};
return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank);
}

14
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h Normal file
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@@ -0,0 +1,14 @@
#pragma once
#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryIF.h"
class LPDDR4DBPhaseEntry : public DBPhaseEntryIF {
public:
LPDDR4DBPhaseEntry(const QSqlQuery&);
// size_t tBankgroup;
size_t tRank;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryIF> otherPhase) const override;
};

409
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp Normal file
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@@ -0,0 +1,409 @@
/* Generated by JetBrains MPS */
#include "TimeDependenciesInfoLPDDR4.h"
using namespace std;
TimeDependenciesInfoLPDDR4::TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesIF(memspec, tCK) {
mInitializeValues();
}
void TimeDependenciesInfoLPDDR4::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"RDA",
"WRA",
"PREPB",
"PREAB",
"REFAB",
"SREFEN",
"SREFEX",
"REFPB",
}
}
});
mPools.insert({
"NAW", {
4, {
"ACT",
"REFPB",
}
}
});
tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt();
tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt();
tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt();
tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt();
tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt();
tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt();
tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt();
tDQSCK = tCK * mMemspecJson["memtimingspec"].toObject()["DQSCK"].toInt();
tDQSS = tCK * mMemspecJson["memtimingspec"].toObject()["DQSS"].toInt();
tDQS2DQ = tCK * mMemspecJson["memtimingspec"].toObject()["DQS2DQ"].toInt();
tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt();
tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt();
tESCKE = tCK * mMemspecJson["memtimingspec"].toObject()["ESCKE"].toInt();
tSR = tCK * mMemspecJson["memtimingspec"].toObject()["SR"].toInt();
tXSR = tCK * mMemspecJson["memtimingspec"].toObject()["XSR"].toInt();
tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
tCMDCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CMDCKE"].toInt();
tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
tBURST = (uint) (burstLength / (float) dataRate) * tCK;
tRDWR = tRL + tDQSCK + tBURST - tWL + tWPRE + tRPST;
tRDWR_R = tRL + tBURST + tRTRS - tWL;
tWRRD = tWL + tCK + tBURST + tWTR;
tWRRD_R = tWL + tBURST + tRTRS - tRL;
tRDPRE = tRTP + tBURST - 6 * tCK;
tRDAACT = tRTP + tRPpb + tBURST - 8 * tCK;
tWRPRE = 2 * tCK + tWL + tCK + tBURST + tWR;
tWRAACT = tWL + tBURST + tWR + tCK + tRPpb;
tACTPDEN = 3 * tCK + tCMDCKE;
tPRPDEN = tCK + tCMDCKE;
tRDPDEN = 3 * tCK + tRL + tDQSCK + tBURST + tRPST;
tWRPDEN = 3 * tCK + tWL + (ceil((uint) (tDQSS / (float) tCK)) + ceil((uint) (tDQS2DQ / (float) tCK))) * tCK + tBURST + tWR;
tWRAPDEN = 3 * tCK + tWL + (ceil((uint) (tDQSS / (float) tCK)) + ceil((uint) (tDQS2DQ / (float) tCK))) * tCK + tBURST + tWR + 2 * tCK;
tREFPDEN = tCK + tCMDCKE;
tSREFPDEN = tCK + tESCKE;
}
const std::vector<QString> TimeDependenciesInfoLPDDR4::getPossiblePhases() {
return {
"ACT",
"RD",
"WR",
"PREPB",
"RDA",
"WRA",
"REFPB",
"REFAB",
"PREAB",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
"PDEA",
"PDXA",
"SRPDEN",
"SRPDEX",
};
}
DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const {
DependencyMap dmap;
dmap.emplace(
piecewise_construct,
forward_as_tuple("ACT"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
{tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
{tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
{tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
{tRPpb - 2 * tCK, "PREPB", DependencyType::IntraBank, "tRPpb - 2 * tCK"},
{tRPab - 2 * tCK, "PREAB", DependencyType::IntraRank, "tRPab - 2 * tCK"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tRFCab - 2 * tCK, "REFAB", DependencyType::IntraRank, "tRFCab - 2 * tCK"},
{tRFCpb - 2 * tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - 2 * tCK"},
{tRRD - 2 * tCK, "REFPB", DependencyType::IntraRank, "tRRD - 2 * tCK"},
{tXSR - 2 * tCK, "SREFEX", DependencyType::IntraRank, "tXSR - 2 * tCK"},
{4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
{tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("RD"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD, "RD", DependencyType::IntraBank, "tCCD"},
{tCCD, "RD", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
{tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
{tWRRD, "WR", DependencyType::IntraBank, "tWRRD"},
{tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
{tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
{tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
{tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("WR"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
{tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
{tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
{tCCD, "WR", DependencyType::IntraBank, "tCCD"},
{tCCD, "WR", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
{tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PREPB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + 2 * tCK, "ACT", DependencyType::IntraBank, "tRAS + 2 * tCK"},
{tRDPRE, "RD", DependencyType::IntraBank, "tRDPRE"},
{tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("RDA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD, "RD", DependencyType::IntraBank, "tCCD"},
{tCCD, "RD", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
{tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
{max({tWRRD, tWRPRE - tRDPRE}), "WR", DependencyType::IntraBank, "max(tWRRD, tWRPRE - tRDPRE)"},
{tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
{tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
{tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
{tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("WRA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
{tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
{tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
{tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
{tCCD, "WR", DependencyType::IntraBank, "tCCD"},
{tCCD, "WR", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
{tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
{tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("REFPB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + 2 * tCK, "ACT", DependencyType::IntraBank, "tRCpb + 2 * tCK"},
{tRRD + 2 * tCK, "ACT", DependencyType::IntraRank, "tRRD + 2 * tCK"},
{tRDPRE + tRPpb, "RDA", DependencyType::IntraBank, "tRDPRE + tRPpb"},
{tWRPRE + tRPpb, "WRA", DependencyType::IntraBank, "tWRPRE + tRPpb"},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
{tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
{tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
{tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("REFAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"},
{tRDPRE + tRPpb, "RDA", DependencyType::IntraRank, "tRDPRE + tRPpb"},
{tWRPRE + tRPpb, "WRA", DependencyType::IntraRank, "tWRPRE + tRPpb"},
{tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
{tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
{tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PREAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + 2 * tCK, "ACT", DependencyType::IntraRank, "tRAS + 2 * tCK"},
{tRDPRE, "RD", DependencyType::IntraRank, "tRDPRE"},
{tRDPRE, "RDA", DependencyType::IntraRank, "tRDPRE"},
{tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
{tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PDEP"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
{tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
{tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
{tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
{tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
{tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
{tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
{tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"},
{tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PDXP"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tCKE, "PDEP", DependencyType::IntraRank, "tCKE"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("SREFEN"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"},
{max({tRDPDEN, tRDPRE + tRPpb}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tRDPRE + tRPpb)"},
{max({tWRAPDEN, tWRPRE + tRPpb}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRPpb)"},
{tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
{tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
{tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("SREFEX"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tSR, "SREFEN", DependencyType::IntraRank, "tSR"},
{tXP, "SRPDEX", DependencyType::IntraRank, "tXP"},
{2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PDEA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
{tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
{tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
{tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
{tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
{tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
{tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
{tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PDXA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tCKE, "PDEA", DependencyType::IntraRank, "tCKE"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("SRPDEN"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tSREFPDEN, "SREFEN", DependencyType::IntraRank, "tSREFPDEN"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("SRPDEX"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tCKE, "SRPDEN", DependencyType::IntraRank, "tCKE"},
}
)
);
return dmap;
}

68
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h Normal file
View File

@@ -0,0 +1,68 @@
/* Generated by JetBrains MPS */
#pragma once
#include "../dramtimedependenciesIF.h"
class TimeDependenciesInfoLPDDR4 final : public DRAMTimeDependenciesIF {
public:
TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint clk);
static const std::vector<QString> getPossiblePhases();
protected:
void mInitializeValues() override;
DependencyMap mSpecializedGetDependencies() const override;
protected:
uint burstLength;
uint dataRate;
uint tRRD;
uint tRCD;
uint tRAS;
uint tFAW;
uint tRPpb;
uint tRPab;
uint tRCpb;
uint tRCab;
uint tCCD;
uint tRTP;
uint tWR;
uint tWTR;
uint tPPD;
uint tWPRE;
uint tRPST;
uint tDQSCK;
uint tDQSS;
uint tDQS2DQ;
uint tRL;
uint tWL;
uint tRFCab;
uint tRFCpb;
uint tESCKE;
uint tSR;
uint tXSR;
uint tXP;
uint tCKE;
uint tCMDCKE;
uint tRTRS;
uint tBURST;
uint tRDWR;
uint tRDWR_R;
uint tWRRD;
uint tWRRD_R;
uint tRDPRE;
uint tRDAACT;
uint tWRPRE;
uint tWRAACT;
uint tACTPDEN;
uint tPRPDEN;
uint tRDPDEN;
uint tWRPDEN;
uint tWRAPDEN;
uint tREFPDEN;
uint tSREFPDEN;
};