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Modified DDR5 to comply with time checker.

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This commit is contained in:
Iron Prando da Silva
2022-03-16 10:42:22 +01:00
parent addb7aae31
commit 866ccd7764
4 changed files with 290 additions and 57 deletions
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8
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp
View File

@@ -35,6 +35,10 @@ QString StringMapper::getIDStr(StringMapper::Identifier id) {
{StringMapper::Identifier::RDA, "RDA"},
{StringMapper::Identifier::WRA, "WRA"},
{StringMapper::Identifier::REFPB, "REFPB"},
{StringMapper::Identifier::PRESB, "PRESB"},
{StringMapper::Identifier::RFMAB, "RFMAB"},
{StringMapper::Identifier::REFSB, "REFSB"},
{StringMapper::Identifier::RFMSB, "RFMSB"},
};
auto it = enumToStr.find(id);
@@ -70,6 +74,10 @@ StringMapper::Identifier StringMapper::getIDEnum(const QString& id) {
{"RDA", StringMapper::Identifier::RDA},
{"WRA", StringMapper::Identifier::WRA},
{"REFPB", StringMapper::Identifier::REFPB},
{"PRESB", StringMapper::Identifier::PRESB},
{"RFMAB", StringMapper::Identifier::RFMAB},
{"REFSB", StringMapper::Identifier::REFSB},
{"RFMSB", StringMapper::Identifier::RFMSB},
};
auto it = strToEnum.find(id);

56
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h
View File

@@ -7,32 +7,36 @@
class StringMapper {
public:
enum Identifier {
None,
CMD_BUS,
RAS_BUS,
CAS_BUS,
NAW,
FAW,
_32AW,
FAW_LOGICAL,
FAW_PHYSICAL,
REFAB,
PREAB,
PDEP,
PDXP,
SREFEN,
SREFEX,
PDEA,
PDXA,
SRPDEN,
SRPDEX,
ACT,
RD,
WR,
PREPB,
RDA,
WRA,
REFPB
None,
CMD_BUS,
RAS_BUS,
CAS_BUS,
NAW,
FAW,
_32AW,
FAW_LOGICAL,
FAW_PHYSICAL,
REFAB,
PREAB,
PDEP,
PDXP,
SREFEN,
SREFEX,
PDEA,
PDXA,
SRPDEN,
SRPDEX,
ACT,
RD,
WR,
PREPB,
RDA,
WRA,
REFPB,
PRESB,
RFMAB,
REFSB,
RFMSB
};
public:

274
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
View File

@@ -32,6 +32,8 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt();
cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt();
mPools.insert({
"CMD_BUS", {
@@ -44,6 +46,10 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
"PREPB",
"PREAB",
"REFAB",
"PRESB",
"RFMAB",
"REFSB",
"RFMSB",
}
}
});
@@ -52,6 +58,8 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
"FAW_LOGICAL", {
4, {
"ACT",
"REFSB",
"RFMSB",
}
}
});
@@ -60,6 +68,8 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
"FAW_PHYSICAL", {
4, {
"ACT",
"REFSB",
"RFMSB",
}
}
});
@@ -124,30 +134,45 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI2"].toInt();
}
if (cmdMode == 2) {
shortCmdOffset = 1 * tCK;
longCmdOffset = 3 * tCK;
} else {
shortCmdOffset = 0 * tCK;
longCmdOffset = 1 * tCK;
}
cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
if (!(burstLength == 16 && bitWidth == 4))
tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt();
tBURST16 = 8 * tCK;
tBURST32 = 16 * tCK;
tRD_BURST = (uint) (RBL / (float) dataRate) * tCK;
tWR_BURST = (uint) (WBL / (float) dataRate) * tCK;
tWTRA = tWR - tRTP;
tWRRDA = tWL + tWR_BURST + tWTRA;
tWRPRE = tWL + tWR_BURST + tWR;
tWRRDA = tWL + tBURST16 + tWTRA;
tWRPRE = tWL + tBURST16 + tWR;
tRDAACT = tRTP + tRP;
tWRAACT = tWRPRE + tRP;
tCCD_L_RTW_slr = tRL - tWL + tRD_BURST + 2 * tCK - tRDDQS + tRPST + tWPRE;
tCCD_S_RTW_slr = tRL - tWL + tRD_BURST + 2 * tCK - tRDDQS + tRPST + tWPRE;
tCCD_RTW_dlr = tRL - tWL + tRD_BURST + 2 * tCK - tRDDQS + tRPST + tWPRE;
tCCD_L_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
tCCD_S_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
tCCD_RTW_dlr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
tRDRD_dpr = tRD_BURST + tRTRS;
tRDRD_ddr = tRD_BURST + tRTRS;
tRDWR_dpr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE;
tRDWR_ddr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE;
tCCD_L_WTR_slr = tWL + tWR_BURST + tWTR_L;
tCCD_S_WTR_slr = tWL + tWR_BURST + tWTR_S;
tCCD_WTR_dlr = tWL + tWR_BURST + tWTR_S;
tWRWR_dpr = max(tCCD_WR_dpr, tWR_BURST + tRTRS);
tWRWR_ddr = tWR_BURST + tRTRS;
tWRRD_dpr = tWL - tRL + tWR_BURST + tRTRS + tRDDQS + tWPST + tRPRE;
tWRRD_ddr = tWL - tRL + tWR_BURST + tRTRS + tRDDQS + tWPST + tRPRE;
tRDPDEN = tRL + tRD_BURST + tCK;
tWRPDEN = tWL + tWR_BURST + tWR + tCK;
tWRAPDEN = tWL + tWR_BURST + tWR + tCK;
tCCD_L_WTR_slr = tWL + tBURST16 + tWTR_L;
tCCD_S_WTR_slr = tWL + tBURST16 + tWTR_S;
tCCD_WTR_dlr = tWL + tBURST16 + tWTR_S;
tWRWR_dpr = max(tCCD_WR_dpr, tBURST16 + tRTRS);
tWRWR_ddr = tBURST16 + tRTRS;
tWRRD_dpr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE;
tWRRD_ddr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE;
tRDPDEN = tRL + tBURST16 + cmdLengthDiff;
tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
}
@@ -156,9 +181,13 @@ const std::vector<QString> TimeDependenciesInfoDDR5::getPossiblePhases() {
"ACT",
"RD",
"WR",
"PRESB",
"PREPB",
"RDA",
"WRA",
"RFMAB",
"REFSB",
"RFMSB",
"REFAB",
"PREAB",
"PDEP",
@@ -184,12 +213,21 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"},
{tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
{tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
{tRP - tCK, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
{tRP - tCK, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"},
{tRFC_slr - tCK, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
{tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"},
{tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
{tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankGroup, "tRP - tCK"},
{tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"},
{tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
{tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
{tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankGroup, "tRFCsb_slr - tCK"},
{tREFSBRD_slr - cmdLengthDiff, "REFSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
{tREFSBRD_dlr - cmdLengthDiff, "REFSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
{tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankGroup, "tRFCsb_slr - tCK"},
{tREFSBRD_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
{tREFSBRD_dlr - cmdLengthDiff, "RFMSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
{tFAW_slr, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
{tFAW_dlr, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
{tFAW_slr - longCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
{tFAW_dlr - longCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
}
)
);
@@ -203,23 +241,39 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -232,25 +286,42 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"},
{tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -261,11 +332,13 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
forward_as_tuple("PREPB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
{tRTP + tCK, "RD", DependencyType::IntraBank, "tRTP + tCK"},
{tWRPRE + tCK, "WR", DependencyType::IntraBank, "tWRPRE + tCK"},
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16"},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -280,24 +353,41 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA"},
{tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16"},
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -310,25 +400,42 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"},
{tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -339,29 +446,134 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
forward_as_tuple("REFAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRC + tCK, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
{tRDAACT + tCK, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
{tWRPRE + tRP + tCK, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"},
{tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
{tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("RFMAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"},
{tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
{tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("REFSB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"},
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"},
{tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"},
{tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
{tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
{tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
{tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
{tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
{tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("RFMSB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"},
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"},
{tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"},
{tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
{tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
{tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
{tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
{tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
{tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
{tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PREAB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"},
{tRTP + tCK, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"},
{tRTP + tCK, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"},
{tWRPRE + tCK, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
{tWRPRE + tCK, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"},
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("PRESB"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankGroup, "tRTP + tCK"},
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankGroup, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRPRE + tCK + tBURST16"},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},

9
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h
View File

@@ -98,6 +98,15 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesIF {
uint tWRPDEN;
uint tWRAPDEN;
uint cmdMode;
uint bitWidth;
uint cmdLengthDiff;
uint shortCmdOffset;
uint longCmdOffset;
uint tBURST16;
uint tBURST32;
protected:
uint mBitsDIMMRanks;
uint mBitsPhysicalRanks;