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Remove unused END phases.

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This commit is contained in:
Lukas Steiner
2022-05-02 14:24:18 +02:00
parent 26d7e3e83e
commit 489fa5f02b
3 changed files with 114 additions and 135 deletions
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66
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -122,32 +122,18 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase
if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end())
introduceTransactionSystem(trans);
if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA)
{
assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name);
// TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions
if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF)
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay
+ memSpec.getCommandLength(Command(phase));
else
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay;
}
else if (phase == BEGIN_REQ || phase == BEGIN_RESP)
if (phase == BEGIN_REQ || phase == BEGIN_RESP)
{
std::string phaseName = getPhaseName(phase).substr(6);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(phaseName, currentTime + delay);
}
else if (phase == BEGIN_PDNA || phase == BEGIN_PDNP || phase == BEGIN_SREF)
else if (phase == END_REQ || phase == END_RESP)
{
std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"
const ControllerExtension& extension = ControllerExtension::getExtension(trans);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName),
std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)),
std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)),
extension.getRank(), extension.getBankGroup(), extension.getBank(),
extension.getRow(), extension.getColumn(), extension.getBurstLength());
assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem.at(&trans).recordedPhases.back().name);
// TODO: this assumes that the controller does not start with a transaction until END_REQ has been sent, which is not true any more for big transactions
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay;
}
else
else if (isFixedCommandPhase(phase))
{
std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"
const ControllerExtension& extension = ControllerExtension::getExtension(trans);
@@ -160,31 +146,29 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase
}
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName),
std::move(TimeInterval(currentTime + delay, currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))),
std::move(TimeInterval(currentTime + delay,
currentTime + delay + memSpec.getExecutionTime(Command(phase), trans))),
std::move(intervalOnDataStrobe), extension.getRank(), extension.getBankGroup(), extension.getBank(),
extension.getRow(), extension.getColumn(), extension.getBurstLength());
}
else if (isPowerDownEntryPhase(phase))
{
std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"
const ControllerExtension& extension = ControllerExtension::getExtension(trans);
currentTransactionsInSystem.at(&trans).recordedPhases.emplace_back(std::move(phaseName),
std::move(TimeInterval(currentTime + delay, SC_ZERO_TIME)),
std::move(TimeInterval(SC_ZERO_TIME, SC_ZERO_TIME)),
extension.getRank(), extension.getBankGroup(), extension.getBank(),
extension.getRow(), extension.getColumn(), extension.getBurstLength());
}
else if (isPowerDownExitPhase(phase))
{
currentTransactionsInSystem.at(&trans).recordedPhases.back().interval.end = currentTime + delay
+ memSpec.getCommandLength(Command(phase));
}
if (currentTransactionsInSystem.at(&trans).cmd == 'X')
{
if (phase == BEGIN_REFAB
|| phase == BEGIN_RFMAB
|| phase == BEGIN_REFPB
|| phase == BEGIN_RFMPB
|| phase == BEGIN_REFP2B
|| phase == BEGIN_RFMP2B
|| phase == BEGIN_REFSB
|| phase == BEGIN_RFMSB
|| phase == END_PDNA
|| phase == END_PDNP
|| phase == END_SREF)
removeTransactionFromSystem(trans);
}
else
{
if (phase == END_RESP)
removeTransactionFromSystem(trans);
}
if (phase == END_RESP || isRefreshCommandPhase(phase) || isPowerDownExitPhase(phase))
removeTransactionFromSystem(trans);
simulationTimeCoveredByRecording = currentTime + delay;
}

154
DRAMSys/library/src/controller/Command.cpp
View File

@@ -42,6 +42,65 @@
using namespace tlm;
using namespace DRAMPower;
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
{
// TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
assert(phase >= BEGIN_NOP && phase <= END_SREF);
static std::array<MemCommand::cmds, Command::Type::END_ENUM> phaseOfCommand =
{
MemCommand::NOP, // 0
MemCommand::RD, // 1
MemCommand::WR, // 2
MemCommand::RDA, // 3
MemCommand::WRA, // 4
MemCommand::ACT, // 5
MemCommand::PRE, // 6, PREPB
MemCommand::REFB, // 7, REFPB
MemCommand::NOP, // 8, RFMPB
MemCommand::NOP, // 9, REFP2B
MemCommand::NOP, // 10, RFMP2B
MemCommand::NOP, // 11, PRESB
MemCommand::NOP, // 12, REFSB
MemCommand::NOP, // 13, RFMSB
MemCommand::PREA, // 14, PREAB
MemCommand::REF, // 15, REFAB
MemCommand::NOP, // 16, RFMAB
MemCommand::PDN_S_ACT, // 17
MemCommand::PDN_S_PRE, // 18
MemCommand::SREN, // 19
MemCommand::PUP_ACT, // 20
MemCommand::PUP_PRE, // 21
MemCommand::SREX // 22
};
return phaseOfCommand[phase - BEGIN_NOP];
}
bool phaseHasDataStrobe(tlm::tlm_phase phase)
{
return (phase >= BEGIN_RD && phase <= BEGIN_WRA);
}
bool isPowerDownEntryPhase(tlm::tlm_phase phase)
{
return (phase >= BEGIN_PDNA && phase <= BEGIN_SREF);
}
bool isPowerDownExitPhase(tlm::tlm_phase phase)
{
return (phase >= END_PDNA && phase <= END_SREF);
}
bool isFixedCommandPhase(tlm::tlm_phase phase)
{
return (phase >= BEGIN_NOP && phase <= BEGIN_RFMAB);
}
bool isRefreshCommandPhase(tlm::tlm_phase phase)
{
return (phase == BEGIN_REFPB || phase == BEGIN_REFP2B || phase == BEGIN_REFSB || phase == BEGIN_REFAB
|| phase == BEGIN_RFMPB || phase == BEGIN_RFMP2B || phase == BEGIN_RFMSB || phase == BEGIN_RFMAB);
}
Command::Command(Command::Type type) : type(type) {}
Command::Command(tlm_phase phase)
@@ -118,82 +177,33 @@ tlm_phase Command::toPhase() const
assert(type >= Command::NOP && type <= Command::SREFEX);
static std::array<tlm_phase, Command::Type::END_ENUM> phaseOfCommand =
{
BEGIN_NOP, // 0
BEGIN_RD, // 1
BEGIN_WR, // 2
BEGIN_RDA, // 3
BEGIN_WRA, // 4
BEGIN_ACT, // 5
BEGIN_PREPB, // 6
BEGIN_REFPB, // 7
BEGIN_RFMPB, // 8
BEGIN_REFP2B, // 9
BEGIN_RFMP2B, // 10
BEGIN_PRESB, // 11
BEGIN_REFSB, // 12
BEGIN_RFMSB, // 13
BEGIN_PREAB, // 14
BEGIN_REFAB, // 15
BEGIN_RFMAB, // 16
BEGIN_PDNA, // 17
BEGIN_PDNP, // 18
BEGIN_SREF, // 19
END_PDNA, // 20
END_PDNP, // 21
END_SREF // 22
BEGIN_NOP, // 0
BEGIN_RD, // 1
BEGIN_WR, // 2
BEGIN_RDA, // 3
BEGIN_WRA, // 4
BEGIN_ACT, // 5
BEGIN_PREPB, // 6
BEGIN_REFPB, // 7
BEGIN_RFMPB, // 8
BEGIN_REFP2B, // 9
BEGIN_RFMP2B, // 10
BEGIN_PRESB, // 11
BEGIN_REFSB, // 12
BEGIN_RFMSB, // 13
BEGIN_PREAB, // 14
BEGIN_REFAB, // 15
BEGIN_RFMAB, // 16
BEGIN_PDNA, // 17
BEGIN_PDNP, // 18
BEGIN_SREF, // 19
END_PDNA, // 20
END_PDNP, // 21
END_SREF // 22
};
return phaseOfCommand[type];
}
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
{
// TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
assert(phase >= BEGIN_NOP && phase <= END_SREF);
static std::array<MemCommand::cmds, Command::Type::END_ENUM> phaseOfCommand =
{
MemCommand::NOP, // 0
MemCommand::RD, // 1
MemCommand::WR, // 2
MemCommand::RDA, // 3
MemCommand::WRA, // 4
MemCommand::ACT, // 5
MemCommand::PRE, // 6, PREPB
MemCommand::REFB, // 7, REFPB
MemCommand::NOP, // 8, RFMPB
MemCommand::NOP, // 9, REFP2B
MemCommand::NOP, // 10, RFMP2B
MemCommand::NOP, // 11, PRESB
MemCommand::NOP, // 12, REFSB
MemCommand::NOP, // 13, RFMSB
MemCommand::PREA, // 14, PREAB
MemCommand::REF, // 15, REFAB
MemCommand::NOP, // 16, RFMAB
MemCommand::PDN_S_ACT, // 17
MemCommand::PDN_S_PRE, // 18
MemCommand::SREN, // 19
MemCommand::PUP_ACT, // 20
MemCommand::PUP_PRE, // 21
MemCommand::SREX // 22
};
return phaseOfCommand[phase - BEGIN_NOP];
}
bool phaseNeedsEnd(tlm_phase phase)
{
return (phase >= BEGIN_NOP && phase <= BEGIN_RFMAB);
}
bool phaseHasDataStrobe(tlm_phase phase)
{
return (phase >= BEGIN_RD && phase <= BEGIN_WRA);
}
tlm_phase getEndPhase(tlm_phase phase)
{
assert(phase >= BEGIN_NOP && phase <= BEGIN_RFMAB);
return (phase + Command::Type::END_ENUM);
}
bool Command::isBankCommand() const
{
assert(type >= Command::NOP && type <= Command::SREFEX);

29
DRAMSys/library/src/controller/Command.h
View File

@@ -69,6 +69,7 @@ DECLARE_EXTENDED_PHASE(BEGIN_RFMSB); // 18
DECLARE_EXTENDED_PHASE(BEGIN_PREAB); // 19
DECLARE_EXTENDED_PHASE(BEGIN_REFAB); // 20
DECLARE_EXTENDED_PHASE(BEGIN_RFMAB); // 21
DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 22
DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 23
DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 24
@@ -77,23 +78,12 @@ DECLARE_EXTENDED_PHASE(END_PDNA); // 25
DECLARE_EXTENDED_PHASE(END_PDNP); // 26
DECLARE_EXTENDED_PHASE(END_SREF); // 27
DECLARE_EXTENDED_PHASE(END_NOP); // 28
DECLARE_EXTENDED_PHASE(END_RD); // 29
DECLARE_EXTENDED_PHASE(END_WR); // 30
DECLARE_EXTENDED_PHASE(END_RDA); // 31
DECLARE_EXTENDED_PHASE(END_WRA); // 32
DECLARE_EXTENDED_PHASE(END_ACT); // 33
DECLARE_EXTENDED_PHASE(END_PREPB); // 34
DECLARE_EXTENDED_PHASE(END_REFPB); // 35
DECLARE_EXTENDED_PHASE(END_RFMPB); // 36
DECLARE_EXTENDED_PHASE(END_REFP2B); // 37
DECLARE_EXTENDED_PHASE(END_RFMP2B); // 38
DECLARE_EXTENDED_PHASE(END_PRESB); // 39
DECLARE_EXTENDED_PHASE(END_REFSB); // 40
DECLARE_EXTENDED_PHASE(END_RFMSB); // 41
DECLARE_EXTENDED_PHASE(END_PREAB); // 42
DECLARE_EXTENDED_PHASE(END_REFAB); // 43
DECLARE_EXTENDED_PHASE(END_RFMAB); // 44
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase);
bool phaseHasDataStrobe(tlm::tlm_phase phase);
bool isPowerDownEntryPhase(tlm::tlm_phase phase);
bool isPowerDownExitPhase(tlm::tlm_phase phase);
bool isFixedCommandPhase(tlm::tlm_phase phase);
bool isRefreshCommandPhase(tlm::tlm_phase phase);
class Command
{
@@ -150,11 +140,6 @@ public:
}
};
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
bool phaseNeedsEnd(tlm::tlm_phase);
bool phaseHasDataStrobe(tlm::tlm_phase);
tlm::tlm_phase getEndPhase(tlm::tlm_phase);
struct CommandTuple
{
using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_core::sc_time>;