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81eaccf3d6ae151c3d2ffe8c26b1c6357faa6727
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44 Commits

Author SHA1 Message Date
Derek Christ
81eaccf3d6 Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3 2023-08-15 10:58:10 +02:00
Derek Christ
e3bd773cac Implement isFullCycle, alignAtNext functions in utils and add tests 2023-08-15 10:58:10 +02:00
Lukas Steiner
56c9f5f5f0 Merge branch 'initialize_generalinfotable' into 'develop' 
Write GeneralInfo table at the beginning

See merge request ems/astdm/modeling.dram/dram.sys.5!39
 2023-08-14 13:33:40 +00:00
Lukas Steiner
b5fb23b55d Merge branch 'debug_file' into 'develop' 
Don't create log file when debug is not enabled

See merge request ems/astdm/modeling.dram/dram.sys.5!36
 2023-08-10 12:27:54 +00:00
Lukas Steiner
cb9689a08d Merge branch 'work/simulator_library' into 'develop' 
Introduce Simulator class

See merge request ems/astdm/modeling.dram/dram.sys.5!35
 2023-08-10 12:19:33 +00:00
Derek Christ
d392d0ab98 Write GeneralInfo table at the beginning 
and do not include information in it that is only known at the end of
the simulation. These can trivially be calculated by the trace itself
and would be redundant information regardless.

The TraceAnalyzer gets the number of transactions and the length of
the trace by additional SQL queries.

This enables us to inspect traces of simulations that were aborted
without finishing cleanlywithout finishing cleanly.
 2023-08-09 11:55:10 +02:00
Derek Christ
085bfbd8de Don't create log file when debug is not enabled 2023-07-21 09:39:52 +02:00
Derek Christ
14ecc64ed0 Introduce Simulator class 2023-07-14 14:31:03 +02:00
Lukas Steiner
12dcbfd917 Use scoped enums for DRAM types. 2023-06-30 15:49:41 +02:00
Lukas Steiner
4e0891affb Inherit privately from std::vector. 2023-06-26 16:32:39 +02:00
Lukas Steiner
413921f420 Minor formatting. 2023-06-22 10:19:34 +02:00
Lukas Steiner
c833471480 Use type safe index vectors in remaining controller. 2023-06-21 14:51:15 +02:00
Lukas Steiner
ba3f367676 Use type safe index vectors in timing checkers (2/2). 2023-06-21 12:59:26 +02:00
Lukas Steiner
d045af9d16 Use type safe index vectors in timing checkers (1). 2023-06-20 13:54:36 +02:00
Lukas Steiner
20f6aae787 Replace tabs with whitespaces. 2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02 Update TUK to RPTU. 2023-05-25 15:15:52 +02:00
Lukas Steiner
4212e55f6c Set cmake defaults, replace TUK with RPTU. 2023-05-23 16:47:03 +02:00
Derek Christ
69cd04c448 Namespace the complete DRAMSys library 2023-05-17 11:42:00 +02:00
Derek Christ
44a4d71635 Fix HBM pseudochannels not respeced in AddressDecoder 2023-04-21 11:12:21 +02:00
Derek Christ
85f944fe58 Rename RAACDR to RAADEC 2023-04-21 11:10:09 +02:00
Lukas Steiner
9a1443835d Merge branch 'develop' into wip/unit_test_preps 
# Conflicts:
#	extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
 2023-04-14 11:35:32 +02:00
Lukas Steiner
9b31fef555 Use local copies of sc_max_time() instead of calling the function. 2023-04-14 10:03:59 +02:00
Lukas Steiner
9115845862 Add common interface for BM, RM and PDM (2). 2023-04-13 16:10:59 +02:00
Derek Christ
b343ea821f Refactor Configuration and add warnings when invalid values are provided 2023-04-13 11:21:37 +02:00
Derek Christ
03152c0e61 Fix dump of mcconfig and memspec in GeneralInfo table 2023-04-13 11:21:36 +02:00
Derek Christ
a49afa40eb Use key "addressmapping" instead of "CONGEN" in addressmapping configs 2023-04-13 11:21:36 +02:00
Derek Christ
c8e509a120 Add EccModule to simulator 2023-04-13 11:21:36 +02:00
Derek Christ
d27a29ca80 Refactor configuration library 
The configuration library has been refactored to make use of nlohmann
macros to reduce boilerplate code.
The nlohmann parser callback is used to decide whether to include
configuration json objects directly, or if they need to be loaded
from a sperate file.
 2023-04-13 11:18:39 +02:00
Lukas Steiner
0d09222ab5 Implement cache into checker. 2023-04-13 11:07:55 +02:00
Lukas Steiner
65a20e9827 Remove checker from BM, RM and PDM. 2023-04-13 09:57:50 +02:00
Lukas Steiner
088621880c Rename methods to evaluate and update. 2023-04-12 16:47:26 +02:00
Lukas Steiner
af386b4852 Increment nextChannelPayloadIDToAppend only once. 2023-03-23 10:27:48 +00:00
Lukas Steiner
d18778a40a Minor refactor. 2023-03-22 10:44:48 +01:00
Lukas Steiner
04ca902cf4 Minor renaming and formatting. 2023-03-22 10:13:16 +01:00
Derek Christ
53d913c5f1 Make BlockingRead/WriteDelay configurable 2023-03-17 09:45:11 +01:00
Derek Christ
ac9351c025 Implement b_transport and add tests for it 2023-03-06 14:10:56 +01:00
Lukas Steiner
c4ca3d71d7 Reorganize config files, remove unused config. 2023-02-23 17:02:21 +01:00
Lukas Steiner
d736a2d25e Fix regression tests, add DRAMPower. 2023-02-23 10:38:59 +01:00
Lukas Steiner
e848d776cc Fix Trace Analyzer cmake. 2023-02-22 17:11:17 +01:00
Lukas Steiner
1bd6d61d23 Adapt more paths. 2023-02-22 15:18:17 +01:00
Lukas Steiner
b13cf5845c Remove unused files, make includes consistent. 2023-02-22 10:53:20 +01:00
Lukas Steiner
3bc1a6afde Remove unused files, adapt include paths. 2023-02-13 14:41:59 +01:00
Thomas Psota
f434026ccd Added extension mechanism and ported DDR5, LPDDR5, HBM3, TraceAnalyzer 2023-02-09 14:22:34 +01:00
Thomas Psota
b63c9beb50 Intensive refactor of DRAMSys project structure and CMakeFiles 2022-12-14 15:51:46 +01:00