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Make BlockingRead/WriteDelay configurable

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This commit is contained in:
Derek Christ
2023-03-17 09:44:31 +01:00
parent ac9351c025
commit 53d913c5f1
13 changed files with 43 additions and 18 deletions
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10
src/configuration/DRAMSys/config/McConfig.cpp
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@@ -60,7 +60,9 @@ void to_json(json_t &j, const McConfig &c)
{"ThinkDelayFw", c.thinkDelayFw},
{"ThinkDelayBw", c.thinkDelayBw},
{"PhyDelayFw", c.phyDelayFw},
{"PhyDelayBw", c.phyDelayBw}};
{"PhyDelayBw", c.phyDelayBw},
{"BlockingReadDelay", c.blockingReadDelay},
{"BlockingWriteDelay", c.blockingWriteDelay}};
remove_null_values(j);
}
@@ -132,6 +134,12 @@ void from_json(const json_t &j, McConfig &c)
if (j_mcconfig.contains("PhyDelayBw"))
j_mcconfig.at("PhyDelayBw").get_to(c.phyDelayBw);
if (j_mcconfig.contains("BlockingReadDelay"))
j_mcconfig.at("BlockingReadDelay").get_to(c.blockingReadDelay);
if (j_mcconfig.contains("BlockingWriteDelay"))
j_mcconfig.at("BlockingWriteDelay").get_to(c.blockingWriteDelay);
invalidateEnum(c.pagePolicy);
invalidateEnum(c.scheduler);
invalidateEnum(c.schedulerBuffer);

2
src/configuration/DRAMSys/config/McConfig.h
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@@ -171,6 +171,8 @@ struct McConfig
std::optional<unsigned int> thinkDelayBw;
std::optional<unsigned int> phyDelayFw;
std::optional<unsigned int> phyDelayBw;
std::optional<unsigned int> blockingReadDelay;
std::optional<unsigned int> blockingWriteDelay;
};
void to_json(json_t &j, const McConfig &c);

10
src/libdramsys/DRAMSys/configuration/Configuration.cpp
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@@ -274,6 +274,16 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig)
{
phyDelayBw = std::round(sc_time(*_phyDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
{
auto _blockingReadDelay = mcConfig.blockingReadDelay.value_or(60);
blockingReadDelay = std::round(sc_time(_blockingReadDelay, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
{
auto _blockingWriteDelay = mcConfig.blockingWriteDelay.value_or(60);
blockingWriteDelay = std::round(sc_time(_blockingWriteDelay, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
}
void Configuration::loadMemSpec(const DRAMSys::Config::MemSpec &memSpecConfig)

2
src/libdramsys/DRAMSys/configuration/Configuration.h
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@@ -79,6 +79,8 @@ public:
sc_core::sc_time thinkDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time phyDelayFw = sc_core::SC_ZERO_TIME;
sc_core::sc_time phyDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time blockingReadDelay = sc_core::SC_ZERO_TIME;
sc_core::sc_time blockingWriteDelay = sc_core::SC_ZERO_TIME;
// SimConfig
std::string simulationName = "default";

2
src/libdramsys/DRAMSys/controller/Controller.cpp
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@@ -80,6 +80,7 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
ControllerIF(name, config), addressDecoder(addressDecoder),
thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw),
phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw),
blockingReadDelay(config.blockingReadDelay), blockingWriteDelay(config.blockingWriteDelay),
minBytesPerBurst(config.memSpec->defaultBytesPerBurst),
maxBytesPerBurst(config.memSpec->maxBytesPerBurst)
{
@@ -416,6 +417,7 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &,
void Controller::b_transport(tlm_generic_payload &trans, sc_time &delay)
{
iSocket->b_transport(trans, delay);
delay += trans.is_write() ? blockingWriteDelay : blockingReadDelay;
}
unsigned int Controller::transport_dbg(tlm_generic_payload &trans)

2
src/libdramsys/DRAMSys/controller/Controller.h
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@@ -74,6 +74,8 @@ protected:
const sc_core::sc_time thinkDelayBw;
const sc_core::sc_time phyDelayFw;
const sc_core::sc_time phyDelayBw;
const sc_core::sc_time blockingReadDelay;
const sc_core::sc_time blockingWriteDelay;
private:
unsigned totalNumberOfPayloads = 0;

2
src/libdramsys/DRAMSys/simulation/DRAMSys.cpp
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@@ -103,7 +103,7 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name,
}
}
const Configuration& DRAMSys::getConfig()
const Configuration& DRAMSys::getConfig() const
{
return config;
}

2
src/libdramsys/DRAMSys/simulation/DRAMSys.h
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@@ -69,7 +69,7 @@ public:
DRAMSys(const sc_core::sc_module_name& name,
const ::DRAMSys::Config::Configuration& configLib);
const Configuration& getConfig();
const Configuration& getConfig() const;
protected:
DRAMSys(const sc_core::sc_module_name& name,

5
src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
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@@ -63,9 +63,6 @@ using namespace tlm;
using namespace DRAMPower;
#endif
const sc_core::sc_time Dram::BLOCKING_READ_LATENCY = sc_core::sc_time(60, sc_core::SC_NS);
const sc_core::sc_time Dram::BLOCKING_WRITE_LATENCY = sc_core::sc_time(60, sc_core::SC_NS);
Dram::Dram(const sc_module_name& name, const Configuration& config)
: sc_module(name), memSpec(*config.memSpec), tSocket("socket"), storeMode(config.storeMode),
powerAnalysis(config.powerAnalysis), useMalloc(config.useMalloc)
@@ -212,8 +209,6 @@ void Dram::b_transport(tlm_generic_payload &trans, sc_time &delay)
printedWarning = true;
}
delay += trans.is_write() ? BLOCKING_WRITE_LATENCY : BLOCKING_READ_LATENCY;
if (storeMode == Configuration::StoreMode::Store)
{
tlm_command cmd = trans.get_command();

2
src/libdramsys/DRAMSys/simulation/dram/Dram.h
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@@ -75,8 +75,6 @@ protected:
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
public:
static const sc_core::sc_time BLOCKING_READ_LATENCY;
static const sc_core::sc_time BLOCKING_WRITE_LATENCY;
static constexpr std::string_view BLOCKING_WARNING =
"Use the blocking mode of DRAMSys with caution! "
"The simulated timings do not reflect the real system!";

18
tests/tests_dramsys/b_transport/b_transport.cpp
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@@ -74,11 +74,15 @@ struct BlockingInitiator : sc_core::sc_module
{
tlm_utils::simple_initiator_socket<BlockingInitiator> iSocket;
static constexpr std::array<uint64_t, 8> TEST_DATA = {0xDEADBEEF};
SC_CTOR(BlockingInitiator)
DRAMSys::DRAMSys const &dramSys;
BlockingInitiator(sc_core::sc_module_name const &name, DRAMSys::DRAMSys const &dramSys)
: sc_core::sc_module(name), dramSys(dramSys)
{
SC_THREAD(readAccess);
SC_THREAD(writeAccess);
}
SC_HAS_PROCESS(BlockingInitiator);
void readAccess()
{
@@ -87,7 +91,7 @@ struct BlockingInitiator : sc_core::sc_module
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
iSocket->b_transport(payload, delay);
EXPECT_EQ(delay, Dram::BLOCKING_READ_LATENCY);
EXPECT_EQ(delay, dramSys.getConfig().blockingReadDelay);
}
void writeAccess()
@@ -100,13 +104,13 @@ struct BlockingInitiator : sc_core::sc_module
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
iSocket->b_transport(payload, delay);
EXPECT_EQ(delay, Dram::BLOCKING_WRITE_LATENCY);
EXPECT_EQ(delay, dramSys.getConfig().blockingWriteDelay);
}
};
TEST_F(BTransportNoStorage, RWDelay)
{
BlockingInitiator initiator("initiator");
BlockingInitiator initiator("initiator", dramSysNoStorage);
initiator.iSocket.bind(dramSysNoStorage.tSocket);
sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_US));
@@ -114,7 +118,7 @@ TEST_F(BTransportNoStorage, RWDelay)
TEST_F(BTransportStorage, RWDelay)
{
BlockingInitiator initiator("initiator");
BlockingInitiator initiator("initiator", dramSysStorage);
initiator.iSocket.bind(dramSysStorage.tSocket);
sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_US));
@@ -122,7 +126,7 @@ TEST_F(BTransportStorage, RWDelay)
TEST_F(BTransportStorage, DataWritten)
{
BlockingInitiator initiator("initiator");
BlockingInitiator initiator("initiator", dramSysStorage);
initiator.iSocket.bind(dramSysStorage.tSocket);
sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_US));
@@ -140,7 +144,7 @@ TEST_F(BTransportStorage, DataWritten)
TEST_F(BTransportNoStorage, Warning)
{
BlockingInitiator initiator("initiator");
BlockingInitiator initiator("initiator", dramSysNoStorage);
initiator.iSocket.bind(dramSysNoStorage.tSocket);
// Redirect stdout to buffer

4
tests/tests_dramsys/b_transport/configs/no_storage.json
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@@ -59,7 +59,9 @@
"RequestBufferSize": 8,
"RespQueue": "Fifo",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise"
"SchedulerBuffer": "Bankwise",
"BlockingReadDelay": 80,
"BlockingWriteDelay": 100
},
"memspec": {
"memarchitecturespec": {

0
tests/tests_dramsys/example.txt
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