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Remove unused files, adapt include paths.

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This commit is contained in:
Lukas Steiner
2023-02-13 14:41:59 +01:00
parent f434026ccd
commit 3bc1a6afde
172 changed files with 826 additions and 5434 deletions
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6
CMakeLists.txt
View File

@@ -69,7 +69,7 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
endif()
### DRAMPower directories ###
### DRAMSys directories ###
set(DRAMSYS_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/src")
set(DRAMSYS_LIBRARY_DIR "${CMAKE_CURRENT_SOURCE_DIR}/lib")
set(DRAMSYS_TESTS_DIR "${CMAKE_CURRENT_SOURCE_DIR}/tests")
@@ -79,14 +79,14 @@ set(DRAMSYS_EXTENSIONS_DIR "${CMAKE_CURRENT_SOURCE_DIR}/extensions")
### Build options ###
option(DRAMSYS_BUILD_TESTS "Build DRAMSys unit tests" OFF)
option(DRAMSYS_VERBOSE_CMAKE_OUTPUT "Show detailed CMake output" OFF)
option(DRAMSYS_BUILD_CLI "Build DRAMSys Command Line Tool" OFF)
option(DRAMSYS_BUILD_CLI "Build DRAMSys Command Line Tool" ON)
option(DRAMSYS_COVERAGE_CHECK "Coverage check of DRAMSys" OFF)
option(DRAMSYS_WITH_GEM5 "Build DRAMSys with gem5 coupling" OFF)
option(DRAMSYS_WITH_DRAMPOWER "Build with DRAMPower support enabled." OFF)
option(DRAMSYS_ENABLE_EXTENSIONS "Enable proprietary DRAMSys extensions." OFF)
### Compiler settings ###
set(CMAKE_CXX_STANDARD 23)
set(CMAKE_CXX_STANDARD 17)
if(DRAMSYS_COVERAGE_CHECK)
message("== Coverage check enabled")

2
src/configuration/DRAMSys/config/AddressMapping.h
View File

@@ -36,7 +36,7 @@
#ifndef DRAMSYSCONFIGURATION_ADDRESSMAPPING_H
#define DRAMSYSCONFIGURATION_ADDRESSMAPPING_H
#include <DRAMSys/config/ConfigUtil.h>
#include "DRAMSys/config/ConfigUtil.h"
#include <optional>

6
src/configuration/DRAMSys/config/ConfigUtil.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,9 +33,9 @@
* Derek Christ
*/
#include "DRAMSys/config/ConfigUtil.h"
#include "ConfigUtil.h"
#include "DRAMSysConfiguration.h"
#include "DRAMSys/config/DRAMSysConfiguration.h"
#include <fstream>
#include <iostream>

3
src/configuration/DRAMSys/config/ConfigUtil.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,7 +41,6 @@
#include <optional>
#include <utility>
namespace DRAMSys::Config
{
//using json_t = nlohmann::json;

2
src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp
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@@ -37,10 +37,8 @@
#include "DRAMSys/config/ConfigUtil.h"
#include <exception>
#include <fstream>
namespace DRAMSys::Config
{

2
src/configuration/DRAMSys/config/DRAMSysConfiguration.h
View File

@@ -42,7 +42,6 @@
#include "DRAMSys/config/ThermalConfig.h"
#include "DRAMSys/config/TraceSetup.h"
#include "DRAMSys/config/memspec/MemSpec.h"
#include "DRAMSys/config/ConfigUtil.h"
#include <optional>
@@ -67,7 +66,6 @@ struct Configuration
MemSpec memSpec;
SimConfig simConfig;
std::string simulationId;
std::optional<ThermalConfig> thermalConfig;
std::optional<TraceSetup> traceSetup;
static std::string resourceDirectory;

7
src/configuration/DRAMSys/config/memspec/MemSpec.h
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@@ -37,10 +37,9 @@
#define DRAMSYSCONFIGURATION_MEMSPEC_H
#include "DRAMSys/config/ConfigUtil.h"
#include "MemArchitectureSpec.h"
#include "MemPowerSpec.h"
#include "MemTimingSpec.h"
#include "DRAMSys/config/memspec/MemArchitectureSpec.h"
#include "DRAMSys/config/memspec/MemPowerSpec.h"
#include "DRAMSys/config/memspec/MemTimingSpec.h"
#include <optional>

266
src/libdramsys/CMakeLists - Copy.txt
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@@ -1,266 +0,0 @@
# Copyright (c) 2020, Technische Universität Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
# Lukas Steiner
# Derek Christ
cmake_minimum_required(VERSION 3.10)
# Project Name
project(DRAMSysLibrary)
# Configuration:
#set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version")
#set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
# Add DRAMPower:
if (DRAMSYS_WITH_DRAMPOWER)
add_subdirectory(src/common/third_party/DRAMPower)
endif()
# Add Configuration
add_subdirectory(src/common/configuration)
# Add SystemC:
if(DEFINED ENV{SYSTEMC_HOME})
find_library(SYSTEMC_LIBRARY
NAMES systemc SnpsVP
PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/lib64 $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/
)
message("== Building with external SystemC located in $ENV{SYSTEMC_HOME}")
else()
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
add_subdirectory(src/common/third_party/systemc)
set(SYSTEMC_LIBRARY systemc)
message("== Building with SystemC submodule")
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation)
message("== Database recording included")
# Add sqlite3 Dependency:
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
set(BUILD_ENABLE_RTREE ON)
add_subdirectory(src/common/third_party/sqlite-amalgamation)
set(RECORDING_SOURCES
src/common/TlmRecorder.cpp
src/controller/ControllerRecordable.cpp
src/simulation/DRAMSysRecordable.cpp
src/simulation/dram/DramRecordable.cpp
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerDDR5.cpp)
message("== DDR5 included")
set(DDR5_SOURCES
src/configuration/memspec/MemSpecDDR5.cpp
src/controller/checker/CheckerDDR5.cpp
src/simulation/dram/DramDDR5.cpp
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerLPDDR5.cpp)
message("== LPDDR5 included")
set(LPDDR5_SOURCES
src/configuration/memspec/MemSpecLPDDR5.cpp
src/controller/checker/CheckerLPDDR5.cpp
src/simulation/dram/DramLPDDR5.cpp
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerHBM3.cpp)
message("== HBM3 included")
set(HBM3_SOURCES
src/configuration/memspec/MemSpecHBM3.cpp
src/controller/checker/CheckerHBM3.cpp
src/simulation/dram/DramHBM3.cpp
)
endif()
add_library(DRAMSysLibrary
src/common/DebugManager.cpp
src/common/dramExtensions.cpp
src/common/tlm2_base_protocol_checker.h
src/common/utils.cpp
src/configuration/Configuration.cpp
src/configuration/TemperatureSimConfig.h
src/configuration/memspec/MemSpec.cpp
src/configuration/memspec/MemSpecDDR3.cpp
src/configuration/memspec/MemSpecDDR4.cpp
src/configuration/memspec/MemSpecLPDDR4.cpp
src/configuration/memspec/MemSpecWideIO.cpp
src/configuration/memspec/MemSpecWideIO2.cpp
src/configuration/memspec/MemSpecGDDR5.cpp
src/configuration/memspec/MemSpecGDDR5X.cpp
src/configuration/memspec/MemSpecGDDR6.cpp
src/configuration/memspec/MemSpecHBM2.cpp
src/configuration/memspec/MemSpecSTTMRAM.cpp
src/controller/BankMachine.cpp
src/controller/Command.cpp
src/controller/ControllerIF.h
src/controller/Controller.cpp
src/controller/checker/CheckerIF.h
src/controller/checker/CheckerDDR3.cpp
src/controller/checker/CheckerDDR4.cpp
src/controller/checker/CheckerLPDDR4.cpp
src/controller/checker/CheckerWideIO.cpp
src/controller/checker/CheckerWideIO2.cpp
src/controller/checker/CheckerGDDR5.cpp
src/controller/checker/CheckerGDDR5X.cpp
src/controller/checker/CheckerGDDR6.cpp
src/controller/checker/CheckerHBM2.cpp
src/controller/checker/CheckerSTTMRAM.cpp
src/controller/cmdmux/CmdMuxIF.h
src/controller/cmdmux/CmdMuxOldest.cpp
src/controller/cmdmux/CmdMuxStrict.cpp
src/controller/powerdown/PowerDownManagerIF.h
src/controller/powerdown/PowerDownManagerDummy.cpp
src/controller/powerdown/PowerDownManagerStaggered.cpp
src/controller/refresh/RefreshManagerIF.h
src/controller/refresh/RefreshManagerDummy.cpp
src/controller/refresh/RefreshManagerAllBank.cpp
src/controller/refresh/RefreshManagerPerBank.cpp
src/controller/refresh/RefreshManagerPer2Bank.cpp
src/controller/refresh/RefreshManagerSameBank.cpp
src/controller/respqueue/RespQueueIF.h
src/controller/respqueue/RespQueueFifo.cpp
src/controller/respqueue/RespQueueReorder.cpp
src/controller/scheduler/SchedulerIF.h
src/controller/scheduler/SchedulerFifo.cpp
src/controller/scheduler/SchedulerFrFcfs.cpp
src/controller/scheduler/SchedulerFrFcfsGrp.cpp
src/controller/scheduler/SchedulerGrpFrFcfs.cpp
src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp
src/controller/scheduler/BufferCounterIF.h
src/controller/scheduler/BufferCounterBankwise.cpp
src/controller/scheduler/BufferCounterReadWrite.cpp
src/controller/scheduler/BufferCounterShared.cpp
src/error/eccbaseclass.cpp
src/error/ecchamming.cpp
src/error/errormodel.cpp
src/error/ECC/Bit.cpp
src/error/ECC/ECC.cpp
src/error/ECC/Word.cpp
src/simulation/Arbiter.cpp
src/simulation/AddressDecoder.cpp
src/simulation/DRAMSys.cpp
src/simulation/ReorderBuffer.h
src/simulation/TemperatureController.cpp
src/simulation/dram/Dram.cpp
src/simulation/dram/DramDDR3.cpp
src/simulation/dram/DramDDR4.cpp
src/simulation/dram/DramLPDDR4.cpp
src/simulation/dram/DramWideIO.cpp
src/simulation/dram/DramWideIO2.cpp
src/simulation/dram/DramGDDR5.cpp
src/simulation/dram/DramGDDR5X.cpp
src/simulation/dram/DramGDDR6.cpp
src/simulation/dram/DramHBM2.cpp
src/simulation/dram/DramSTTMRAM.cpp
${RECORDING_SOURCES}
${DDR5_SOURCES}
${LPDDR5_SOURCES}
${HBM3_SOURCES}
)
if(DEFINED DDR5_SOURCES)
target_compile_definitions(DRAMSysLibrary PRIVATE DDR5_SIM)
endif()
if(DEFINED LPDDR5_SOURCES)
target_compile_definitions(DRAMSysLibrary PRIVATE LPDDR5_SIM)
endif()
if(DEFINED HBM3_SOURCES)
target_compile_definitions(DRAMSysLibrary PRIVATE HBM3_SIM)
endif()
if(DEFINED ENV{LIBTHREED_ICE_HOME})
message("== Thermal simulation available")
target_compile_definitions(DRAMSysLibrary PRIVATE THERMALSIM)
target_include_directories(DRAMSysLibrary
PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/
)
find_library(3DICE_LIBRARY NAMES threed-ice-2.2.4 PATHS $ENV{LIBTHREED_ICE_HOME}/lib/)
target_link_libraries(DRAMSysLibrary
PRIVATE ${3DICE_LIBRARY}
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation)
target_include_directories(DRAMSysLibrary
PUBLIC src/common/third_party/sqlite-amalgamation/
)
target_link_libraries(DRAMSysLibrary
PRIVATE sqlite3::sqlite3
)
endif()
# Build:
target_include_directories(DRAMSysLibrary
PRIVATE src/common/third_party/DRAMPower/src/
PUBLIC $ENV{SYSTEMC_HOME}/include/
)
if(EXISTS $ENV{SYSTEMC_HOME}/include/tlm/)
target_include_directories(DRAMSysLibrary
PUBLIC $ENV{SYSTEMC_HOME}/include/tlm/
)
endif()
target_link_libraries(DRAMSysLibrary
PUBLIC ${SYSTEMC_LIBRARY}
PUBLIC DRAMSysConfiguration
)
if (DRAMSYS_WITH_DRAMPOWER)
target_compile_definitions(DRAMSysLibrary PRIVATE DRAMPOWER)
target_link_libraries(DRAMSysLibrary
PRIVATE DRAMPower
)
endif()

6
src/libdramsys/CMakeLists.txt
View File

@@ -38,10 +38,8 @@
project(DRAMSys_libdramsys)
#file(GLOB_RECURSE SOURCE_FILES CONFIGURE_DEPENDS *.cpp)
#file(GLOB_RECURSE HEADER_FILES CONFIGURE_DEPENDS *.h;*.hpp)
include(sources.lst)
file(GLOB_RECURSE SOURCE_FILES CONFIGURE_DEPENDS *.cpp)
file(GLOB_RECURSE HEADER_FILES CONFIGURE_DEPENDS *.h;*.hpp)
add_library(${PROJECT_NAME} STATIC ${SOURCE_FILES} ${HEADER_FILES})

5
src/libdramsys/DRAMSys/common/TlmRecorder.cpp
View File

@@ -40,9 +40,8 @@
*/
#include "TlmRecorder.h"
#include "../configuration/Configuration.h"
#include "../controller/Command.h"
#include "DebugManager.h"
#include "DRAMSys/common/DebugManager.h"
#include <fstream>
#include <sqlite3.h>

8
src/libdramsys/DRAMSys/common/TlmRecorder.h
View File

@@ -41,6 +41,10 @@
#ifndef TLMRECORDER_H
#define TLMRECORDER_H
#include "DRAMSys/configuration/Configuration.h"
#include "DRAMSys/common/dramExtensions.h"
#include "DRAMSys/common/utils.h"
#include <string>
#include <systemc>
#include <thread>
@@ -49,10 +53,6 @@
#include <utility>
#include <vector>
#include "../configuration/Configuration.h"
#include "dramExtensions.h"
#include "utils.h"
class sqlite3;
class sqlite3_stmt;

5
src/libdramsys/DRAMSys/common/utils.cpp
View File

@@ -37,11 +37,10 @@
* Derek Christ
*/
#include <sstream>
#include <fstream>
#include "utils.h"
#include <sstream>
using namespace sc_core;
using namespace tlm;

4
src/libdramsys/DRAMSys/common/utils.h
View File

@@ -40,11 +40,11 @@
#ifndef UTILS_H
#define UTILS_H
#include <string>
#include "DRAMSys/common/dramExtensions.h"
#include <systemc>
#include <tlm>
#include "dramExtensions.h"
#include <string>
class TimeInterval
{

91
src/libdramsys/DRAMSys/configuration/Configuration.cpp
View File

@@ -40,25 +40,26 @@
*/
#include "Configuration.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
#include "memspec/MemSpecGDDR5X.h"
#include "memspec/MemSpecGDDR6.h"
#include "memspec/MemSpecSTTMRAM.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR3.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR4.h"
#include "DRAMSys/configuration/memspec/MemSpecWideIO.h"
#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h"
#include "DRAMSys/configuration/memspec/MemSpecWideIO2.h"
#include "DRAMSys/configuration/memspec/MemSpecHBM2.h"
#include "DRAMSys/configuration/memspec/MemSpecGDDR5.h"
#include "DRAMSys/configuration/memspec/MemSpecGDDR5X.h"
#include "DRAMSys/configuration/memspec/MemSpecGDDR6.h"
#include "DRAMSys/configuration/memspec/MemSpecSTTMRAM.h"
#ifdef DDR5_SIM
#include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
#include "DRAMSys/configuration/memspec/MemSpecDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include <DRAMSys/configuration/memspec/MemSpecLPDDR5.h>
#include "DRAMSys/configuration/memspec/MemSpecLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "memspec/MemSpecHBM3.h"
#include "DRAMSys/configuration/memspec/MemSpecHBM3.h"
#endif
using namespace sc_core;
@@ -102,7 +103,13 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)
enableWindowing = *_enableWindowing;
if (const auto& _powerAnalysis = simConfig.powerAnalysis)
{
powerAnalysis = *_powerAnalysis;
#ifndef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("Configuration", "Power analysis is only supported with included DRAMPower library!");
#endif
}
if (const auto& _simulationName = simConfig.simulationName)
simulationName = *_simulationName;
@@ -110,9 +117,6 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)
if (const auto& _simulationProgressBar = simConfig.simulationProgressBar)
simulationProgressBar = *_simulationProgressBar;
if (const auto& _thermalSimulation = simConfig.thermalSimulation)
thermalSimulation = *_thermalSimulation;
if (const auto& _useMalloc = simConfig.useMalloc)
useMalloc = *_useMalloc;
@@ -122,68 +126,15 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)
if (windowSize == 0)
SC_REPORT_FATAL("Configuration", "Minimum window size is 1");
if (const auto& _errorCsvFile = simConfig.errorCsvFile)
errorCSVFile = *_errorCsvFile;
if (const auto& _errorChipSeed = simConfig.errorChipSeed)
errorChipSeed = *_errorChipSeed;
if (const auto& _storeMode = simConfig.storeMode)
storeMode = [=] {
if (_storeMode == DRAMSys::Config::StoreMode::NoStorage)
return StoreMode::NoStorage;
else if (_storeMode == DRAMSys::Config::StoreMode::Store)
else // (_storeMode == DRAMSys::Config::StoreMode::Store)
return StoreMode::Store;
else
return StoreMode::ErrorModel;
}();
}
void Configuration::loadTemperatureSimConfig(const DRAMSys::Config::ThermalConfig &thermalConfig)
{
temperatureSim.temperatureScale = [=] {
if (thermalConfig.temperatureScale == DRAMSys::Config::TemperatureScale::Celsius)
return TemperatureSimConfig::TemperatureScale::Celsius;
else if (thermalConfig.temperatureScale == DRAMSys::Config::TemperatureScale::Fahrenheit)
return TemperatureSimConfig::TemperatureScale::Fahrenheit;
else
return TemperatureSimConfig::TemperatureScale::Kelvin;
}();
temperatureSim.staticTemperatureDefaultValue = thermalConfig.staticTemperatureDefaultValue;
temperatureSim.thermalSimPeriod = thermalConfig.thermalSimPeriod;
temperatureSim.thermalSimUnit = [=] {
if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Seconds)
return sc_core::SC_SEC;
else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Milliseconds)
return sc_core::SC_MS;
else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Microseconds)
return sc_core::SC_US;
else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Nanoseconds)
return sc_core::SC_NS;
else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Picoseconds)
return sc_core::SC_PS;
else
return sc_core::SC_FS;
}();
for (const auto &channel : thermalConfig.powerInfo.channels)
{
temperatureSim.powerInitialValues.push_back(channel.init_pow);
temperatureSim.powerThresholds.push_back(channel.threshold);
}
temperatureSim.iceServerIp = thermalConfig.iceServerIp;
temperatureSim.iceServerPort = thermalConfig.iceServerPort;
temperatureSim.simPeriodAdjustFactor = thermalConfig.simPeriodAdjustFactor;
temperatureSim.nPowStableCyclesToIncreasePeriod = thermalConfig.nPowStableCyclesToIncreasePeriod;
temperatureSim.generateTemperatureMap = thermalConfig.generateTemperatureMap;
temperatureSim.generatePowerMap = thermalConfig.generatePowerMap;
temperatureSim.showTemperatureSimConfig();
}
void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig)
{
if (const auto& _pagePolicy = mcConfig.pagePolicy)

18
src/libdramsys/DRAMSys/configuration/Configuration.h
View File

@@ -43,13 +43,10 @@
#ifndef CONFIGURATION_H
#define CONFIGURATION_H
#include <DRAMSYS/config/DRAMSysConfiguration.h>
#include "memspec/MemSpec.h"
#include "TemperatureSimConfig.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/config/DRAMSysConfiguration.h"
#include <systemc>
#include <string>
class Configuration
@@ -74,7 +71,6 @@ public:
unsigned int refreshMaxPostponed = 0;
unsigned int refreshMaxPulledin = 0;
enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy = PowerDownPolicy::NoPowerDown;
unsigned int powerDownTimeout = 3;
unsigned int maxActiveTransactions = 64;
bool refreshManagement = false;
sc_core::sc_time arbitrationDelayFw = sc_core::SC_ZERO_TIME;
@@ -91,27 +87,19 @@ public:
bool enableWindowing = false;
unsigned int windowSize = 1000;
bool debug = false;
bool thermalSimulation = false;
bool simulationProgressBar = false;
bool checkTLM2Protocol = false;
bool useMalloc = false;
unsigned long long int addressOffset = 0;
//Configs for Seed, csv file and StorageMode
unsigned int errorChipSeed = 0;
std::string errorCSVFile = "not defined.";
enum class StoreMode {NoStorage, Store, ErrorModel} storeMode = StoreMode::NoStorage;
enum class StoreMode {NoStorage, Store} storeMode = StoreMode::NoStorage;
// MemSpec (from DRAM-Power)
std::unique_ptr<const MemSpec> memSpec;
// Temperature Simulation related
TemperatureSimConfig temperatureSim;
void loadMCConfig(const DRAMSys::Config::McConfig& mcConfig);
void loadSimConfig(const DRAMSys::Config::SimConfig& simConfig);
void loadMemSpec(const DRAMSys::Config::MemSpec& memSpec);
void loadTemperatureSimConfig(const DRAMSys::Config::ThermalConfig& thermalConfig);
};
#endif // CONFIGURATION_H

89
src/libdramsys/DRAMSys/configuration/TemperatureSimConfig.h
View File

@@ -1,89 +0,0 @@
/*
* Copyright (c) 2015, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Eder F. Zulian
* Matthias Jung
* Luiza Correa
* Derek Christ
*/
#ifndef TEMPERATURESIMCONFIG_H
#define TEMPERATURESIMCONFIG_H
#include <string>
#include <vector>
#include <DRAMSYS/config/DRAMSysConfiguration.h>
#include <systemc>
#include <utility>
#include "../common/DebugManager.h"
struct TemperatureSimConfig
{
// Temperature Scale
enum class TemperatureScale {Celsius, Fahrenheit, Kelvin} temperatureScale;
// Static Temperature Simulation parameters
int staticTemperatureDefaultValue;
// Thermal Simulation parameters
double thermalSimPeriod;
enum sc_core::sc_time_unit thermalSimUnit;
std::string iceServerIp;
unsigned int iceServerPort;
unsigned int simPeriodAdjustFactor;
unsigned int nPowStableCyclesToIncreasePeriod;
bool generateTemperatureMap;
bool generatePowerMap;
// Power related information
std::vector<float> powerInitialValues;
std::vector<float> powerThresholds;
void showTemperatureSimConfig()
{
NDEBUG_UNUSED(int i) = 0;
for (NDEBUG_UNUSED(auto e) : powerInitialValues)
{
PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerInitialValues["
+ std::to_string(i++) + "]: " + std::to_string(e));
}
i = 0;
for (NDEBUG_UNUSED(auto e) : powerThresholds)
{
PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerThreshold["
+ std::to_string(i++) + "]: " + std::to_string(e));
}
}
};
#endif // TEMPERATURESIMCONFIG_H

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
View File

@@ -39,16 +39,14 @@
#ifndef MEMSPEC_H
#define MEMSPEC_H
#include <DRAMSYS/config/DRAMSysConfiguration.h>
#include <DRAMSys/config/DRAMSysConfiguration.h>
#include <DRAMSys/common/utils.h>
#include <DRAMSys/controller/Command.h>
#include <vector>
#include <string>
#include <systemc>
#include <tlm>
#include <vector>
#include <string>
class MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecDDR3.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h
View File

@@ -37,10 +37,10 @@
#ifndef MEMSPECDDR3_H
#define MEMSPECDDR3_H
#include "MemSpec.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/config/DRAMSysConfiguration.h"
#include <systemc>
#include <DRAMSYS/config/DRAMSysConfiguration.h>
class MemSpecDDR3 final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecDDR4.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECDDR4_H
#define MEMSPECDDR4_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecDDR4 final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecGDDR5.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECGDDR5_H
#define MEMSPECGDDR5_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecGDDR5 final : public MemSpec
{

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -33,11 +33,13 @@
* Lukas Steiner
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecGDDR5X.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECGDDR5X_H
#define MEMSPECGDDR5X_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecGDDR5X final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecGDDR6.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECGDDR6_H
#define MEMSPECGDDR6_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
struct MemSpecGDDR6 final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecHBM2.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECHBM2_H
#define MEMSPECHBM2_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecHBM2 final : public MemSpec
{

195
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
View File

@@ -1,195 +0,0 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecHBM3.h"
using namespace sc_core;
using namespace tlm;
MemSpecHBM3::MemSpecHBM3(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::HBM3,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")),
RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tPL (tCK * memSpec.memTimingSpec.entries.at("PL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCKE + tCK),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD"))
{
commandLengthInCycles[Command::ACT] = 1.5;
commandLengthInCycles[Command::PREPB] = 0.5;
commandLengthInCycles[Command::PREAB] = 0.5;
commandLengthInCycles[Command::REFPB] = 0.5;
commandLengthInCycles[Command::REFAB] = 0.5;
commandLengthInCycles[Command::RFMPB] = 0.5;
commandLengthInCycles[Command::RFMAB] = 0.5;
commandLengthInCycles[Command::PDXA] = 0.5;
commandLengthInCycles[Command::SREFEX] = 0.5;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "HBM3" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl;
std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl;
std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl;
std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
}
sc_time MemSpecHBM3::getRefreshIntervalAB() const
{
return tREFI;
}
sc_time MemSpecHBM3::getRefreshIntervalPB() const
{
return tREFIPB;
}
bool MemSpecHBM3::hasRasAndCasBus() const
{
return true;
}
sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload &payload) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD + tCK;
else
return tRCDWR + tCK;
}
else if (command == Command::RD)
return tRL + tDQSCK + burstDuration;
else if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR)
return tWL + burstDuration;
else if (command == Command::WRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB || command == Command::RFMAB)
return tRFC;
else if (command == Command::REFPB || command == Command::RFMPB)
return tRFCPB;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
}
TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecHBM3", "Method was called with invalid argument");
return {};
}
}
unsigned MemSpecHBM3::getRAACDR() const
{
return RAACDR;
}
unsigned MemSpecHBM3::getRAAIMT() const
{
return RAAIMT;
}
unsigned MemSpecHBM3::getRAAMMT() const
{
return RAAMMT;
}

102
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.h
View File

@@ -1,102 +0,0 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
* Derek Christ
*/
#ifndef MemSpecHBM3_H
#define MemSpecHBM3_H
#include <systemc>
#include "MemSpec.h"
class MemSpecHBM3 final : public MemSpec
{
public:
explicit MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec);
const unsigned RAAIMT;
const unsigned RAAMMT;
const unsigned RAACDR;
// Memspec Variables:
const sc_core::sc_time tDQSCK;
// sc_time tDQSQ; // TODO: check actual value of this parameter
const sc_core::sc_time tRC;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRCDRD;
const sc_core::sc_time tRCDWR;
const sc_core::sc_time tRRDL;
const sc_core::sc_time tRRDS;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRP;
const sc_core::sc_time tRL;
const sc_core::sc_time tWL;
const sc_core::sc_time tPL;
const sc_core::sc_time tWR;
const sc_core::sc_time tCCDL;
const sc_core::sc_time tCCDS;
// sc_time tCCDR; // TODO: consecutive reads to different stack IDs
const sc_core::sc_time tWTRL;
const sc_core::sc_time tWTRS;
const sc_core::sc_time tRTW;
const sc_core::sc_time tXP;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD; // = tCKE;
const sc_core::sc_time tCKESR; // = tCKE + tCK;
const sc_core::sc_time tXS;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRFCPB;
const sc_core::sc_time tRREFD;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIPB;
const sc_core::sc_time tPPD;
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
unsigned getRAACDR() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
bool hasRasAndCasBus() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MemSpecHBM3_H

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecLPDDR4.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECLPDDR4_H
#define MEMSPECLPDDR4_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecLPDDR4 final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecSTTMRAM.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECSTTMRAM_H
#define MEMSPECSTTMRAM_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecSTTMRAM final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecWideIO.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECWIDEIO_H
#define MEMSPECWIDEIO_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecWideIO final : public MemSpec
{

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -34,11 +34,12 @@
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecWideIO2.h"
#include "DRAMSys/common/utils.h"
#include <iostream>
using namespace sc_core;
using namespace tlm;

3
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h
View File

@@ -37,8 +37,9 @@
#ifndef MEMSPECWIDEIO2_H
#define MEMSPECWIDEIO2_H
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <systemc>
#include "MemSpec.h"
class MemSpecWideIO2 final : public MemSpec
{

7
src/libdramsys/DRAMSys/controller/BankMachine.cpp
View File

@@ -32,10 +32,11 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "BankMachine.h"
#include <DRAMSys/configuration/Configuration.h>
#include "DRAMSys/configuration/Configuration.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

34
src/libdramsys/DRAMSys/controller/BankMachine.h
View File

@@ -35,18 +35,16 @@
#ifndef BANKMACHINE_H
#define BANKMACHINE_H
#include "DRAMSys/controller/scheduler/SchedulerIF.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/controller/Command.h"
#include "DRAMSys/common/dramExtensions.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/configuration/Configuration.h"
#include <systemc>
#include <tlm>
#include <DRAMSys/common/dramExtensions.h>
#include <DRAMSys/configuration/memspec/MemSpec.h>
#include <DRAMSys/configuration/Configuration.h>
#include "scheduler/SchedulerIF.h"
#include "checker/CheckerIF.h"
#include "Command.h"
class BankMachine
{
public:
@@ -56,20 +54,20 @@ public:
void updateState(Command);
void block();
Rank getRank() const;
BankGroup getBankGroup() const;
Bank getBank() const;
Row getOpenRow() const;
bool isIdle() const;
bool isActivated() const;
bool isPrecharged() const;
uint64_t getRefreshManagementCounter() const;
[[nodiscard]] Rank getRank() const;
[[nodiscard]] BankGroup getBankGroup() const;
[[nodiscard]] Bank getBank() const;
[[nodiscard]] Row getOpenRow() const;
[[nodiscard]] bool isIdle() const;
[[nodiscard]] bool isActivated() const;
[[nodiscard]] bool isPrecharged() const;
[[nodiscard]] uint64_t getRefreshManagementCounter() const;
protected:
enum class State {Precharged, Activated} state = State::Precharged;
BankMachine(const Configuration& config, const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank);
const MemSpec& memSpec;
tlm::tlm_generic_payload *currentPayload = nullptr;
tlm::tlm_generic_payload* currentPayload = nullptr;
const SchedulerIF& scheduler;
const CheckerIF& checker;
Command nextCommand = Command::NOP;

3
src/libdramsys/DRAMSys/controller/Command.cpp
View File

@@ -36,9 +36,10 @@
* Lukas Steiner
*/
#include <array>
#include "Command.h"
#include <array>
using namespace tlm;
#ifdef DRAMPOWER

34
src/libdramsys/DRAMSys/controller/Command.h
View File

@@ -37,17 +37,16 @@
#ifndef COMMAND_H
#define COMMAND_H
#include <string>
#include <vector>
#include <tuple>
#include <systemc>
#include <tlm>
#ifdef DRAMPOWER
#include "../common/third_party/DRAMPower/src/MemCommand.h"
#endif
#include <string>
#include <vector>
#include <tuple>
#include <systemc>
#include <tlm>
// DO NOT CHANGE THE ORDER!
// BEGIN_REQ // 1
@@ -84,6 +83,7 @@ DECLARE_EXTENDED_PHASE(END_SREF); // 27
#ifdef DRAMPOWER
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
#endif
bool phaseHasDataStrobe(tlm::tlm_phase phase);
bool isPowerDownEntryPhase(tlm::tlm_phase phase);
bool isPowerDownExitPhase(tlm::tlm_phase phase);
@@ -126,18 +126,18 @@ private:
public:
Command() = default;
Command(Type type);
Command(tlm::tlm_phase phase);
explicit Command(Type type);
explicit Command(tlm::tlm_phase phase);
std::string toString() const;
tlm::tlm_phase toPhase() const;
[[nodiscard]] std::string toString() const;
[[nodiscard]] tlm::tlm_phase toPhase() const;
static unsigned numberOfCommands();
bool isBankCommand() const;
bool is2BankCommand() const;
bool isGroupCommand() const;
bool isRankCommand() const;
bool isCasCommand() const;
bool isRasCommand() const;
[[nodiscard]] bool isBankCommand() const;
[[nodiscard]] bool is2BankCommand() const;
[[nodiscard]] bool isGroupCommand() const;
[[nodiscard]] bool isRankCommand() const;
[[nodiscard]] bool isCasCommand() const;
[[nodiscard]] bool isRasCommand() const;
constexpr operator uint8_t() const
{

63
src/libdramsys/DRAMSys/controller/Controller.cpp
View File

@@ -34,44 +34,43 @@
#include "Controller.h"
#include <DRAMSys/configuration/Configuration.h>
#include "../common/dramExtensions.h"
#include "checker/CheckerDDR3.h"
#include "checker/CheckerDDR4.h"
#include "checker/CheckerWideIO.h"
#include "checker/CheckerLPDDR4.h"
#include "checker/CheckerWideIO2.h"
#include "checker/CheckerHBM2.h"
#include "checker/CheckerGDDR5.h"
#include "checker/CheckerGDDR5X.h"
#include "checker/CheckerGDDR6.h"
#include "checker/CheckerSTTMRAM.h"
#include "scheduler/SchedulerFifo.h"
#include "scheduler/SchedulerFrFcfs.h"
#include "scheduler/SchedulerFrFcfsGrp.h"
#include "scheduler/SchedulerGrpFrFcfs.h"
#include "scheduler/SchedulerGrpFrFcfsWm.h"
#include "cmdmux/CmdMuxStrict.h"
#include "cmdmux/CmdMuxOldest.h"
#include "respqueue/RespQueueFifo.h"
#include "respqueue/RespQueueReorder.h"
#include "refresh/RefreshManagerDummy.h"
#include "refresh/RefreshManagerAllBank.h"
#include "refresh/RefreshManagerPerBank.h"
#include "refresh/RefreshManagerPer2Bank.h"
#include "refresh/RefreshManagerSameBank.h"
#include "powerdown/PowerDownManagerStaggered.h"
#include "powerdown/PowerDownManagerDummy.h"
#include "DRAMSys/controller/checker/CheckerDDR3.h"
#include "DRAMSys/controller/checker/CheckerDDR4.h"
#include "DRAMSys/controller/checker/CheckerWideIO.h"
#include "DRAMSys/controller/checker/CheckerLPDDR4.h"
#include "DRAMSys/controller/checker/CheckerWideIO2.h"
#include "DRAMSys/controller/checker/CheckerHBM2.h"
#include "DRAMSys/controller/checker/CheckerGDDR5.h"
#include "DRAMSys/controller/checker/CheckerGDDR5X.h"
#include "DRAMSys/controller/checker/CheckerGDDR6.h"
#include "DRAMSys/controller/checker/CheckerSTTMRAM.h"
#include "DRAMSys/controller/scheduler/SchedulerFifo.h"
#include "DRAMSys/controller/scheduler/SchedulerFrFcfs.h"
#include "DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h"
#include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h"
#include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h"
#include "DRAMSys/controller/cmdmux/CmdMuxStrict.h"
#include "DRAMSys/controller/cmdmux/CmdMuxOldest.h"
#include "DRAMSys/controller/respqueue/RespQueueFifo.h"
#include "DRAMSys/controller/respqueue/RespQueueReorder.h"
#include "DRAMSys/controller/refresh/RefreshManagerDummy.h"
#include "DRAMSys/controller/refresh/RefreshManagerAllBank.h"
#include "DRAMSys/controller/refresh/RefreshManagerPerBank.h"
#include "DRAMSys/controller/refresh/RefreshManagerPer2Bank.h"
#include "DRAMSys/controller/refresh/RefreshManagerSameBank.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerStaggered.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerDummy.h"
#include "DRAMSys/configuration/Configuration.h"
#include "DRAMSys/common/dramExtensions.h"
#ifdef DDR5_SIM
#include <DRAMSys/controller/checker/CheckerDDR5.h>
#include "DRAMSys/controller/checker/CheckerDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include <DRAMSys/controller/checker/CheckerLPDDR5.h>
#include "DRAMSys/controller/checker/CheckerLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "checker/CheckerHBM3.h"
#include "DRAMSys/controller/checker/CheckerHBM3.h"
#endif
using namespace sc_core;

23
src/libdramsys/DRAMSys/controller/Controller.h
View File

@@ -35,21 +35,20 @@
#ifndef CONTROLLER_H
#define CONTROLLER_H
#include "DRAMSys/controller/ControllerIF.h"
#include "DRAMSys/controller/Command.h"
#include "DRAMSys/controller/BankMachine.h"
#include "DRAMSys/controller/cmdmux/CmdMuxIF.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
#include "DRAMSys/controller/respqueue/RespQueueIF.h"
#include "DRAMSys/simulation/AddressDecoder.h"
#include <vector>
#include <stack>
#include <systemc>
#include <tlm>
#include "ControllerIF.h"
#include "Command.h"
#include "BankMachine.h"
#include "cmdmux/CmdMuxIF.h"
#include "checker/CheckerIF.h"
#include "refresh/RefreshManagerIF.h"
#include "powerdown/PowerDownManagerIF.h"
#include "respqueue/RespQueueIF.h"
#include "../simulation/AddressDecoder.h"
class Controller : public ControllerIF
{
@@ -93,12 +92,12 @@ private:
struct Transaction
{
tlm::tlm_generic_payload *payload = nullptr;
tlm::tlm_generic_payload* payload = nullptr;
sc_core::sc_time time = sc_core::sc_max_time();
} transToAcquire, transToRelease;
void manageResponses();
void manageRequests(const sc_core::sc_time &delay);
void manageRequests(const sc_core::sc_time& delay);
bool isFullCycle(const sc_core::sc_time& time) const;

6
src/libdramsys/DRAMSys/controller/ControllerIF.h
View File

@@ -37,15 +37,15 @@
#ifndef CONTROLLERIF_H
#define CONTROLLERIF_H
#include <iomanip>
#include "DRAMSys/configuration/Configuration.h"
#include <iomanip>
#include <systemc>
#include <tlm>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <DRAMSys/configuration/Configuration.h>
// Utiliy class to pass around the DRAMSys, without having to propagate the template defintions
// Utility class to pass around DRAMSys, without having to propagate the template definitions
// throughout all classes
class ControllerIF : public sc_core::sc_module
{

14
src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp
View File

@@ -33,13 +33,13 @@
*/
#include "ControllerRecordable.h"
#include "../configuration/Configuration.h"
#include "scheduler/SchedulerIF.h"
#include "DRAMSys/controller/scheduler/SchedulerIF.h"
using namespace sc_core;
using namespace tlm;
ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Configuration& config,
ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config,
const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder)
: Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder),
activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing),
@@ -55,15 +55,15 @@ ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Con
}
}
tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans,
tlm_phase& phase, sc_time& delay)
{
tlmRecorder.recordPhase(trans, phase, delay);
return Controller::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &,
tlm_phase &, sc_time &)
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload&,
tlm_phase&, sc_time&)
{
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called");
return TLM_ACCEPTED;

15
src/libdramsys/DRAMSys/controller/ControllerRecordable.h
View File

@@ -35,23 +35,24 @@
#ifndef CONTROLLERRECORDABLE_H
#define CONTROLLERRECORDABLE_H
#include "DRAMSys/controller/Controller.h"
#include "DRAMSys/common/TlmRecorder.h"
#include <systemc>
#include <tlm>
#include "Controller.h"
#include "../common/TlmRecorder.h"
class ControllerRecordable final : public Controller
{
public:
ControllerRecordable(const sc_core::sc_module_name &name, const Configuration& config,
ControllerRecordable(const sc_core::sc_module_name& name, const Configuration& config,
const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder);
~ControllerRecordable() override = default;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) override;
void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override;

4
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerDDR3.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERDDR3_H
#define CHECKERDDR3_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR3.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecDDR3.h"
#include "../../configuration/Configuration.h"
class CheckerDDR3 final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerDDR4.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERDDR4_H
#define CHECKERDDR4_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR4.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecDDR4.h"
#include "../../configuration/Configuration.h"
class CheckerDDR4 final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerGDDR5.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERGDDR5_H
#define CHECKERGDDR5_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecGDDR5.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecGDDR5.h"
#include "../../configuration/Configuration.h"
class CheckerGDDR5 final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerGDDR5X.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERGDDR5X_H
#define CHECKERGDDR5X_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecGDDR5X.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecGDDR5X.h"
#include "../../configuration/Configuration.h"
class CheckerGDDR5X final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerGDDR6.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERGDDR6_H
#define CHECKERGDDR6_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecGDDR6.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecGDDR6.h"
#include "../../configuration/Configuration.h"
class CheckerGDDR6 final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerHBM2.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERHBM2_H
#define CHECKERHBM2_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecHBM2.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecHBM2.h"
#include "../../configuration/Configuration.h"
class CheckerHBM2 final : public CheckerIF
{
public:

806
src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.cpp
View File

@@ -1,806 +0,0 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerHBM3.h"
using namespace sc_core;
using namespace tlm;
CheckerHBM3::CheckerHBM3(const Configuration &config)
{
memSpec = dynamic_cast<const MemSpecHBM3 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerHBM3", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>(
Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>(
Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>(
Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnRasBus = sc_max_time();
lastCommandOnCasBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->ranksPerChannel);
tRDPDE = memSpec->tRL + memSpec->tPL + 2 * memSpec->tCK;
tRDSRE = memSpec->tRL + memSpec->tPL + 3 * memSpec->tCK;
tWRPRE = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWR;
tWRPDE = memSpec->tWL + memSpec->tPL + 3 * memSpec->tCK + memSpec->tWR;
tWRAPDE = memSpec->tWL + memSpec->tPL + 3 * memSpec->tCK + memSpec->tWR;
tWRRDS = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWTRS;
tWRRDL = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWTRL;
}
sc_time CheckerHBM3::timeToSatisfyConstraints(Command command, const tlm_generic_payload &payload) const
{
Rank rank = ControllerExtension::getRank(payload);
BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
Bank bank = ControllerExtension::getBank(payload);
sc_time lastCommandStart;
sc_time earliestTimeToStart = sc_time_stamp();
if (command == Command::PREPB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK / 2);
}
else if (command == Command::RD)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::WR)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::RDA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + 2 * memSpec->tCK +
std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL));
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::WRA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::ACT)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart =
std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart =
std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS - memSpec->tCK);
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart =
std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::REFAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PREAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK / 2);
}
else if (command == Command::REFPB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (bankwiseRefreshCounter[rank.ID()] == 0)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
}
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart =
std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::SREFEN)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart =
std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE));
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::RFMAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::RFMAB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDEA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDEP)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDXP)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDXA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::SREFEX)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else
{
SC_REPORT_FATAL("CheckerHBM3", "Unknown command!");
}
// Don't issue commands at half cycles.
if (command != Command::PREAB && command != Command::PREPB && !isFullCycle(earliestTimeToStart))
earliestTimeToStart += memSpec->tCK / 2;
return earliestTimeToStart;
}
void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload)
{
Rank rank = ControllerExtension::getRank(payload);
BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
Bank bank = ControllerExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerHBM3",
"Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommand[command] = sc_time_stamp();
if (command.isCasCommand())
lastCommandOnCasBus = sc_time_stamp();
else if (command == Command::ACT)
lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK;
else
lastCommandOnRasBus = sc_time_stamp();
if (command == Command::ACT || command == Command::REFPB)
{
if (last4Activates[rank.ID()].size() == 4)
last4Activates[rank.ID()].pop();
last4Activates[rank.ID()].push(lastCommandOnRasBus);
}
if (command == Command::REFPB)
bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
}
bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const
{
sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK;
return sc_time::from_value(aligedAtHalfCycle.value() % memSpec->tCK.value()) == SC_ZERO_TIME;
}

78
src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.h
View File

@@ -1,78 +0,0 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#ifndef CHECKERHBM3_H
#define CHECKERHBM3_H
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecHBM3.h"
#include "../../configuration/Configuration.h"
class CheckerHBM3 final : public CheckerIF
{
public:
explicit CheckerHBM3(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
bool isFullCycle(const sc_core::sc_time& time) const;
const MemSpecHBM3 *memSpec;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnRasBus;
sc_core::sc_time lastCommandOnCasBus;
// Four activate window
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<unsigned> bankwiseRefreshCounter;
sc_core::sc_time tRDPDE;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRPDE;
sc_core::sc_time tWRAPDE;
sc_core::sc_time tWRRDS;
sc_core::sc_time tWRRDL;
};
#endif // CHECKERHBM3_H

4
src/libdramsys/DRAMSys/controller/checker/CheckerIF.h
View File

@@ -35,9 +35,9 @@
#ifndef CHECKERIF_H
#define CHECKERIF_H
#include <systemc>
#include "DRAMSys/controller/Command.h"
#include "../Command.h"
#include <systemc>
class CheckerIF
{

4
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerLPDDR4.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERLPDDR4_H
#define CHECKERLPDDR4_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecLPDDR4.h"
#include "../../configuration/Configuration.h"
class CheckerLPDDR4 final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerSTTMRAM.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERSTTMRAM_H
#define CHECKERSTTMRAM_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecSTTMRAM.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecSTTMRAM.h"
#include "../../configuration/Configuration.h"
class CheckerSTTMRAM final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerWideIO.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERWIDEIO_H
#define CHECKERWIDEIO_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecWideIO.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecWideIO.h"
#include "../../configuration/Configuration.h"
class CheckerWideIO final : public CheckerIF
{
public:

4
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp
View File

@@ -32,10 +32,10 @@
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerWideIO2.h"
#include <algorithm>
using namespace sc_core;
using namespace tlm;

8
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h
View File

@@ -35,13 +35,13 @@
#ifndef CHECKERWIDEIO2_H
#define CHECKERWIDEIO2_H
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecWideIO2.h"
#include "DRAMSys/configuration/Configuration.h"
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecWideIO2.h"
#include "../../configuration/Configuration.h"
class CheckerWideIO2 final : public CheckerIF
{
public:

2
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h
View File

@@ -35,7 +35,7 @@
#ifndef CMDMUXIF_H
#define CMDMUXIF_H
#include "../Command.h"
#include "DRAMSys/controller/Command.h"
class CmdMuxIF
{

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -32,9 +32,9 @@
* Author: Lukas Steiner
*/
#include <systemc>
#include "CmdMuxOldest.h"
#include "../../common/dramExtensions.h"
#include <systemc>
using namespace sc_core;

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h
View File

@@ -35,8 +35,8 @@
#ifndef CMDMUXOLDEST_H
#define CMDMUXOLDEST_H
#include "CmdMuxIF.h"
#include "../../configuration/Configuration.h"
#include "DRAMSys/controller/cmdmux/CmdMuxIF.h"
#include "DRAMSys/configuration/Configuration.h"
class CmdMuxOldest : public CmdMuxIF
{

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -32,9 +32,9 @@
* Author: Lukas Steiner
*/
#include <systemc>
#include "CmdMuxStrict.h"
#include "../../common/dramExtensions.h"
#include <systemc>
using namespace sc_core;

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h
View File

@@ -35,8 +35,8 @@
#ifndef CMDMUXSTRICT_H
#define CMDMUXSTRICT_H
#include "CmdMuxIF.h"
#include "../../configuration/Configuration.h"
#include "DRAMSys/controller/cmdmux/CmdMuxIF.h"
#include "DRAMSys/configuration/Configuration.h"
class CmdMuxStrict : public CmdMuxIF
{

1
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp
View File

@@ -32,7 +32,6 @@
* Author: Lukas Steiner
*/
#include "../Command.h"
#include "PowerDownManagerDummy.h"
using namespace sc_core;

2
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h
View File

@@ -35,7 +35,7 @@
#ifndef POWERDOWNMANAGERDUMMY_H
#define POWERDOWNMANAGERDUMMY_H
#include "PowerDownManagerIF.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
class PowerDownManagerDummy final : public PowerDownManagerIF
{

3
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h
View File

@@ -35,8 +35,9 @@
#ifndef POWERDOWNMANAGERIF_H
#define POWERDOWNMANAGERIF_H
#include "DRAMSys/controller/Command.h"
#include <systemc>
#include "../Command.h"
class PowerDownManagerIF
{

4
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp
View File

@@ -33,8 +33,8 @@
*/
#include "PowerDownManagerStaggered.h"
#include "../BankMachine.h"
#include "../../common/utils.h"
#include "DRAMSys/controller/BankMachine.h"
using namespace sc_core;
using namespace tlm;

7
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -35,10 +35,11 @@
#ifndef POWERDOWNMANAGERSTAGGERED_H
#define POWERDOWNMANAGERSTAGGERED_H
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
#include "DRAMSys/common/dramExtensions.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include <systemc>
#include "PowerDownManagerIF.h"
#include "../../common/dramExtensions.h"
#include "../checker/CheckerIF.h"
class BankMachine;

8
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp
View File

@@ -34,11 +34,9 @@
*/
#include "RefreshManagerAllBank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../common/dramExtensions.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "DRAMSys/controller/BankMachine.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
using namespace sc_core;
using namespace tlm;

10
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h
View File

@@ -35,14 +35,14 @@
#ifndef REFRESHMANAGERALLBANK_H
#define REFRESHMANAGERALLBANK_H
#include <vector>
#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/Configuration.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include <vector>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/Configuration.h"
#include "../../configuration/memspec/MemSpec.h"
class BankMachine;
class PowerDownManagerIF;

3
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h
View File

@@ -35,8 +35,9 @@
#ifndef REFRESHMANAGERDUMMY_H
#define REFRESHMANAGERDUMMY_H
#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
#include <systemc>
#include "RefreshManagerIF.h"
class RefreshManagerDummy final : public RefreshManagerIF
{

7
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h
View File

@@ -35,11 +35,12 @@
#ifndef REFRESHMANAGERIF_H
#define REFRESHMANAGERIF_H
#include <cmath>
#include "DRAMSys/controller/Command.h"
#include "DRAMSys/configuration/Configuration.h"
#include <cmath>
#include <systemc>
#include "../Command.h"
#include "../../configuration/Configuration.h"
class RefreshManagerIF
{

8
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp
View File

@@ -33,11 +33,9 @@
*/
#include "RefreshManagerPer2Bank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
#include "DRAMSys/controller/BankMachine.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
using namespace sc_core;
using namespace tlm;

10
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h
View File

@@ -35,16 +35,16 @@
#ifndef REFRESHMANAGERPER2BANK_H
#define REFRESHMANAGERPER2BANK_H
#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/configuration/Configuration.h"
#include <vector>
#include <list>
#include <unordered_map>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../../configuration/Configuration.h"
class BankMachine;
class PowerDownManagerIF;

8
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp
View File

@@ -33,11 +33,9 @@
*/
#include "RefreshManagerPerBank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
#include "DRAMSys/controller/BankMachine.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
using namespace sc_core;
using namespace tlm;

10
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h
View File

@@ -35,16 +35,16 @@
#ifndef REFRESHMANAGERPERBANK_H
#define REFRESHMANAGERPERBANK_H
#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/configuration/Configuration.h"
#include <vector>
#include <list>
#include <unordered_map>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../../configuration/Configuration.h"
class BankMachine;
class PowerDownManagerIF;

8
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp
View File

@@ -33,11 +33,9 @@
*/
#include "RefreshManagerSameBank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
#include "DRAMSys/controller/BankMachine.h"
#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
using namespace sc_core;
using namespace tlm;

10
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h
View File

@@ -35,15 +35,15 @@
#ifndef REFRESHMANAGERSAMEBANK_H
#define REFRESHMANAGERSAMEBANK_H
#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/configuration/Configuration.h"
#include <vector>
#include <list>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../../configuration/Configuration.h"
class BankMachine;
class PowerDownManagerIF;

8
src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp
View File

@@ -37,16 +37,16 @@
using namespace sc_core;
using namespace tlm;
void RespQueueFifo::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd)
void RespQueueFifo::insertPayload(tlm_generic_payload* payload, sc_time strobeEnd)
{
buffer.push({payload, strobeEnd});
buffer.emplace(payload, strobeEnd);
}
tlm_generic_payload *RespQueueFifo::nextPayload()
tlm_generic_payload* RespQueueFifo::nextPayload()
{
if (!buffer.empty())
{
std::pair<tlm_generic_payload *, sc_time> element = buffer.front();
std::pair<tlm_generic_payload*, sc_time> element = buffer.front();
if (element.second <= sc_time_stamp())
{
buffer.pop();

12
src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h
View File

@@ -35,22 +35,22 @@
#ifndef RESPQUEUEFIFO_H
#define RESPQUEUEFIFO_H
#include "DRAMSys/controller/respqueue/RespQueueIF.h"
#include <utility>
#include <queue>
#include <systemc>
#include <tlm>
#include "RespQueueIF.h"
class RespQueueFifo final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override;
tlm::tlm_generic_payload *nextPayload() override;
sc_core::sc_time getTriggerTime() const override;
void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override;
tlm::tlm_generic_payload* nextPayload() override;
[[nodiscard]] sc_core::sc_time getTriggerTime() const override;
private:
std::queue<std::pair<tlm::tlm_generic_payload *, sc_core::sc_time>> buffer;
std::queue<std::pair<tlm::tlm_generic_payload*, sc_core::sc_time>> buffer;
};
#endif // RESPQUEUEFIFO_H

6
src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h
View File

@@ -41,9 +41,9 @@
class RespQueueIF
{
public:
virtual void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) = 0;
virtual tlm::tlm_generic_payload *nextPayload() = 0;
virtual sc_core::sc_time getTriggerTime() const = 0;
virtual void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) = 0;
virtual tlm::tlm_generic_payload* nextPayload() = 0;
[[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0;
virtual ~RespQueueIF() = default;
};

9
src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp
View File

@@ -33,23 +33,24 @@
*/
#include "RespQueueReorder.h"
#include "../../common/dramExtensions.h"
#include "DRAMSys/common/dramExtensions.h"
using namespace sc_core;
using namespace tlm;
void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd)
void RespQueueReorder::insertPayload(tlm_generic_payload* payload, sc_time strobeEnd)
{
buffer[ControllerExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd};
}
tlm_generic_payload *RespQueueReorder::nextPayload()
tlm_generic_payload* RespQueueReorder::nextPayload()
{
if (!buffer.empty())
{
if (buffer.begin()->first == nextPayloadID)
{
std::pair<tlm_generic_payload *, sc_time> element = buffer.begin()->second;
std::pair<tlm_generic_payload*, sc_time> element = buffer.begin()->second;
if (element.second <= sc_time_stamp())
{
buffer.erase(nextPayloadID++);

12
src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h
View File

@@ -35,22 +35,22 @@
#ifndef RESPQUEUEREORDER_H
#define RESPQUEUEREORDER_H
#include <map>
#include "DRAMSys/controller/respqueue/RespQueueIF.h"
#include <map>
#include <systemc>
#include <tlm>
#include "RespQueueIF.h"
class RespQueueReorder final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override;
tlm::tlm_generic_payload *nextPayload() override;
sc_core::sc_time getTriggerTime() const override;
void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override;
tlm::tlm_generic_payload* nextPayload() override;
[[nodiscard]] sc_core::sc_time getTriggerTime() const override;
private:
uint64_t nextPayloadID = 1;
std::map<uint64_t, std::pair<tlm::tlm_generic_payload *, sc_core::sc_time>> buffer;
std::map<uint64_t, std::pair<tlm::tlm_generic_payload*, sc_core::sc_time>> buffer;
};
#endif // RESPQUEUEREORDER_H

5
src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp
View File

@@ -33,7 +33,8 @@
*/
#include "BufferCounterBankwise.h"
#include "../../common/dramExtensions.h"
#include "DRAMSys/common/dramExtensions.h"
using namespace tlm;
@@ -67,7 +68,7 @@ void BufferCounterBankwise::removeRequest(const tlm_generic_payload& trans)
numWriteRequests--;
}
const std::vector<unsigned> &BufferCounterBankwise::getBufferDepth() const
const std::vector<unsigned>& BufferCounterBankwise::getBufferDepth() const
{
return numRequestsOnBank;
}

12
src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h
View File

@@ -35,21 +35,21 @@
#ifndef BUFFERCOUNTERBANKWISE_H
#define BUFFERCOUNTERBANKWISE_H
#include <vector>
#include "DRAMSys/controller/scheduler/BufferCounterIF.h"
#include <vector>
#include <tlm>
#include "BufferCounterIF.h"
class BufferCounterBankwise final : public BufferCounterIF
{
public:
BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks);
bool hasBufferSpace() const override;
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(const tlm::tlm_generic_payload& trans) override;
void removeRequest(const tlm::tlm_generic_payload& trans) override;
const std::vector<unsigned> &getBufferDepth() const override;
unsigned getNumReadRequests() const override;
unsigned getNumWriteRequests() const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
[[nodiscard]] unsigned getNumReadRequests() const override;
[[nodiscard]] unsigned getNumWriteRequests() const override;
private:
const unsigned requestBufferSize;

9
src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h
View File

@@ -36,19 +36,18 @@
#define BUFFERCOUNTERIF_H
#include <vector>
#include <tlm>
class BufferCounterIF
{
public:
virtual ~BufferCounterIF() = default;
virtual bool hasBufferSpace() const = 0;
[[nodiscard]] virtual bool hasBufferSpace() const = 0;
virtual void storeRequest(const tlm::tlm_generic_payload& trans) = 0;
virtual void removeRequest(const tlm::tlm_generic_payload& trans) = 0;
virtual const std::vector<unsigned> &getBufferDepth() const = 0;
virtual unsigned getNumReadRequests() const = 0;
virtual unsigned getNumWriteRequests() const = 0;
[[nodiscard]] virtual const std::vector<unsigned>& getBufferDepth() const = 0;
[[nodiscard]] virtual unsigned getNumReadRequests() const = 0;
[[nodiscard]] virtual unsigned getNumWriteRequests() const = 0;
};
#endif // BUFFERCOUNTERIF_H

2
src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp
View File

@@ -63,7 +63,7 @@ void BufferCounterReadWrite::removeRequest(const tlm_generic_payload& trans)
numReadWriteRequests[1]--;
}
const std::vector<unsigned> &BufferCounterReadWrite::getBufferDepth() const
const std::vector<unsigned>& BufferCounterReadWrite::getBufferDepth() const
{
return numReadWriteRequests;
}

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