From 3bc1a6afdec5868f6e98d8f8140fa059a6e0b611 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 13 Feb 2023 14:41:59 +0100 Subject: [PATCH] Remove unused files, adapt include paths. --- CMakeLists.txt | 6 +- .../DRAMSys/config/AddressMapping.h | 2 +- .../DRAMSys/config/ConfigUtil.cpp | 6 +- src/configuration/DRAMSys/config/ConfigUtil.h | 3 +- .../DRAMSys/config/DRAMSysConfiguration.cpp | 2 - .../DRAMSys/config/DRAMSysConfiguration.h | 2 - .../DRAMSys/config/memspec/MemSpec.h | 7 +- src/libdramsys/CMakeLists - Copy.txt | 266 ------ src/libdramsys/CMakeLists.txt | 6 +- src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 5 +- src/libdramsys/DRAMSys/common/TlmRecorder.h | 8 +- src/libdramsys/DRAMSys/common/utils.cpp | 5 +- src/libdramsys/DRAMSys/common/utils.h | 4 +- .../DRAMSys/configuration/Configuration.cpp | 91 +- .../DRAMSys/configuration/Configuration.h | 18 +- .../configuration/TemperatureSimConfig.h | 89 -- .../DRAMSys/configuration/memspec/MemSpec.h | 8 +- .../configuration/memspec/MemSpecDDR3.cpp | 7 +- .../configuration/memspec/MemSpecDDR3.h | 4 +- .../configuration/memspec/MemSpecDDR4.cpp | 7 +- .../configuration/memspec/MemSpecDDR4.h | 3 +- .../configuration/memspec/MemSpecGDDR5.cpp | 7 +- .../configuration/memspec/MemSpecGDDR5.h | 3 +- .../configuration/memspec/MemSpecGDDR5X.cpp | 6 +- .../configuration/memspec/MemSpecGDDR5X.h | 3 +- .../configuration/memspec/MemSpecGDDR6.cpp | 7 +- .../configuration/memspec/MemSpecGDDR6.h | 3 +- .../configuration/memspec/MemSpecHBM2.cpp | 7 +- .../configuration/memspec/MemSpecHBM2.h | 3 +- .../configuration/memspec/MemSpecHBM3.cpp | 195 ----- .../configuration/memspec/MemSpecHBM3.h | 102 --- .../configuration/memspec/MemSpecLPDDR4.cpp | 7 +- .../configuration/memspec/MemSpecLPDDR4.h | 3 +- .../configuration/memspec/MemSpecSTTMRAM.cpp | 7 +- .../configuration/memspec/MemSpecSTTMRAM.h | 3 +- .../configuration/memspec/MemSpecWideIO.cpp | 7 +- .../configuration/memspec/MemSpecWideIO.h | 3 +- .../configuration/memspec/MemSpecWideIO2.cpp | 7 +- .../configuration/memspec/MemSpecWideIO2.h | 3 +- .../DRAMSys/controller/BankMachine.cpp | 7 +- .../DRAMSys/controller/BankMachine.h | 34 +- src/libdramsys/DRAMSys/controller/Command.cpp | 3 +- src/libdramsys/DRAMSys/controller/Command.h | 34 +- .../DRAMSys/controller/Controller.cpp | 63 +- .../DRAMSys/controller/Controller.h | 23 +- .../DRAMSys/controller/ControllerIF.h | 6 +- .../controller/ControllerRecordable.cpp | 14 +- .../DRAMSys/controller/ControllerRecordable.h | 15 +- .../controller/checker/CheckerDDR3.cpp | 4 +- .../DRAMSys/controller/checker/CheckerDDR3.h | 8 +- .../controller/checker/CheckerDDR4.cpp | 4 +- .../DRAMSys/controller/checker/CheckerDDR4.h | 8 +- .../controller/checker/CheckerGDDR5.cpp | 4 +- .../DRAMSys/controller/checker/CheckerGDDR5.h | 8 +- .../controller/checker/CheckerGDDR5X.cpp | 4 +- .../controller/checker/CheckerGDDR5X.h | 8 +- .../controller/checker/CheckerGDDR6.cpp | 4 +- .../DRAMSys/controller/checker/CheckerGDDR6.h | 8 +- .../controller/checker/CheckerHBM2.cpp | 4 +- .../DRAMSys/controller/checker/CheckerHBM2.h | 8 +- .../controller/checker/CheckerHBM3.cpp | 806 ------------------ .../DRAMSys/controller/checker/CheckerHBM3.h | 78 -- .../DRAMSys/controller/checker/CheckerIF.h | 4 +- .../controller/checker/CheckerLPDDR4.cpp | 4 +- .../controller/checker/CheckerLPDDR4.h | 8 +- .../controller/checker/CheckerSTTMRAM.cpp | 4 +- .../controller/checker/CheckerSTTMRAM.h | 8 +- .../controller/checker/CheckerWideIO.cpp | 4 +- .../controller/checker/CheckerWideIO.h | 8 +- .../controller/checker/CheckerWideIO2.cpp | 4 +- .../controller/checker/CheckerWideIO2.h | 8 +- .../DRAMSys/controller/cmdmux/CmdMuxIF.h | 2 +- .../controller/cmdmux/CmdMuxOldest.cpp | 4 +- .../DRAMSys/controller/cmdmux/CmdMuxOldest.h | 4 +- .../controller/cmdmux/CmdMuxStrict.cpp | 4 +- .../DRAMSys/controller/cmdmux/CmdMuxStrict.h | 4 +- .../powerdown/PowerDownManagerDummy.cpp | 1 - .../powerdown/PowerDownManagerDummy.h | 2 +- .../controller/powerdown/PowerDownManagerIF.h | 3 +- .../powerdown/PowerDownManagerStaggered.cpp | 4 +- .../powerdown/PowerDownManagerStaggered.h | 7 +- .../refresh/RefreshManagerAllBank.cpp | 8 +- .../refresh/RefreshManagerAllBank.h | 10 +- .../controller/refresh/RefreshManagerDummy.h | 3 +- .../controller/refresh/RefreshManagerIF.h | 7 +- .../refresh/RefreshManagerPer2Bank.cpp | 8 +- .../refresh/RefreshManagerPer2Bank.h | 10 +- .../refresh/RefreshManagerPerBank.cpp | 8 +- .../refresh/RefreshManagerPerBank.h | 10 +- .../refresh/RefreshManagerSameBank.cpp | 8 +- .../refresh/RefreshManagerSameBank.h | 10 +- .../controller/respqueue/RespQueueFifo.cpp | 8 +- .../controller/respqueue/RespQueueFifo.h | 12 +- .../controller/respqueue/RespQueueIF.h | 6 +- .../controller/respqueue/RespQueueReorder.cpp | 9 +- .../controller/respqueue/RespQueueReorder.h | 12 +- .../scheduler/BufferCounterBankwise.cpp | 5 +- .../scheduler/BufferCounterBankwise.h | 12 +- .../controller/scheduler/BufferCounterIF.h | 9 +- .../scheduler/BufferCounterReadWrite.cpp | 2 +- .../scheduler/BufferCounterReadWrite.h | 12 +- .../scheduler/BufferCounterShared.cpp | 2 +- .../scheduler/BufferCounterShared.h | 12 +- .../controller/scheduler/SchedulerFifo.cpp | 14 +- .../controller/scheduler/SchedulerFifo.h | 22 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 14 +- .../controller/scheduler/SchedulerFrFcfs.h | 22 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 14 +- .../controller/scheduler/SchedulerFrFcfsGrp.h | 20 +- .../scheduler/SchedulerGrpFrFcfs.cpp | 16 +- .../controller/scheduler/SchedulerGrpFrFcfs.h | 24 +- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 20 +- .../scheduler/SchedulerGrpFrFcfsWm.h | 22 +- .../controller/scheduler/SchedulerIF.h | 14 +- src/libdramsys/DRAMSys/error/ECC/Bit.cpp | 60 -- src/libdramsys/DRAMSys/error/ECC/Bit.h | 105 --- src/libdramsys/DRAMSys/error/ECC/ECC.cpp | 161 ---- src/libdramsys/DRAMSys/error/ECC/ECC.h | 74 -- src/libdramsys/DRAMSys/error/ECC/ECC_Test.cpp | 152 ---- src/libdramsys/DRAMSys/error/ECC/Word.cpp | 180 ---- src/libdramsys/DRAMSys/error/ECC/Word.h | 98 --- src/libdramsys/DRAMSys/error/eccbaseclass.cpp | 120 --- src/libdramsys/DRAMSys/error/eccbaseclass.h | 102 --- src/libdramsys/DRAMSys/error/ecchamming.cpp | 166 ---- src/libdramsys/DRAMSys/error/ecchamming.h | 82 -- src/libdramsys/DRAMSys/error/errormodel.cpp | 753 ---------------- src/libdramsys/DRAMSys/error/errormodel.h | 147 ---- .../DRAMSys/simulation/AddressDecoder.cpp | 30 +- .../DRAMSys/simulation/AddressDecoder.h | 12 +- src/libdramsys/DRAMSys/simulation/Arbiter.cpp | 127 +-- src/libdramsys/DRAMSys/simulation/Arbiter.h | 46 +- src/libdramsys/DRAMSys/simulation/DRAMSys.cpp | 100 +-- src/libdramsys/DRAMSys/simulation/DRAMSys.h | 38 +- .../DRAMSys/simulation/DRAMSysRecordable.cpp | 62 +- .../DRAMSys/simulation/DRAMSysRecordable.h | 12 +- .../DRAMSys/simulation/ReorderBuffer.h | 47 +- .../simulation/TemperatureController.cpp | 185 ---- .../simulation/TemperatureController.h | 151 ---- .../DRAMSys/simulation/dram/Dram.cpp | 35 +- src/libdramsys/DRAMSys/simulation/dram/Dram.h | 16 +- .../DRAMSys/simulation/dram/DramDDR3.cpp | 14 +- .../DRAMSys/simulation/dram/DramDDR3.h | 8 +- .../DRAMSys/simulation/dram/DramDDR4.cpp | 14 +- .../DRAMSys/simulation/dram/DramDDR4.h | 8 +- .../DRAMSys/simulation/dram/DramGDDR5.cpp | 12 +- .../DRAMSys/simulation/dram/DramGDDR5.h | 8 +- .../DRAMSys/simulation/dram/DramGDDR5X.cpp | 10 +- .../DRAMSys/simulation/dram/DramGDDR5X.h | 8 +- .../DRAMSys/simulation/dram/DramGDDR6.cpp | 10 +- .../DRAMSys/simulation/dram/DramGDDR6.h | 8 +- .../DRAMSys/simulation/dram/DramHBM2.cpp | 10 +- .../DRAMSys/simulation/dram/DramHBM2.h | 8 +- .../DRAMSys/simulation/dram/DramHBM3.cpp | 51 -- .../DRAMSys/simulation/dram/DramHBM3.h | 52 -- .../DRAMSys/simulation/dram/DramLPDDR4.cpp | 10 +- .../DRAMSys/simulation/dram/DramLPDDR4.h | 8 +- .../simulation/dram/DramRecordable.cpp | 52 +- .../DRAMSys/simulation/dram/DramRecordable.h | 19 +- .../DRAMSys/simulation/dram/DramSTTMRAM.cpp | 10 +- .../DRAMSys/simulation/dram/DramSTTMRAM.h | 8 +- .../DRAMSys/simulation/dram/DramWideIO.cpp | 75 +- .../DRAMSys/simulation/dram/DramWideIO.h | 17 +- .../DRAMSys/simulation/dram/DramWideIO2.cpp | 10 +- .../DRAMSys/simulation/dram/DramWideIO2.h | 8 +- src/libdramsys/sources.lst | 195 ----- src/simulator/CMakeLists.txt | 1 + src/simulator/simulator/MemoryManager.h | 2 +- src/simulator/simulator/TrafficGenerator.h | 6 +- src/simulator/simulator/TrafficInitiator.cpp | 1 - src/simulator/simulator/TrafficInitiator.h | 2 +- src/simulator/{ => simulator}/main.cpp | 0 src/util/DRAMSys/util/json.h | 2 +- 172 files changed, 826 insertions(+), 5434 deletions(-) delete mode 100644 src/libdramsys/CMakeLists - Copy.txt delete mode 100644 src/libdramsys/DRAMSys/configuration/TemperatureSimConfig.h delete mode 100644 src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.cpp delete mode 100644 src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.h delete mode 100644 src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.cpp delete mode 100644 src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.h delete mode 100644 src/libdramsys/DRAMSys/error/ECC/Bit.cpp delete mode 100644 src/libdramsys/DRAMSys/error/ECC/Bit.h delete mode 100644 src/libdramsys/DRAMSys/error/ECC/ECC.cpp delete mode 100644 src/libdramsys/DRAMSys/error/ECC/ECC.h delete mode 100644 src/libdramsys/DRAMSys/error/ECC/ECC_Test.cpp delete mode 100644 src/libdramsys/DRAMSys/error/ECC/Word.cpp delete mode 100644 src/libdramsys/DRAMSys/error/ECC/Word.h delete mode 100644 src/libdramsys/DRAMSys/error/eccbaseclass.cpp delete mode 100644 src/libdramsys/DRAMSys/error/eccbaseclass.h delete mode 100644 src/libdramsys/DRAMSys/error/ecchamming.cpp delete mode 100644 src/libdramsys/DRAMSys/error/ecchamming.h delete mode 100644 src/libdramsys/DRAMSys/error/errormodel.cpp delete mode 100644 src/libdramsys/DRAMSys/error/errormodel.h delete mode 100644 src/libdramsys/DRAMSys/simulation/TemperatureController.cpp delete mode 100644 src/libdramsys/DRAMSys/simulation/TemperatureController.h delete mode 100644 src/libdramsys/DRAMSys/simulation/dram/DramHBM3.cpp delete mode 100644 src/libdramsys/DRAMSys/simulation/dram/DramHBM3.h delete mode 100644 src/libdramsys/sources.lst rename src/simulator/{ => simulator}/main.cpp (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 73b02cbf..81e74a04 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -69,7 +69,7 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) endif() -### DRAMPower directories ### +### DRAMSys directories ### set(DRAMSYS_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/src") set(DRAMSYS_LIBRARY_DIR "${CMAKE_CURRENT_SOURCE_DIR}/lib") set(DRAMSYS_TESTS_DIR "${CMAKE_CURRENT_SOURCE_DIR}/tests") @@ -79,14 +79,14 @@ set(DRAMSYS_EXTENSIONS_DIR "${CMAKE_CURRENT_SOURCE_DIR}/extensions") ### Build options ### option(DRAMSYS_BUILD_TESTS "Build DRAMSys unit tests" OFF) option(DRAMSYS_VERBOSE_CMAKE_OUTPUT "Show detailed CMake output" OFF) -option(DRAMSYS_BUILD_CLI "Build DRAMSys Command Line Tool" OFF) +option(DRAMSYS_BUILD_CLI "Build DRAMSys Command Line Tool" ON) option(DRAMSYS_COVERAGE_CHECK "Coverage check of DRAMSys" OFF) option(DRAMSYS_WITH_GEM5 "Build DRAMSys with gem5 coupling" OFF) option(DRAMSYS_WITH_DRAMPOWER "Build with DRAMPower support enabled." OFF) option(DRAMSYS_ENABLE_EXTENSIONS "Enable proprietary DRAMSys extensions." OFF) ### Compiler settings ### -set(CMAKE_CXX_STANDARD 23) +set(CMAKE_CXX_STANDARD 17) if(DRAMSYS_COVERAGE_CHECK) message("== Coverage check enabled") diff --git a/src/configuration/DRAMSys/config/AddressMapping.h b/src/configuration/DRAMSys/config/AddressMapping.h index 52e67f86..bcc9f4df 100644 --- a/src/configuration/DRAMSys/config/AddressMapping.h +++ b/src/configuration/DRAMSys/config/AddressMapping.h @@ -36,7 +36,7 @@ #ifndef DRAMSYSCONFIGURATION_ADDRESSMAPPING_H #define DRAMSYSCONFIGURATION_ADDRESSMAPPING_H -#include +#include "DRAMSys/config/ConfigUtil.h" #include diff --git a/src/configuration/DRAMSys/config/ConfigUtil.cpp b/src/configuration/DRAMSys/config/ConfigUtil.cpp index bcd35ad0..8024cfee 100644 --- a/src/configuration/DRAMSys/config/ConfigUtil.cpp +++ b/src/configuration/DRAMSys/config/ConfigUtil.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Technische Universität Kaiserslautern + * Copyright (c) 2021, Technische Universität Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,9 +33,9 @@ * Derek Christ */ -#include "DRAMSys/config/ConfigUtil.h" +#include "ConfigUtil.h" -#include "DRAMSysConfiguration.h" +#include "DRAMSys/config/DRAMSysConfiguration.h" #include #include diff --git a/src/configuration/DRAMSys/config/ConfigUtil.h b/src/configuration/DRAMSys/config/ConfigUtil.h index 53ba6d46..9c45aa5b 100644 --- a/src/configuration/DRAMSys/config/ConfigUtil.h +++ b/src/configuration/DRAMSys/config/ConfigUtil.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Technische Universität Kaiserslautern + * Copyright (c) 2021, Technische Universität Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -41,7 +41,6 @@ #include #include - namespace DRAMSys::Config { //using json_t = nlohmann::json; diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp index d2ad67d8..a3baeac8 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp @@ -37,10 +37,8 @@ #include "DRAMSys/config/ConfigUtil.h" -#include #include - namespace DRAMSys::Config { diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.h b/src/configuration/DRAMSys/config/DRAMSysConfiguration.h index 360cd9fa..e44cf44f 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.h +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.h @@ -42,7 +42,6 @@ #include "DRAMSys/config/ThermalConfig.h" #include "DRAMSys/config/TraceSetup.h" #include "DRAMSys/config/memspec/MemSpec.h" - #include "DRAMSys/config/ConfigUtil.h" #include @@ -67,7 +66,6 @@ struct Configuration MemSpec memSpec; SimConfig simConfig; std::string simulationId; - std::optional thermalConfig; std::optional traceSetup; static std::string resourceDirectory; diff --git a/src/configuration/DRAMSys/config/memspec/MemSpec.h b/src/configuration/DRAMSys/config/memspec/MemSpec.h index d5089c69..79708d63 100644 --- a/src/configuration/DRAMSys/config/memspec/MemSpec.h +++ b/src/configuration/DRAMSys/config/memspec/MemSpec.h @@ -37,10 +37,9 @@ #define DRAMSYSCONFIGURATION_MEMSPEC_H #include "DRAMSys/config/ConfigUtil.h" - -#include "MemArchitectureSpec.h" -#include "MemPowerSpec.h" -#include "MemTimingSpec.h" +#include "DRAMSys/config/memspec/MemArchitectureSpec.h" +#include "DRAMSys/config/memspec/MemPowerSpec.h" +#include "DRAMSys/config/memspec/MemTimingSpec.h" #include diff --git a/src/libdramsys/CMakeLists - Copy.txt b/src/libdramsys/CMakeLists - Copy.txt deleted file mode 100644 index f1d12de9..00000000 --- a/src/libdramsys/CMakeLists - Copy.txt +++ /dev/null @@ -1,266 +0,0 @@ -# Copyright (c) 2020, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: -# Matthias Jung -# Lukas Steiner -# Derek Christ - -cmake_minimum_required(VERSION 3.10) - -# Project Name -project(DRAMSysLibrary) - -# Configuration: -#set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version") -#set(DCMAKE_SH="CMAKE_SH-NOTFOUND") - -# Add DRAMPower: -if (DRAMSYS_WITH_DRAMPOWER) -add_subdirectory(src/common/third_party/DRAMPower) -endif() - -# Add Configuration -add_subdirectory(src/common/configuration) - -# Add SystemC: -if(DEFINED ENV{SYSTEMC_HOME}) - find_library(SYSTEMC_LIBRARY - NAMES systemc SnpsVP - PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/lib64 $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/ - ) - message("== Building with external SystemC located in $ENV{SYSTEMC_HOME}") -else() - set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs") - add_subdirectory(src/common/third_party/systemc) - set(SYSTEMC_LIBRARY systemc) - message("== Building with SystemC submodule") -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation) - message("== Database recording included") - # Add sqlite3 Dependency: - set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature") - set(BUILD_ENABLE_RTREE ON) - add_subdirectory(src/common/third_party/sqlite-amalgamation) - - set(RECORDING_SOURCES - src/common/TlmRecorder.cpp - src/controller/ControllerRecordable.cpp - src/simulation/DRAMSysRecordable.cpp - src/simulation/dram/DramRecordable.cpp - ) -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerDDR5.cpp) - message("== DDR5 included") - set(DDR5_SOURCES - src/configuration/memspec/MemSpecDDR5.cpp - src/controller/checker/CheckerDDR5.cpp - src/simulation/dram/DramDDR5.cpp - ) -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerLPDDR5.cpp) - message("== LPDDR5 included") - set(LPDDR5_SOURCES - src/configuration/memspec/MemSpecLPDDR5.cpp - src/controller/checker/CheckerLPDDR5.cpp - src/simulation/dram/DramLPDDR5.cpp - ) -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerHBM3.cpp) - message("== HBM3 included") - set(HBM3_SOURCES - src/configuration/memspec/MemSpecHBM3.cpp - src/controller/checker/CheckerHBM3.cpp - src/simulation/dram/DramHBM3.cpp - ) -endif() - -add_library(DRAMSysLibrary - src/common/DebugManager.cpp - src/common/dramExtensions.cpp - src/common/tlm2_base_protocol_checker.h - src/common/utils.cpp - - src/configuration/Configuration.cpp - src/configuration/TemperatureSimConfig.h - - src/configuration/memspec/MemSpec.cpp - src/configuration/memspec/MemSpecDDR3.cpp - src/configuration/memspec/MemSpecDDR4.cpp - src/configuration/memspec/MemSpecLPDDR4.cpp - src/configuration/memspec/MemSpecWideIO.cpp - src/configuration/memspec/MemSpecWideIO2.cpp - src/configuration/memspec/MemSpecGDDR5.cpp - src/configuration/memspec/MemSpecGDDR5X.cpp - src/configuration/memspec/MemSpecGDDR6.cpp - src/configuration/memspec/MemSpecHBM2.cpp - src/configuration/memspec/MemSpecSTTMRAM.cpp - - src/controller/BankMachine.cpp - src/controller/Command.cpp - src/controller/ControllerIF.h - src/controller/Controller.cpp - - src/controller/checker/CheckerIF.h - src/controller/checker/CheckerDDR3.cpp - src/controller/checker/CheckerDDR4.cpp - src/controller/checker/CheckerLPDDR4.cpp - src/controller/checker/CheckerWideIO.cpp - src/controller/checker/CheckerWideIO2.cpp - src/controller/checker/CheckerGDDR5.cpp - src/controller/checker/CheckerGDDR5X.cpp - src/controller/checker/CheckerGDDR6.cpp - src/controller/checker/CheckerHBM2.cpp - src/controller/checker/CheckerSTTMRAM.cpp - - src/controller/cmdmux/CmdMuxIF.h - src/controller/cmdmux/CmdMuxOldest.cpp - src/controller/cmdmux/CmdMuxStrict.cpp - - src/controller/powerdown/PowerDownManagerIF.h - src/controller/powerdown/PowerDownManagerDummy.cpp - src/controller/powerdown/PowerDownManagerStaggered.cpp - - src/controller/refresh/RefreshManagerIF.h - src/controller/refresh/RefreshManagerDummy.cpp - src/controller/refresh/RefreshManagerAllBank.cpp - src/controller/refresh/RefreshManagerPerBank.cpp - src/controller/refresh/RefreshManagerPer2Bank.cpp - src/controller/refresh/RefreshManagerSameBank.cpp - - src/controller/respqueue/RespQueueIF.h - src/controller/respqueue/RespQueueFifo.cpp - src/controller/respqueue/RespQueueReorder.cpp - - src/controller/scheduler/SchedulerIF.h - src/controller/scheduler/SchedulerFifo.cpp - src/controller/scheduler/SchedulerFrFcfs.cpp - src/controller/scheduler/SchedulerFrFcfsGrp.cpp - src/controller/scheduler/SchedulerGrpFrFcfs.cpp - src/controller/scheduler/SchedulerGrpFrFcfsWm.cpp - - src/controller/scheduler/BufferCounterIF.h - src/controller/scheduler/BufferCounterBankwise.cpp - src/controller/scheduler/BufferCounterReadWrite.cpp - src/controller/scheduler/BufferCounterShared.cpp - - src/error/eccbaseclass.cpp - src/error/ecchamming.cpp - src/error/errormodel.cpp - - src/error/ECC/Bit.cpp - src/error/ECC/ECC.cpp - src/error/ECC/Word.cpp - - src/simulation/Arbiter.cpp - src/simulation/AddressDecoder.cpp - src/simulation/DRAMSys.cpp - src/simulation/ReorderBuffer.h - src/simulation/TemperatureController.cpp - - src/simulation/dram/Dram.cpp - src/simulation/dram/DramDDR3.cpp - src/simulation/dram/DramDDR4.cpp - src/simulation/dram/DramLPDDR4.cpp - src/simulation/dram/DramWideIO.cpp - src/simulation/dram/DramWideIO2.cpp - src/simulation/dram/DramGDDR5.cpp - src/simulation/dram/DramGDDR5X.cpp - src/simulation/dram/DramGDDR6.cpp - src/simulation/dram/DramHBM2.cpp - src/simulation/dram/DramSTTMRAM.cpp - - ${RECORDING_SOURCES} - ${DDR5_SOURCES} - ${LPDDR5_SOURCES} - ${HBM3_SOURCES} -) - -if(DEFINED DDR5_SOURCES) - target_compile_definitions(DRAMSysLibrary PRIVATE DDR5_SIM) -endif() - -if(DEFINED LPDDR5_SOURCES) - target_compile_definitions(DRAMSysLibrary PRIVATE LPDDR5_SIM) -endif() - -if(DEFINED HBM3_SOURCES) - target_compile_definitions(DRAMSysLibrary PRIVATE HBM3_SIM) -endif() - -if(DEFINED ENV{LIBTHREED_ICE_HOME}) - message("== Thermal simulation available") - target_compile_definitions(DRAMSysLibrary PRIVATE THERMALSIM) - target_include_directories(DRAMSysLibrary - PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/ - ) - find_library(3DICE_LIBRARY NAMES threed-ice-2.2.4 PATHS $ENV{LIBTHREED_ICE_HOME}/lib/) - target_link_libraries(DRAMSysLibrary - PRIVATE ${3DICE_LIBRARY} - ) -endif() - -if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation) - target_include_directories(DRAMSysLibrary - PUBLIC src/common/third_party/sqlite-amalgamation/ - ) - target_link_libraries(DRAMSysLibrary - PRIVATE sqlite3::sqlite3 - ) -endif() - -# Build: -target_include_directories(DRAMSysLibrary - PRIVATE src/common/third_party/DRAMPower/src/ - PUBLIC $ENV{SYSTEMC_HOME}/include/ -) - -if(EXISTS $ENV{SYSTEMC_HOME}/include/tlm/) - target_include_directories(DRAMSysLibrary - PUBLIC $ENV{SYSTEMC_HOME}/include/tlm/ - ) -endif() - -target_link_libraries(DRAMSysLibrary - PUBLIC ${SYSTEMC_LIBRARY} - PUBLIC DRAMSysConfiguration -) - -if (DRAMSYS_WITH_DRAMPOWER) -target_compile_definitions(DRAMSysLibrary PRIVATE DRAMPOWER) - -target_link_libraries(DRAMSysLibrary - PRIVATE DRAMPower -) -endif() diff --git a/src/libdramsys/CMakeLists.txt b/src/libdramsys/CMakeLists.txt index 5b93063f..33495c96 100644 --- a/src/libdramsys/CMakeLists.txt +++ b/src/libdramsys/CMakeLists.txt @@ -38,10 +38,8 @@ project(DRAMSys_libdramsys) -#file(GLOB_RECURSE SOURCE_FILES CONFIGURE_DEPENDS *.cpp) -#file(GLOB_RECURSE HEADER_FILES CONFIGURE_DEPENDS *.h;*.hpp) - -include(sources.lst) +file(GLOB_RECURSE SOURCE_FILES CONFIGURE_DEPENDS *.cpp) +file(GLOB_RECURSE HEADER_FILES CONFIGURE_DEPENDS *.h;*.hpp) add_library(${PROJECT_NAME} STATIC ${SOURCE_FILES} ${HEADER_FILES}) diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index 70681f8a..55bb66ef 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -40,9 +40,8 @@ */ #include "TlmRecorder.h" -#include "../configuration/Configuration.h" -#include "../controller/Command.h" -#include "DebugManager.h" + +#include "DRAMSys/common/DebugManager.h" #include #include diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index b4ccd8fc..1b01a163 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -41,6 +41,10 @@ #ifndef TLMRECORDER_H #define TLMRECORDER_H +#include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/common/utils.h" + #include #include #include @@ -49,10 +53,6 @@ #include #include -#include "../configuration/Configuration.h" -#include "dramExtensions.h" -#include "utils.h" - class sqlite3; class sqlite3_stmt; diff --git a/src/libdramsys/DRAMSys/common/utils.cpp b/src/libdramsys/DRAMSys/common/utils.cpp index 9784289d..70df58d6 100644 --- a/src/libdramsys/DRAMSys/common/utils.cpp +++ b/src/libdramsys/DRAMSys/common/utils.cpp @@ -37,11 +37,10 @@ * Derek Christ */ -#include -#include - #include "utils.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index a0b90f26..f6c6a2c0 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -40,11 +40,11 @@ #ifndef UTILS_H #define UTILS_H -#include +#include "DRAMSys/common/dramExtensions.h" #include #include -#include "dramExtensions.h" +#include class TimeInterval { diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.cpp b/src/libdramsys/DRAMSys/configuration/Configuration.cpp index 7bc52949..d7ca08d7 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.cpp +++ b/src/libdramsys/DRAMSys/configuration/Configuration.cpp @@ -40,25 +40,26 @@ */ #include "Configuration.h" -#include "memspec/MemSpecDDR3.h" -#include "memspec/MemSpecDDR4.h" -#include "memspec/MemSpecWideIO.h" -#include "memspec/MemSpecLPDDR4.h" -#include "memspec/MemSpecWideIO2.h" -#include "memspec/MemSpecHBM2.h" -#include "memspec/MemSpecGDDR5.h" -#include "memspec/MemSpecGDDR5X.h" -#include "memspec/MemSpecGDDR6.h" -#include "memspec/MemSpecSTTMRAM.h" + +#include "DRAMSys/configuration/memspec/MemSpecDDR3.h" +#include "DRAMSys/configuration/memspec/MemSpecDDR4.h" +#include "DRAMSys/configuration/memspec/MemSpecWideIO.h" +#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h" +#include "DRAMSys/configuration/memspec/MemSpecWideIO2.h" +#include "DRAMSys/configuration/memspec/MemSpecHBM2.h" +#include "DRAMSys/configuration/memspec/MemSpecGDDR5.h" +#include "DRAMSys/configuration/memspec/MemSpecGDDR5X.h" +#include "DRAMSys/configuration/memspec/MemSpecGDDR6.h" +#include "DRAMSys/configuration/memspec/MemSpecSTTMRAM.h" #ifdef DDR5_SIM -#include +#include "DRAMSys/configuration/memspec/MemSpecDDR5.h" #endif #ifdef LPDDR5_SIM -#include +#include "DRAMSys/configuration/memspec/MemSpecLPDDR5.h" #endif #ifdef HBM3_SIM -#include "memspec/MemSpecHBM3.h" +#include "DRAMSys/configuration/memspec/MemSpecHBM3.h" #endif using namespace sc_core; @@ -102,7 +103,13 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) enableWindowing = *_enableWindowing; if (const auto& _powerAnalysis = simConfig.powerAnalysis) + { powerAnalysis = *_powerAnalysis; +#ifndef DRAMPOWER + if (powerAnalysis) + SC_REPORT_FATAL("Configuration", "Power analysis is only supported with included DRAMPower library!"); +#endif + } if (const auto& _simulationName = simConfig.simulationName) simulationName = *_simulationName; @@ -110,9 +117,6 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) if (const auto& _simulationProgressBar = simConfig.simulationProgressBar) simulationProgressBar = *_simulationProgressBar; - if (const auto& _thermalSimulation = simConfig.thermalSimulation) - thermalSimulation = *_thermalSimulation; - if (const auto& _useMalloc = simConfig.useMalloc) useMalloc = *_useMalloc; @@ -122,68 +126,15 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) if (windowSize == 0) SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); - if (const auto& _errorCsvFile = simConfig.errorCsvFile) - errorCSVFile = *_errorCsvFile; - - if (const auto& _errorChipSeed = simConfig.errorChipSeed) - errorChipSeed = *_errorChipSeed; - if (const auto& _storeMode = simConfig.storeMode) storeMode = [=] { if (_storeMode == DRAMSys::Config::StoreMode::NoStorage) return StoreMode::NoStorage; - else if (_storeMode == DRAMSys::Config::StoreMode::Store) + else // (_storeMode == DRAMSys::Config::StoreMode::Store) return StoreMode::Store; - else - return StoreMode::ErrorModel; }(); } -void Configuration::loadTemperatureSimConfig(const DRAMSys::Config::ThermalConfig &thermalConfig) -{ - temperatureSim.temperatureScale = [=] { - if (thermalConfig.temperatureScale == DRAMSys::Config::TemperatureScale::Celsius) - return TemperatureSimConfig::TemperatureScale::Celsius; - else if (thermalConfig.temperatureScale == DRAMSys::Config::TemperatureScale::Fahrenheit) - return TemperatureSimConfig::TemperatureScale::Fahrenheit; - else - return TemperatureSimConfig::TemperatureScale::Kelvin; - }(); - - temperatureSim.staticTemperatureDefaultValue = thermalConfig.staticTemperatureDefaultValue; - temperatureSim.thermalSimPeriod = thermalConfig.thermalSimPeriod; - - temperatureSim.thermalSimUnit = [=] { - if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Seconds) - return sc_core::SC_SEC; - else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Milliseconds) - return sc_core::SC_MS; - else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Microseconds) - return sc_core::SC_US; - else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Nanoseconds) - return sc_core::SC_NS; - else if (thermalConfig.thermalSimUnit == DRAMSys::Config::ThermalSimUnit::Picoseconds) - return sc_core::SC_PS; - else - return sc_core::SC_FS; - }(); - - for (const auto &channel : thermalConfig.powerInfo.channels) - { - temperatureSim.powerInitialValues.push_back(channel.init_pow); - temperatureSim.powerThresholds.push_back(channel.threshold); - } - - temperatureSim.iceServerIp = thermalConfig.iceServerIp; - temperatureSim.iceServerPort = thermalConfig.iceServerPort; - temperatureSim.simPeriodAdjustFactor = thermalConfig.simPeriodAdjustFactor; - temperatureSim.nPowStableCyclesToIncreasePeriod = thermalConfig.nPowStableCyclesToIncreasePeriod; - temperatureSim.generateTemperatureMap = thermalConfig.generateTemperatureMap; - temperatureSim.generatePowerMap = thermalConfig.generatePowerMap; - - temperatureSim.showTemperatureSimConfig(); -} - void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig) { if (const auto& _pagePolicy = mcConfig.pagePolicy) diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index a92cd654..7a4cfc20 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -43,13 +43,10 @@ #ifndef CONFIGURATION_H #define CONFIGURATION_H -#include - -#include "memspec/MemSpec.h" -#include "TemperatureSimConfig.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/config/DRAMSysConfiguration.h" #include - #include class Configuration @@ -74,7 +71,6 @@ public: unsigned int refreshMaxPostponed = 0; unsigned int refreshMaxPulledin = 0; enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy = PowerDownPolicy::NoPowerDown; - unsigned int powerDownTimeout = 3; unsigned int maxActiveTransactions = 64; bool refreshManagement = false; sc_core::sc_time arbitrationDelayFw = sc_core::SC_ZERO_TIME; @@ -91,27 +87,19 @@ public: bool enableWindowing = false; unsigned int windowSize = 1000; bool debug = false; - bool thermalSimulation = false; bool simulationProgressBar = false; bool checkTLM2Protocol = false; bool useMalloc = false; unsigned long long int addressOffset = 0; - //Configs for Seed, csv file and StorageMode - unsigned int errorChipSeed = 0; - std::string errorCSVFile = "not defined."; - enum class StoreMode {NoStorage, Store, ErrorModel} storeMode = StoreMode::NoStorage; + enum class StoreMode {NoStorage, Store} storeMode = StoreMode::NoStorage; // MemSpec (from DRAM-Power) std::unique_ptr memSpec; - // Temperature Simulation related - TemperatureSimConfig temperatureSim; - void loadMCConfig(const DRAMSys::Config::McConfig& mcConfig); void loadSimConfig(const DRAMSys::Config::SimConfig& simConfig); void loadMemSpec(const DRAMSys::Config::MemSpec& memSpec); - void loadTemperatureSimConfig(const DRAMSys::Config::ThermalConfig& thermalConfig); }; #endif // CONFIGURATION_H diff --git a/src/libdramsys/DRAMSys/configuration/TemperatureSimConfig.h b/src/libdramsys/DRAMSys/configuration/TemperatureSimConfig.h deleted file mode 100644 index 0c190dcd..00000000 --- a/src/libdramsys/DRAMSys/configuration/TemperatureSimConfig.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2015, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Eder F. Zulian - * Matthias Jung - * Luiza Correa - * Derek Christ - */ - -#ifndef TEMPERATURESIMCONFIG_H -#define TEMPERATURESIMCONFIG_H - -#include -#include -#include -#include -#include -#include "../common/DebugManager.h" - -struct TemperatureSimConfig -{ - // Temperature Scale - enum class TemperatureScale {Celsius, Fahrenheit, Kelvin} temperatureScale; - - // Static Temperature Simulation parameters - int staticTemperatureDefaultValue; - - // Thermal Simulation parameters - double thermalSimPeriod; - enum sc_core::sc_time_unit thermalSimUnit; - std::string iceServerIp; - unsigned int iceServerPort; - unsigned int simPeriodAdjustFactor; - unsigned int nPowStableCyclesToIncreasePeriod; - bool generateTemperatureMap; - bool generatePowerMap; - - // Power related information - std::vector powerInitialValues; - std::vector powerThresholds; - - void showTemperatureSimConfig() - { - NDEBUG_UNUSED(int i) = 0; - for (NDEBUG_UNUSED(auto e) : powerInitialValues) - { - PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerInitialValues[" - + std::to_string(i++) + "]: " + std::to_string(e)); - } - i = 0; - for (NDEBUG_UNUSED(auto e) : powerThresholds) - { - PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerThreshold[" - + std::to_string(i++) + "]: " + std::to_string(e)); - } - } -}; - -#endif // TEMPERATURESIMCONFIG_H - diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 3d5cdacd..19e449f2 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -39,16 +39,14 @@ #ifndef MEMSPEC_H #define MEMSPEC_H -#include - - +#include #include #include -#include -#include #include #include +#include +#include class MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 23f59e12..9271fdf5 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecDDR3.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index 11832d01..a5c03d58 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -37,10 +37,10 @@ #ifndef MEMSPECDDR3_H #define MEMSPECDDR3_H -#include "MemSpec.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/config/DRAMSysConfiguration.h" #include -#include class MemSpecDDR3 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 83af4929..594cda9b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecDDR4.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 72eb6f1e..51b9d320 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -37,8 +37,9 @@ #ifndef MEMSPECDDR4_H #define MEMSPECDDR4_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecDDR4 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index c1bd529c..976f5ae1 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecGDDR5.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index 5a377694..72634e58 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -37,8 +37,9 @@ #ifndef MEMSPECGDDR5_H #define MEMSPECGDDR5_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecGDDR5 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 6fb3d562..7b4cf66e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -33,11 +33,13 @@ * Lukas Steiner * Derek Christ */ -#include -#include "../../common/utils.h" #include "MemSpecGDDR5X.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 99092a33..75faec54 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -37,8 +37,9 @@ #ifndef MEMSPECGDDR5X_H #define MEMSPECGDDR5X_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecGDDR5X final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 57ac9eba..64b78b14 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecGDDR6.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index c6f7266c..82711fbc 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -37,8 +37,9 @@ #ifndef MEMSPECGDDR6_H #define MEMSPECGDDR6_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" struct MemSpecGDDR6 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 0e5d188d..479a9069 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecHBM2.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index c87b07d3..b9d4e8a8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -37,8 +37,9 @@ #ifndef MEMSPECHBM2_H #define MEMSPECHBM2_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecHBM2 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.cpp deleted file mode 100644 index d5aeaada..00000000 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.cpp +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2019, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - * Derek Christ - */ - -#include - -#include "../../common/utils.h" -#include "MemSpecHBM3.h" - -using namespace sc_core; -using namespace tlm; - -MemSpecHBM3::MemSpecHBM3(const DRAMSysConfiguration::MemSpec &memSpec) - : MemSpec(memSpec, MemoryType::HBM3, - memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), - memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"), - memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"), - memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), - memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), - memSpec.memArchitectureSpec.entries.at("nbrOfBanks") - / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), - memSpec.memArchitectureSpec.entries.at("nbrOfBanks") - * memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"), - memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") - * memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"), - memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), - RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")), - RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")), - RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")), - tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), - tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), - tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), - tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")), - tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")), - tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")), - tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")), - tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), - tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), - tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), - tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), - tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), - tPL (tCK * memSpec.memTimingSpec.entries.at("PL")), - tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), - tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")), - tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")), - tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")), - tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")), - tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")), - tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), - tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), - tPD (tCKE), - tCKESR (tCKE + tCK), - tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), - tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")), - tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")), - tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")), - tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), - tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")), - tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")) -{ - commandLengthInCycles[Command::ACT] = 1.5; - commandLengthInCycles[Command::PREPB] = 0.5; - commandLengthInCycles[Command::PREAB] = 0.5; - commandLengthInCycles[Command::REFPB] = 0.5; - commandLengthInCycles[Command::REFAB] = 0.5; - commandLengthInCycles[Command::RFMPB] = 0.5; - commandLengthInCycles[Command::RFMAB] = 0.5; - commandLengthInCycles[Command::PDXA] = 0.5; - commandLengthInCycles[Command::SREFEX] = 0.5; - - uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; - uint64_t deviceSizeBytes = deviceSizeBits / 8; - memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; - - std::cout << headline << std::endl; - std::cout << "Memory Configuration:" << std::endl << std::endl; - std::cout << " Memory type: " << "HBM3" << std::endl; - std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl; - std::cout << " Channels: " << numberOfChannels << std::endl; - std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl; - std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl; - std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl; - std::cout << " Rows per bank: " << rowsPerBank << std::endl; - std::cout << " Columns per row: " << columnsPerRow << std::endl; - std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl; - std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl; - std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl; - std::cout << std::endl; -} - -sc_time MemSpecHBM3::getRefreshIntervalAB() const -{ - return tREFI; -} - -sc_time MemSpecHBM3::getRefreshIntervalPB() const -{ - return tREFIPB; -} - -bool MemSpecHBM3::hasRasAndCasBus() const -{ - return true; -} - -sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload &payload) const -{ - if (command == Command::PREPB || command == Command::PREAB) - return tRP; - else if (command == Command::ACT) - { - if (payload.get_command() == TLM_READ_COMMAND) - return tRCDRD + tCK; - else - return tRCDWR + tCK; - } - else if (command == Command::RD) - return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) - return tRTP + tRP; - else if (command == Command::WR) - return tWL + burstDuration; - else if (command == Command::WRA) - return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB || command == Command::RFMAB) - return tRFC; - else if (command == Command::REFPB || command == Command::RFMPB) - return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } -} - -TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const -{ - if (command == Command::RD || command == Command::RDA) - return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA) - return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecHBM3", "Method was called with invalid argument"); - return {}; - } -} - -unsigned MemSpecHBM3::getRAACDR() const -{ - return RAACDR; -} - -unsigned MemSpecHBM3::getRAAIMT() const -{ - return RAAIMT; -} - -unsigned MemSpecHBM3::getRAAMMT() const -{ - return RAAMMT; -} diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.h deleted file mode 100644 index 80e356e5..00000000 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM3.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2019, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - * Derek Christ - */ - -#ifndef MemSpecHBM3_H -#define MemSpecHBM3_H - -#include -#include "MemSpec.h" - -class MemSpecHBM3 final : public MemSpec -{ -public: - explicit MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec); - - const unsigned RAAIMT; - const unsigned RAAMMT; - const unsigned RAACDR; - - // Memspec Variables: - const sc_core::sc_time tDQSCK; -// sc_time tDQSQ; // TODO: check actual value of this parameter - const sc_core::sc_time tRC; - const sc_core::sc_time tRAS; - const sc_core::sc_time tRCDRD; - const sc_core::sc_time tRCDWR; - const sc_core::sc_time tRRDL; - const sc_core::sc_time tRRDS; - const sc_core::sc_time tFAW; - const sc_core::sc_time tRTP; - const sc_core::sc_time tRP; - const sc_core::sc_time tRL; - const sc_core::sc_time tWL; - const sc_core::sc_time tPL; - const sc_core::sc_time tWR; - const sc_core::sc_time tCCDL; - const sc_core::sc_time tCCDS; -// sc_time tCCDR; // TODO: consecutive reads to different stack IDs - const sc_core::sc_time tWTRL; - const sc_core::sc_time tWTRS; - const sc_core::sc_time tRTW; - const sc_core::sc_time tXP; - const sc_core::sc_time tCKE; - const sc_core::sc_time tPD; // = tCKE; - const sc_core::sc_time tCKESR; // = tCKE + tCK; - const sc_core::sc_time tXS; - const sc_core::sc_time tRFC; - const sc_core::sc_time tRFCPB; - const sc_core::sc_time tRREFD; - const sc_core::sc_time tREFI; - const sc_core::sc_time tREFIPB; - const sc_core::sc_time tPPD; - - // Currents and Voltages: - // TODO: to be completed - - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; - - unsigned getRAACDR() const override; - unsigned getRAAIMT() const override; - unsigned getRAAMMT() const override; - - bool hasRasAndCasBus() const override; - - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; -}; - -#endif // MemSpecHBM3_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index f84a4176..0c8b80ea 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecLPDDR4.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 541e1c9b..343677c5 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -37,8 +37,9 @@ #ifndef MEMSPECLPDDR4_H #define MEMSPECLPDDR4_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecLPDDR4 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index f6bbd1d1..b68f15f0 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecSTTMRAM.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index 4171b1c4..b31e2b2d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -37,8 +37,9 @@ #ifndef MEMSPECSTTMRAM_H #define MEMSPECSTTMRAM_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecSTTMRAM final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index 0fa297b6..a47a3e77 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecWideIO.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index 8deb06c8..e34a8892 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -37,8 +37,9 @@ #ifndef MEMSPECWIDEIO_H #define MEMSPECWIDEIO_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecWideIO final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index 07f67cf6..2cb5a443 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -34,11 +34,12 @@ * Derek Christ */ -#include - -#include "../../common/utils.h" #include "MemSpecWideIO2.h" +#include "DRAMSys/common/utils.h" + +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index 9db78fa5..8138e9ec 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -37,8 +37,9 @@ #ifndef MEMSPECWIDEIO2_H #define MEMSPECWIDEIO2_H +#include "DRAMSys/configuration/memspec/MemSpec.h" + #include -#include "MemSpec.h" class MemSpecWideIO2 final : public MemSpec { diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index cea8d1c9..9f7cabcd 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -32,10 +32,11 @@ * Author: Lukas Steiner */ -#include - #include "BankMachine.h" -#include + +#include "DRAMSys/configuration/Configuration.h" + +#include using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index 3515bf7d..820d0919 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -35,18 +35,16 @@ #ifndef BANKMACHINE_H #define BANKMACHINE_H +#include "DRAMSys/controller/scheduler/SchedulerIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/Command.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include -#include -#include - -#include "scheduler/SchedulerIF.h" -#include "checker/CheckerIF.h" - -#include "Command.h" - class BankMachine { public: @@ -56,20 +54,20 @@ public: void updateState(Command); void block(); - Rank getRank() const; - BankGroup getBankGroup() const; - Bank getBank() const; - Row getOpenRow() const; - bool isIdle() const; - bool isActivated() const; - bool isPrecharged() const; - uint64_t getRefreshManagementCounter() const; + [[nodiscard]] Rank getRank() const; + [[nodiscard]] BankGroup getBankGroup() const; + [[nodiscard]] Bank getBank() const; + [[nodiscard]] Row getOpenRow() const; + [[nodiscard]] bool isIdle() const; + [[nodiscard]] bool isActivated() const; + [[nodiscard]] bool isPrecharged() const; + [[nodiscard]] uint64_t getRefreshManagementCounter() const; protected: enum class State {Precharged, Activated} state = State::Precharged; BankMachine(const Configuration& config, const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank); const MemSpec& memSpec; - tlm::tlm_generic_payload *currentPayload = nullptr; + tlm::tlm_generic_payload* currentPayload = nullptr; const SchedulerIF& scheduler; const CheckerIF& checker; Command nextCommand = Command::NOP; diff --git a/src/libdramsys/DRAMSys/controller/Command.cpp b/src/libdramsys/DRAMSys/controller/Command.cpp index fbb7562f..1ad12525 100644 --- a/src/libdramsys/DRAMSys/controller/Command.cpp +++ b/src/libdramsys/DRAMSys/controller/Command.cpp @@ -36,9 +36,10 @@ * Lukas Steiner */ -#include #include "Command.h" +#include + using namespace tlm; #ifdef DRAMPOWER diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 9826f083..0d6055eb 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -37,17 +37,16 @@ #ifndef COMMAND_H #define COMMAND_H -#include -#include -#include - -#include -#include - #ifdef DRAMPOWER #include "../common/third_party/DRAMPower/src/MemCommand.h" #endif +#include +#include +#include +#include +#include + // DO NOT CHANGE THE ORDER! // BEGIN_REQ // 1 @@ -84,6 +83,7 @@ DECLARE_EXTENDED_PHASE(END_SREF); // 27 #ifdef DRAMPOWER DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); #endif + bool phaseHasDataStrobe(tlm::tlm_phase phase); bool isPowerDownEntryPhase(tlm::tlm_phase phase); bool isPowerDownExitPhase(tlm::tlm_phase phase); @@ -126,18 +126,18 @@ private: public: Command() = default; - Command(Type type); - Command(tlm::tlm_phase phase); + explicit Command(Type type); + explicit Command(tlm::tlm_phase phase); - std::string toString() const; - tlm::tlm_phase toPhase() const; + [[nodiscard]] std::string toString() const; + [[nodiscard]] tlm::tlm_phase toPhase() const; static unsigned numberOfCommands(); - bool isBankCommand() const; - bool is2BankCommand() const; - bool isGroupCommand() const; - bool isRankCommand() const; - bool isCasCommand() const; - bool isRasCommand() const; + [[nodiscard]] bool isBankCommand() const; + [[nodiscard]] bool is2BankCommand() const; + [[nodiscard]] bool isGroupCommand() const; + [[nodiscard]] bool isRankCommand() const; + [[nodiscard]] bool isCasCommand() const; + [[nodiscard]] bool isRasCommand() const; constexpr operator uint8_t() const { diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index d86f614e..0965809a 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -34,44 +34,43 @@ #include "Controller.h" -#include -#include "../common/dramExtensions.h" - -#include "checker/CheckerDDR3.h" -#include "checker/CheckerDDR4.h" -#include "checker/CheckerWideIO.h" -#include "checker/CheckerLPDDR4.h" -#include "checker/CheckerWideIO2.h" -#include "checker/CheckerHBM2.h" -#include "checker/CheckerGDDR5.h" -#include "checker/CheckerGDDR5X.h" -#include "checker/CheckerGDDR6.h" -#include "checker/CheckerSTTMRAM.h" -#include "scheduler/SchedulerFifo.h" -#include "scheduler/SchedulerFrFcfs.h" -#include "scheduler/SchedulerFrFcfsGrp.h" -#include "scheduler/SchedulerGrpFrFcfs.h" -#include "scheduler/SchedulerGrpFrFcfsWm.h" -#include "cmdmux/CmdMuxStrict.h" -#include "cmdmux/CmdMuxOldest.h" -#include "respqueue/RespQueueFifo.h" -#include "respqueue/RespQueueReorder.h" -#include "refresh/RefreshManagerDummy.h" -#include "refresh/RefreshManagerAllBank.h" -#include "refresh/RefreshManagerPerBank.h" -#include "refresh/RefreshManagerPer2Bank.h" -#include "refresh/RefreshManagerSameBank.h" -#include "powerdown/PowerDownManagerStaggered.h" -#include "powerdown/PowerDownManagerDummy.h" +#include "DRAMSys/controller/checker/CheckerDDR3.h" +#include "DRAMSys/controller/checker/CheckerDDR4.h" +#include "DRAMSys/controller/checker/CheckerWideIO.h" +#include "DRAMSys/controller/checker/CheckerLPDDR4.h" +#include "DRAMSys/controller/checker/CheckerWideIO2.h" +#include "DRAMSys/controller/checker/CheckerHBM2.h" +#include "DRAMSys/controller/checker/CheckerGDDR5.h" +#include "DRAMSys/controller/checker/CheckerGDDR5X.h" +#include "DRAMSys/controller/checker/CheckerGDDR6.h" +#include "DRAMSys/controller/checker/CheckerSTTMRAM.h" +#include "DRAMSys/controller/scheduler/SchedulerFifo.h" +#include "DRAMSys/controller/scheduler/SchedulerFrFcfs.h" +#include "DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h" +#include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h" +#include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h" +#include "DRAMSys/controller/cmdmux/CmdMuxStrict.h" +#include "DRAMSys/controller/cmdmux/CmdMuxOldest.h" +#include "DRAMSys/controller/respqueue/RespQueueFifo.h" +#include "DRAMSys/controller/respqueue/RespQueueReorder.h" +#include "DRAMSys/controller/refresh/RefreshManagerDummy.h" +#include "DRAMSys/controller/refresh/RefreshManagerAllBank.h" +#include "DRAMSys/controller/refresh/RefreshManagerPerBank.h" +#include "DRAMSys/controller/refresh/RefreshManagerPer2Bank.h" +#include "DRAMSys/controller/refresh/RefreshManagerSameBank.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerStaggered.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerDummy.h" +#include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/common/dramExtensions.h" #ifdef DDR5_SIM -#include +#include "DRAMSys/controller/checker/CheckerDDR5.h" #endif #ifdef LPDDR5_SIM -#include +#include "DRAMSys/controller/checker/CheckerLPDDR5.h" #endif #ifdef HBM3_SIM -#include "checker/CheckerHBM3.h" +#include "DRAMSys/controller/checker/CheckerHBM3.h" #endif using namespace sc_core; diff --git a/src/libdramsys/DRAMSys/controller/Controller.h b/src/libdramsys/DRAMSys/controller/Controller.h index b51cfa3a..5154102e 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.h +++ b/src/libdramsys/DRAMSys/controller/Controller.h @@ -35,21 +35,20 @@ #ifndef CONTROLLER_H #define CONTROLLER_H +#include "DRAMSys/controller/ControllerIF.h" +#include "DRAMSys/controller/Command.h" +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" +#include "DRAMSys/controller/respqueue/RespQueueIF.h" +#include "DRAMSys/simulation/AddressDecoder.h" #include #include - #include #include -#include "ControllerIF.h" -#include "Command.h" -#include "BankMachine.h" -#include "cmdmux/CmdMuxIF.h" -#include "checker/CheckerIF.h" -#include "refresh/RefreshManagerIF.h" -#include "powerdown/PowerDownManagerIF.h" -#include "respqueue/RespQueueIF.h" -#include "../simulation/AddressDecoder.h" class Controller : public ControllerIF { @@ -93,12 +92,12 @@ private: struct Transaction { - tlm::tlm_generic_payload *payload = nullptr; + tlm::tlm_generic_payload* payload = nullptr; sc_core::sc_time time = sc_core::sc_max_time(); } transToAcquire, transToRelease; void manageResponses(); - void manageRequests(const sc_core::sc_time &delay); + void manageRequests(const sc_core::sc_time& delay); bool isFullCycle(const sc_core::sc_time& time) const; diff --git a/src/libdramsys/DRAMSys/controller/ControllerIF.h b/src/libdramsys/DRAMSys/controller/ControllerIF.h index 89283383..8a7f5ce0 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerIF.h +++ b/src/libdramsys/DRAMSys/controller/ControllerIF.h @@ -37,15 +37,15 @@ #ifndef CONTROLLERIF_H #define CONTROLLERIF_H -#include +#include "DRAMSys/configuration/Configuration.h" +#include #include #include #include #include -#include -// Utiliy class to pass around the DRAMSys, without having to propagate the template defintions +// Utility class to pass around DRAMSys, without having to propagate the template definitions // throughout all classes class ControllerIF : public sc_core::sc_module { diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index da6a0d0b..241913d2 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -33,13 +33,13 @@ */ #include "ControllerRecordable.h" -#include "../configuration/Configuration.h" -#include "scheduler/SchedulerIF.h" + +#include "DRAMSys/controller/scheduler/SchedulerIF.h" using namespace sc_core; using namespace tlm; -ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Configuration& config, +ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing), @@ -55,15 +55,15 @@ ControllerRecordable::ControllerRecordable(const sc_module_name &name, const Con } } -tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay) +tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, + tlm_phase& phase, sc_time& delay) { tlmRecorder.recordPhase(trans, phase, delay); return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &, - tlm_phase &, sc_time &) +tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload&, + tlm_phase&, sc_time&) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 8594fb23..125c188d 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -35,23 +35,24 @@ #ifndef CONTROLLERRECORDABLE_H #define CONTROLLERRECORDABLE_H +#include "DRAMSys/controller/Controller.h" +#include "DRAMSys/common/TlmRecorder.h" + #include #include -#include "Controller.h" -#include "../common/TlmRecorder.h" class ControllerRecordable final : public Controller { public: - ControllerRecordable(const sc_core::sc_module_name &name, const Configuration& config, + ControllerRecordable(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder); ~ControllerRecordable() override = default; protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, - sc_core::sc_time &delay) override; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, - sc_core::sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + sc_core::sc_time& delay) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + sc_core::sc_time& delay) override; void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp index 4743ceb4..10838df6 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerDDR3.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h index 41e2708b..8aa5372a 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h @@ -35,13 +35,13 @@ #ifndef CHECKERDDR3_H #define CHECKERDDR3_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecDDR3.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecDDR3.h" -#include "../../configuration/Configuration.h" - class CheckerDDR3 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp index a15b8dfa..8801d5b1 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerDDR4.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h index 4871c76c..2c603d7c 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h @@ -35,13 +35,13 @@ #ifndef CHECKERDDR4_H #define CHECKERDDR4_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecDDR4.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecDDR4.h" -#include "../../configuration/Configuration.h" - class CheckerDDR4 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp index 8ed0bf46..55b1ba8d 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerGDDR5.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h index 7384867b..3dd19f6b 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h @@ -35,13 +35,13 @@ #ifndef CHECKERGDDR5_H #define CHECKERGDDR5_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecGDDR5.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecGDDR5.h" -#include "../../configuration/Configuration.h" - class CheckerGDDR5 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp index beb43e2f..b8956d96 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerGDDR5X.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h index 06408ec6..771e4b60 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h @@ -35,13 +35,13 @@ #ifndef CHECKERGDDR5X_H #define CHECKERGDDR5X_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecGDDR5X.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecGDDR5X.h" -#include "../../configuration/Configuration.h" - class CheckerGDDR5X final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp index 681f251d..684de357 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerGDDR6.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h index a415cffe..281ab583 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h @@ -35,13 +35,13 @@ #ifndef CHECKERGDDR6_H #define CHECKERGDDR6_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecGDDR6.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecGDDR6.h" -#include "../../configuration/Configuration.h" - class CheckerGDDR6 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp index 76bd4650..120e2c23 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerHBM2.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h index bb83fb0b..50b7c527 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h @@ -35,13 +35,13 @@ #ifndef CHECKERHBM2_H #define CHECKERHBM2_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecHBM2.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecHBM2.h" -#include "../../configuration/Configuration.h" - class CheckerHBM2 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.cpp deleted file mode 100644 index 88fe561c..00000000 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.cpp +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) 2019, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Lukas Steiner - */ - -#include - -#include "CheckerHBM3.h" - -using namespace sc_core; -using namespace tlm; - -CheckerHBM3::CheckerHBM3(const Configuration &config) -{ - memSpec = dynamic_cast(config.memSpec.get()); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerHBM3", "Wrong MemSpec chosen"); - - lastScheduledByCommandAndBank = std::vector>( - Command::numberOfCommands(), std::vector(memSpec->banksPerChannel, sc_max_time())); - lastScheduledByCommandAndBankGroup = std::vector>( - Command::numberOfCommands(), std::vector(memSpec->bankGroupsPerChannel, sc_max_time())); - lastScheduledByCommandAndRank = std::vector>( - Command::numberOfCommands(), std::vector(memSpec->ranksPerChannel, sc_max_time())); - lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); - lastCommandOnRasBus = sc_max_time(); - lastCommandOnCasBus = sc_max_time(); - last4Activates = std::vector>(memSpec->ranksPerChannel); - - bankwiseRefreshCounter = std::vector(memSpec->ranksPerChannel); - - tRDPDE = memSpec->tRL + memSpec->tPL + 2 * memSpec->tCK; - tRDSRE = memSpec->tRL + memSpec->tPL + 3 * memSpec->tCK; - tWRPRE = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWR; - tWRPDE = memSpec->tWL + memSpec->tPL + 3 * memSpec->tCK + memSpec->tWR; - tWRAPDE = memSpec->tWL + memSpec->tPL + 3 * memSpec->tCK + memSpec->tWR; - tWRRDS = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWTRS; - tWRRDL = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWTRL; -} - -sc_time CheckerHBM3::timeToSatisfyConstraints(Command command, const tlm_generic_payload &payload) const -{ - Rank rank = ControllerExtension::getRank(payload); - BankGroup bankGroup = ControllerExtension::getBankGroup(payload); - Bank bank = ControllerExtension::getBank(payload); - - sc_time lastCommandStart; - sc_time earliestTimeToStart = sc_time_stamp(); - - if (command == Command::PREPB) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK / 2); - } - else if (command == Command::RD) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); - } - else if (command == Command::WR) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); - } - else if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + 2 * memSpec->tCK + - std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); - } - else if (command == Command::WRA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); - } - else if (command == Command::ACT) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); - - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = - std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = - std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS - memSpec->tCK); - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = - std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::REFAB) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PREAB) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK / 2); - } - else if (command == Command::REFPB) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - { - if (bankwiseRefreshCounter[rank.ID()] == 0) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - } - - if (last4Activates[rank.ID()].size() >= 4) - earliestTimeToStart = - std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::SREFEN) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = - std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE)); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::RFMAB) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::RFMAB) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDEA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDEP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); - - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDXP) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::PDXA) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else if (command == Command::SREFEX) - { - lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; - if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); - } - else - { - SC_REPORT_FATAL("CheckerHBM3", "Unknown command!"); - } - - // Don't issue commands at half cycles. - if (command != Command::PREAB && command != Command::PREPB && !isFullCycle(earliestTimeToStart)) - earliestTimeToStart += memSpec->tCK / 2; - - return earliestTimeToStart; -} - -void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload) -{ - Rank rank = ControllerExtension::getRank(payload); - BankGroup bankGroup = ControllerExtension::getBankGroup(payload); - Bank bank = ControllerExtension::getBank(payload); - - PRINTDEBUGMESSAGE("CheckerHBM3", - "Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString()); - - lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); - lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); - lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); - lastScheduledByCommand[command] = sc_time_stamp(); - - if (command.isCasCommand()) - lastCommandOnCasBus = sc_time_stamp(); - else if (command == Command::ACT) - lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK; - else - lastCommandOnRasBus = sc_time_stamp(); - - if (command == Command::ACT || command == Command::REFPB) - { - if (last4Activates[rank.ID()].size() == 4) - last4Activates[rank.ID()].pop(); - last4Activates[rank.ID()].push(lastCommandOnRasBus); - } - - if (command == Command::REFPB) - bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; -} - -bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const -{ - sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK; - return sc_time::from_value(aligedAtHalfCycle.value() % memSpec->tCK.value()) == SC_ZERO_TIME; -} diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.h b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.h deleted file mode 100644 index 8bd4423d..00000000 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM3.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2019, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Lukas Steiner - */ - -#ifndef CHECKERHBM3_H -#define CHECKERHBM3_H - -#include -#include - -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecHBM3.h" -#include "../../configuration/Configuration.h" - -class CheckerHBM3 final : public CheckerIF -{ -public: - explicit CheckerHBM3(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; - void insert(Command command, const tlm::tlm_generic_payload& payload) override; - -private: - bool isFullCycle(const sc_core::sc_time& time) const; - - const MemSpecHBM3 *memSpec; - - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - - sc_core::sc_time lastCommandOnRasBus; - sc_core::sc_time lastCommandOnCasBus; - - // Four activate window - std::vector> last4Activates; - std::vector bankwiseRefreshCounter; - - sc_core::sc_time tRDPDE; - sc_core::sc_time tRDSRE; - sc_core::sc_time tWRPRE; - sc_core::sc_time tWRPDE; - sc_core::sc_time tWRAPDE; - sc_core::sc_time tWRRDS; - sc_core::sc_time tWRRDL; -}; - -#endif // CHECKERHBM3_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h index 994a0243..773a3d0e 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h @@ -35,9 +35,9 @@ #ifndef CHECKERIF_H #define CHECKERIF_H -#include +#include "DRAMSys/controller/Command.h" -#include "../Command.h" +#include class CheckerIF { diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp index 8f0d6622..f417d870 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerLPDDR4.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h index 5f39c3f8..b01f1699 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h @@ -35,13 +35,13 @@ #ifndef CHECKERLPDDR4_H #define CHECKERLPDDR4_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecLPDDR4.h" -#include "../../configuration/Configuration.h" - class CheckerLPDDR4 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp index 887c59a3..3b38d746 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerSTTMRAM.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h index 4a1498f2..212bacf3 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h @@ -35,13 +35,13 @@ #ifndef CHECKERSTTMRAM_H #define CHECKERSTTMRAM_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecSTTMRAM.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecSTTMRAM.h" -#include "../../configuration/Configuration.h" - class CheckerSTTMRAM final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp index 76c0abbb..281f1b79 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerWideIO.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h index eea2a9d5..a525ea35 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h @@ -35,13 +35,13 @@ #ifndef CHECKERWIDEIO_H #define CHECKERWIDEIO_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecWideIO.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecWideIO.h" -#include "../../configuration/Configuration.h" - class CheckerWideIO final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp index ca42f0fd..3cfc58b2 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp @@ -32,10 +32,10 @@ * Author: Lukas Steiner */ -#include - #include "CheckerWideIO2.h" +#include + using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h index 8c08a9e5..ef102ea6 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h @@ -35,13 +35,13 @@ #ifndef CHECKERWIDEIO2_H #define CHECKERWIDEIO2_H +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpecWideIO2.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include -#include "CheckerIF.h" -#include "../../configuration/memspec/MemSpecWideIO2.h" -#include "../../configuration/Configuration.h" - class CheckerWideIO2 final : public CheckerIF { public: diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index 006c4e5d..f286f0de 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -35,7 +35,7 @@ #ifndef CMDMUXIF_H #define CMDMUXIF_H -#include "../Command.h" +#include "DRAMSys/controller/Command.h" class CmdMuxIF { diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index 151b34dc..6ebbe109 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -32,9 +32,9 @@ * Author: Lukas Steiner */ -#include #include "CmdMuxOldest.h" -#include "../../common/dramExtensions.h" + +#include using namespace sc_core; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index 196b5242..3df42450 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -35,8 +35,8 @@ #ifndef CMDMUXOLDEST_H #define CMDMUXOLDEST_H -#include "CmdMuxIF.h" -#include "../../configuration/Configuration.h" +#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" +#include "DRAMSys/configuration/Configuration.h" class CmdMuxOldest : public CmdMuxIF { diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index 9f3dd176..89777c0e 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -32,9 +32,9 @@ * Author: Lukas Steiner */ -#include #include "CmdMuxStrict.h" -#include "../../common/dramExtensions.h" + +#include using namespace sc_core; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index cf806e39..da384d5d 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -35,8 +35,8 @@ #ifndef CMDMUXSTRICT_H #define CMDMUXSTRICT_H -#include "CmdMuxIF.h" -#include "../../configuration/Configuration.h" +#include "DRAMSys/controller/cmdmux/CmdMuxIF.h" +#include "DRAMSys/configuration/Configuration.h" class CmdMuxStrict : public CmdMuxIF { diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp index f81c8d45..120f9e39 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp @@ -32,7 +32,6 @@ * Author: Lukas Steiner */ -#include "../Command.h" #include "PowerDownManagerDummy.h" using namespace sc_core; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h index d28aa011..35e5e461 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h @@ -35,7 +35,7 @@ #ifndef POWERDOWNMANAGERDUMMY_H #define POWERDOWNMANAGERDUMMY_H -#include "PowerDownManagerIF.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" class PowerDownManagerDummy final : public PowerDownManagerIF { diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h index 5e2fa4ba..c4d08e92 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h @@ -35,8 +35,9 @@ #ifndef POWERDOWNMANAGERIF_H #define POWERDOWNMANAGERIF_H +#include "DRAMSys/controller/Command.h" + #include -#include "../Command.h" class PowerDownManagerIF { diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index 72db9e14..16da02d8 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -33,8 +33,8 @@ */ #include "PowerDownManagerStaggered.h" -#include "../BankMachine.h" -#include "../../common/utils.h" + +#include "DRAMSys/controller/BankMachine.h" using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index faf474a3..2fcce6da 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -35,10 +35,11 @@ #ifndef POWERDOWNMANAGERSTAGGERED_H #define POWERDOWNMANAGERSTAGGERED_H +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/controller/checker/CheckerIF.h" + #include -#include "PowerDownManagerIF.h" -#include "../../common/dramExtensions.h" -#include "../checker/CheckerIF.h" class BankMachine; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index 06199c2f..f51fd319 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -34,11 +34,9 @@ */ #include "RefreshManagerAllBank.h" -#include "../BankMachine.h" -#include "../powerdown/PowerDownManagerIF.h" -#include "../../common/dramExtensions.h" -#include "../../configuration/Configuration.h" -#include "../../common/utils.h" + +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index 321e0d82..92ee1a00 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -35,14 +35,14 @@ #ifndef REFRESHMANAGERALLBANK_H #define REFRESHMANAGERALLBANK_H -#include +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include #include #include -#include "RefreshManagerIF.h" -#include "../checker/CheckerIF.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpec.h" class BankMachine; class PowerDownManagerIF; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 05d127e7..8fa857c0 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -35,8 +35,9 @@ #ifndef REFRESHMANAGERDUMMY_H #define REFRESHMANAGERDUMMY_H +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" + #include -#include "RefreshManagerIF.h" class RefreshManagerDummy final : public RefreshManagerIF { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h index 8e281fdb..2a9eea72 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h @@ -35,11 +35,12 @@ #ifndef REFRESHMANAGERIF_H #define REFRESHMANAGERIF_H -#include +#include "DRAMSys/controller/Command.h" +#include "DRAMSys/configuration/Configuration.h" + +#include #include -#include "../Command.h" -#include "../../configuration/Configuration.h" class RefreshManagerIF { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index aaf27e04..98d555b3 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -33,11 +33,9 @@ */ #include "RefreshManagerPer2Bank.h" -#include "../BankMachine.h" -#include "../powerdown/PowerDownManagerIF.h" -#include "../../configuration/Configuration.h" -#include "../../common/utils.h" -#include "../../common/dramExtensions.h" + +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index 5ced622a..cf188ebf 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -35,16 +35,16 @@ #ifndef REFRESHMANAGERPER2BANK_H #define REFRESHMANAGERPER2BANK_H +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include #include - #include #include -#include "RefreshManagerIF.h" -#include "../checker/CheckerIF.h" -#include "../../configuration/memspec/MemSpec.h" -#include "../../configuration/Configuration.h" class BankMachine; class PowerDownManagerIF; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 33d8da8a..6107e746 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -33,11 +33,9 @@ */ #include "RefreshManagerPerBank.h" -#include "../BankMachine.h" -#include "../powerdown/PowerDownManagerIF.h" -#include "../../configuration/Configuration.h" -#include "../../common/utils.h" -#include "../../common/dramExtensions.h" + +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index b642398f..98ad4634 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -35,16 +35,16 @@ #ifndef REFRESHMANAGERPERBANK_H #define REFRESHMANAGERPERBANK_H +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include #include - #include #include -#include "RefreshManagerIF.h" -#include "../checker/CheckerIF.h" -#include "../../configuration/memspec/MemSpec.h" -#include "../../configuration/Configuration.h" class BankMachine; class PowerDownManagerIF; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 989881cb..8b99f2bb 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -33,11 +33,9 @@ */ #include "RefreshManagerSameBank.h" -#include "../BankMachine.h" -#include "../powerdown/PowerDownManagerIF.h" -#include "../../configuration/Configuration.h" -#include "../../common/utils.h" -#include "../../common/dramExtensions.h" + +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" using namespace sc_core; using namespace tlm; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index b914ff38..00c790e3 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -35,15 +35,15 @@ #ifndef REFRESHMANAGERSAMEBANK_H #define REFRESHMANAGERSAMEBANK_H +#include "DRAMSys/controller/refresh/RefreshManagerIF.h" +#include "DRAMSys/controller/checker/CheckerIF.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include - #include #include -#include "RefreshManagerIF.h" -#include "../checker/CheckerIF.h" -#include "../../configuration/memspec/MemSpec.h" -#include "../../configuration/Configuration.h" class BankMachine; class PowerDownManagerIF; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp index 825efd13..2186a70f 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp @@ -37,16 +37,16 @@ using namespace sc_core; using namespace tlm; -void RespQueueFifo::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) +void RespQueueFifo::insertPayload(tlm_generic_payload* payload, sc_time strobeEnd) { - buffer.push({payload, strobeEnd}); + buffer.emplace(payload, strobeEnd); } -tlm_generic_payload *RespQueueFifo::nextPayload() +tlm_generic_payload* RespQueueFifo::nextPayload() { if (!buffer.empty()) { - std::pair element = buffer.front(); + std::pair element = buffer.front(); if (element.second <= sc_time_stamp()) { buffer.pop(); diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index 7c611d45..6b96b972 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -35,22 +35,22 @@ #ifndef RESPQUEUEFIFO_H #define RESPQUEUEFIFO_H +#include "DRAMSys/controller/respqueue/RespQueueIF.h" + #include #include - #include #include -#include "RespQueueIF.h" class RespQueueFifo final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override; - tlm::tlm_generic_payload *nextPayload() override; - sc_core::sc_time getTriggerTime() const override; + void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override; + tlm::tlm_generic_payload* nextPayload() override; + [[nodiscard]] sc_core::sc_time getTriggerTime() const override; private: - std::queue> buffer; + std::queue> buffer; }; #endif // RESPQUEUEFIFO_H diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index 9f566a78..f9119ae1 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -41,9 +41,9 @@ class RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) = 0; - virtual tlm::tlm_generic_payload *nextPayload() = 0; - virtual sc_core::sc_time getTriggerTime() const = 0; + virtual void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) = 0; + virtual tlm::tlm_generic_payload* nextPayload() = 0; + [[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0; virtual ~RespQueueIF() = default; }; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp index 2ce372ad..117c5635 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp @@ -33,23 +33,24 @@ */ #include "RespQueueReorder.h" -#include "../../common/dramExtensions.h" + +#include "DRAMSys/common/dramExtensions.h" using namespace sc_core; using namespace tlm; -void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) +void RespQueueReorder::insertPayload(tlm_generic_payload* payload, sc_time strobeEnd) { buffer[ControllerExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; } -tlm_generic_payload *RespQueueReorder::nextPayload() +tlm_generic_payload* RespQueueReorder::nextPayload() { if (!buffer.empty()) { if (buffer.begin()->first == nextPayloadID) { - std::pair element = buffer.begin()->second; + std::pair element = buffer.begin()->second; if (element.second <= sc_time_stamp()) { buffer.erase(nextPayloadID++); diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h index f236affe..2f3b5fdf 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h @@ -35,22 +35,22 @@ #ifndef RESPQUEUEREORDER_H #define RESPQUEUEREORDER_H -#include +#include "DRAMSys/controller/respqueue/RespQueueIF.h" +#include #include #include -#include "RespQueueIF.h" class RespQueueReorder final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override; - tlm::tlm_generic_payload *nextPayload() override; - sc_core::sc_time getTriggerTime() const override; + void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override; + tlm::tlm_generic_payload* nextPayload() override; + [[nodiscard]] sc_core::sc_time getTriggerTime() const override; private: uint64_t nextPayloadID = 1; - std::map> buffer; + std::map> buffer; }; #endif // RESPQUEUEREORDER_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp index d31db7e6..423ccfb1 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp @@ -33,7 +33,8 @@ */ #include "BufferCounterBankwise.h" -#include "../../common/dramExtensions.h" + +#include "DRAMSys/common/dramExtensions.h" using namespace tlm; @@ -67,7 +68,7 @@ void BufferCounterBankwise::removeRequest(const tlm_generic_payload& trans) numWriteRequests--; } -const std::vector &BufferCounterBankwise::getBufferDepth() const +const std::vector& BufferCounterBankwise::getBufferDepth() const { return numRequestsOnBank; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h index f970a697..4b70a819 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h @@ -35,21 +35,21 @@ #ifndef BUFFERCOUNTERBANKWISE_H #define BUFFERCOUNTERBANKWISE_H -#include +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include #include -#include "BufferCounterIF.h" class BufferCounterBankwise final : public BufferCounterIF { public: BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(const tlm::tlm_generic_payload& trans) override; void removeRequest(const tlm::tlm_generic_payload& trans) override; - const std::vector &getBufferDepth() const override; - unsigned getNumReadRequests() const override; - unsigned getNumWriteRequests() const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; + [[nodiscard]] unsigned getNumReadRequests() const override; + [[nodiscard]] unsigned getNumWriteRequests() const override; private: const unsigned requestBufferSize; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h index 87936fbf..237cb9ea 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h @@ -36,19 +36,18 @@ #define BUFFERCOUNTERIF_H #include - #include class BufferCounterIF { public: virtual ~BufferCounterIF() = default; - virtual bool hasBufferSpace() const = 0; + [[nodiscard]] virtual bool hasBufferSpace() const = 0; virtual void storeRequest(const tlm::tlm_generic_payload& trans) = 0; virtual void removeRequest(const tlm::tlm_generic_payload& trans) = 0; - virtual const std::vector &getBufferDepth() const = 0; - virtual unsigned getNumReadRequests() const = 0; - virtual unsigned getNumWriteRequests() const = 0; + [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; + [[nodiscard]] virtual unsigned getNumReadRequests() const = 0; + [[nodiscard]] virtual unsigned getNumWriteRequests() const = 0; }; #endif // BUFFERCOUNTERIF_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp index fae82ad5..b794560c 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp @@ -63,7 +63,7 @@ void BufferCounterReadWrite::removeRequest(const tlm_generic_payload& trans) numReadWriteRequests[1]--; } -const std::vector &BufferCounterReadWrite::getBufferDepth() const +const std::vector& BufferCounterReadWrite::getBufferDepth() const { return numReadWriteRequests; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h index fb330499..9ea6a971 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h @@ -35,21 +35,21 @@ #ifndef BUFFERCOUNTERREADWRITE_H #define BUFFERCOUNTERREADWRITE_H -#include +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include #include -#include "BufferCounterIF.h" class BufferCounterReadWrite final : public BufferCounterIF { public: explicit BufferCounterReadWrite(unsigned requestBufferSize); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(const tlm::tlm_generic_payload& trans) override; void removeRequest(const tlm::tlm_generic_payload& trans) override; - const std::vector &getBufferDepth() const override; - unsigned getNumReadRequests() const override; - unsigned getNumWriteRequests() const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; + [[nodiscard]] unsigned getNumReadRequests() const override; + [[nodiscard]] unsigned getNumWriteRequests() const override; private: const unsigned requestBufferSize; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp index 7008d899..ae37069a 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp @@ -65,7 +65,7 @@ void BufferCounterShared::removeRequest(const tlm_generic_payload& trans) numWriteRequests--; } -const std::vector &BufferCounterShared::getBufferDepth() const +const std::vector& BufferCounterShared::getBufferDepth() const { return numRequests; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h index 31277f6a..3c2880e3 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h @@ -35,21 +35,21 @@ #ifndef BUFFERCOUNTERSHARED_H #define BUFFERCOUNTERSHARED_H -#include +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include #include -#include "BufferCounterIF.h" class BufferCounterShared final : public BufferCounterIF { public: explicit BufferCounterShared(unsigned requestBufferSize); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(const tlm::tlm_generic_payload& trans) override; void removeRequest(const tlm::tlm_generic_payload& trans) override; - const std::vector &getBufferDepth() const override; - unsigned getNumReadRequests() const override; - unsigned getNumWriteRequests() const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; + [[nodiscard]] unsigned getNumReadRequests() const override; + [[nodiscard]] unsigned getNumWriteRequests() const override; private: const unsigned requestBufferSize; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 9e1f9ede..455f0507 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -33,16 +33,16 @@ */ #include "SchedulerFifo.h" -#include "../../configuration/Configuration.h" -#include "BufferCounterBankwise.h" -#include "BufferCounterReadWrite.h" -#include "BufferCounterShared.h" + +#include "DRAMSys/controller/scheduler/BufferCounterBankwise.h" +#include "DRAMSys/controller/scheduler/BufferCounterReadWrite.h" +#include "DRAMSys/controller/scheduler/BufferCounterShared.h" using namespace tlm; SchedulerFifo::SchedulerFifo(const Configuration& config) { - buffer = std::vector>(config.memSpec->banksPerChannel); + buffer = std::vector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); @@ -69,7 +69,7 @@ void SchedulerFifo::removeRequest(tlm_generic_payload& payload) bufferCounter->removeRequest(payload); } -tlm_generic_payload *SchedulerFifo::getNextRequest(const BankMachine& bankMachine) const +tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachine) const { unsigned bankID = bankMachine.getBank().ID(); if (!buffer[bankID].empty()) @@ -97,7 +97,7 @@ bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const return false; } -const std::vector &SchedulerFifo::getBufferDepth() const +const std::vector& SchedulerFifo::getBufferDepth() const { return bufferCounter->getBufferDepth(); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index 154cddde..f6dc34f7 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -35,30 +35,30 @@ #ifndef SCHEDULERFIFO_H #define SCHEDULERFIFO_H +#include "DRAMSys/controller/scheduler/SchedulerIF.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" + #include #include #include - #include -#include "SchedulerIF.h" -#include "../../common/dramExtensions.h" -#include "../BankMachine.h" -#include "BufferCounterIF.h" class SchedulerFifo final : public SchedulerIF { public: explicit SchedulerFifo(const Configuration& config); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload&) override; void removeRequest(tlm::tlm_generic_payload&) override; - tlm::tlm_generic_payload *getNextRequest(const BankMachine&) const override; - bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - bool hasFurtherRequest(Bank, tlm::tlm_command) const override; - const std::vector &getBufferDepth() const override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; private: - std::vector> buffer; + std::vector> buffer; std::unique_ptr bufferCounter; }; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index dffdd224..076d8708 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -33,16 +33,16 @@ */ #include "SchedulerFrFcfs.h" -#include "../../configuration/Configuration.h" -#include "BufferCounterBankwise.h" -#include "BufferCounterReadWrite.h" -#include "BufferCounterShared.h" + +#include "DRAMSys/controller/scheduler/BufferCounterBankwise.h" +#include "DRAMSys/controller/scheduler/BufferCounterReadWrite.h" +#include "DRAMSys/controller/scheduler/BufferCounterShared.h" using namespace tlm; SchedulerFrFcfs::SchedulerFrFcfs(const Configuration& config) { - buffer = std::vector>(config.memSpec->banksPerChannel); + buffer = std::vector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); @@ -77,7 +77,7 @@ void SchedulerFrFcfs::removeRequest(tlm_generic_payload& trans) } } -tlm_generic_payload *SchedulerFrFcfs::getNextRequest(const BankMachine& bankMachine) const +tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMachine) const { unsigned bankID = bankMachine.getBank().ID(); if (!buffer[bankID].empty()) @@ -118,7 +118,7 @@ bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const return (buffer[bank.ID()].size() >= 2); } -const std::vector &SchedulerFrFcfs::getBufferDepth() const +const std::vector& SchedulerFrFcfs::getBufferDepth() const { return bufferCounter->getBufferDepth(); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index df7196cc..2526e890 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -35,30 +35,30 @@ #ifndef SCHEDULERFRFCFS_H #define SCHEDULERFRFCFS_H +#include "DRAMSys/controller/scheduler/SchedulerIF.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" + #include #include #include - #include -#include "SchedulerIF.h" -#include "../../common/dramExtensions.h" -#include "../BankMachine.h" -#include "BufferCounterIF.h" class SchedulerFrFcfs final : public SchedulerIF { public: explicit SchedulerFrFcfs(const Configuration& config); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload&) override; void removeRequest(tlm::tlm_generic_payload&) override; - tlm::tlm_generic_payload *getNextRequest(const BankMachine&) const override; - bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - bool hasFurtherRequest(Bank, tlm::tlm_command) const override; - const std::vector &getBufferDepth() const override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; private: - std::vector> buffer; + std::vector> buffer; std::unique_ptr bufferCounter; }; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index 5d3a2b8e..bb6bc990 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -33,16 +33,16 @@ */ #include "SchedulerFrFcfsGrp.h" -#include "../../configuration/Configuration.h" -#include "BufferCounterBankwise.h" -#include "BufferCounterReadWrite.h" -#include "BufferCounterShared.h" + +#include "DRAMSys/controller/scheduler/BufferCounterBankwise.h" +#include "DRAMSys/controller/scheduler/BufferCounterReadWrite.h" +#include "DRAMSys/controller/scheduler/BufferCounterShared.h" using namespace tlm; SchedulerFrFcfsGrp::SchedulerFrFcfsGrp(const Configuration& config) { - buffer = std::vector>(config.memSpec->banksPerChannel); + buffer = std::vector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); @@ -78,7 +78,7 @@ void SchedulerFrFcfsGrp::removeRequest(tlm_generic_payload& trans) } } -tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankMachine) const +tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankMachine) const { unsigned bankID = bankMachine.getBank().ID(); if (!buffer[bankID].empty()) @@ -146,7 +146,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const return false; } -const std::vector &SchedulerFrFcfsGrp::getBufferDepth() const +const std::vector& SchedulerFrFcfsGrp::getBufferDepth() const { return bufferCounter->getBufferDepth(); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index d10e5bf0..5b130188 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -35,27 +35,27 @@ #ifndef SCHEDULERFRFCFSGRP_H #define SCHEDULERFRFCFSGRP_H +#include "DRAMSys/controller/scheduler/SchedulerIF.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" + #include #include #include - #include -#include "SchedulerIF.h" -#include "../../common/dramExtensions.h" -#include "../BankMachine.h" -#include "BufferCounterIF.h" class SchedulerFrFcfsGrp final : public SchedulerIF { public: explicit SchedulerFrFcfsGrp(const Configuration& config); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload&) override; void removeRequest(tlm::tlm_generic_payload&) override; - tlm::tlm_generic_payload *getNextRequest(const BankMachine&) const override; - bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - bool hasFurtherRequest(Bank, tlm::tlm_command) const override; - const std::vector &getBufferDepth() const override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; private: std::vector> buffer; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 35b7fa48..cbc8b694 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -33,17 +33,17 @@ */ #include "SchedulerGrpFrFcfs.h" -#include "../../configuration/Configuration.h" -#include "BufferCounterBankwise.h" -#include "BufferCounterReadWrite.h" -#include "BufferCounterShared.h" + +#include "DRAMSys/controller/scheduler/BufferCounterBankwise.h" +#include "DRAMSys/controller/scheduler/BufferCounterReadWrite.h" +#include "DRAMSys/controller/scheduler/BufferCounterShared.h" using namespace tlm; SchedulerGrpFrFcfs::SchedulerGrpFrFcfs(const Configuration& config) { - readBuffer = std::vector>(config.memSpec->banksPerChannel); - writeBuffer = std::vector>(config.memSpec->banksPerChannel); + readBuffer = std::vector>(config.memSpec->banksPerChannel); + writeBuffer = std::vector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); @@ -81,7 +81,7 @@ void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& trans) writeBuffer[bankID].remove(&trans); } -tlm_generic_payload *SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankMachine) const +tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankMachine) const { // search row hits, search wrd/wr hits // search rd/wr hits, search row hits @@ -209,7 +209,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const } } -const std::vector &SchedulerGrpFrFcfs::getBufferDepth() const +const std::vector& SchedulerGrpFrFcfs::getBufferDepth() const { return bufferCounter->getBufferDepth(); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index 47a82916..9078915e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -35,31 +35,31 @@ #ifndef SCHEDULERGRPFRFCFS_H #define SCHEDULERGRPFRFCFS_H +#include "DRAMSys/controller/scheduler/SchedulerIF.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" + #include #include #include - #include -#include "SchedulerIF.h" -#include "../../common/dramExtensions.h" -#include "../BankMachine.h" -#include "BufferCounterIF.h" class SchedulerGrpFrFcfs final : public SchedulerIF { public: explicit SchedulerGrpFrFcfs(const Configuration& config); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload&) override; void removeRequest(tlm::tlm_generic_payload&) override; - tlm::tlm_generic_payload *getNextRequest(const BankMachine&) const override; - bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - bool hasFurtherRequest(Bank, tlm::tlm_command) const override; - const std::vector &getBufferDepth() const override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; private: - std::vector> readBuffer; - std::vector> writeBuffer; + std::vector> readBuffer; + std::vector> writeBuffer; tlm::tlm_command lastCommand = tlm::TLM_READ_COMMAND; std::unique_ptr bufferCounter; }; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index 6a4a8971..32be6603 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -33,18 +33,18 @@ */ #include "SchedulerGrpFrFcfsWm.h" -#include "../../configuration/Configuration.h" -#include "BufferCounterBankwise.h" -#include "BufferCounterReadWrite.h" -#include "BufferCounterShared.h" + +#include "DRAMSys/controller/scheduler/BufferCounterBankwise.h" +#include "DRAMSys/controller/scheduler/BufferCounterReadWrite.h" +#include "DRAMSys/controller/scheduler/BufferCounterShared.h" using namespace tlm; SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) - :lowWatermark(config.lowWatermark), highWatermark(config.highWatermark) + : lowWatermark(config.lowWatermark), highWatermark(config.highWatermark) { - readBuffer = std::vector>(config.memSpec->banksPerChannel); - writeBuffer = std::vector>(config.memSpec->banksPerChannel); + readBuffer = std::vector>(config.memSpec->banksPerChannel); + writeBuffer = std::vector>(config.memSpec->banksPerChannel); if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise) bufferCounter = std::make_unique(config.requestBufferSize, config.memSpec->banksPerChannel); @@ -53,7 +53,7 @@ SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared) bufferCounter = std::make_unique(config.requestBufferSize); - if (lowWatermark == 0 || highWatermark == 0 || lowWatermark == highWatermark) + if (lowWatermark == 0 || lowWatermark >= highWatermark) SC_REPORT_FATAL("SchedulerGrpFrFcfsWm", "Invalid watermark configuration."); SC_REPORT_WARNING("SchedulerGrpFrFcfsWm", "Hazard detection not yet implemented!"); @@ -87,7 +87,7 @@ void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& trans) evaluateWriteMode(); } -tlm_generic_payload *SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& bankMachine) const +tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& bankMachine) const { unsigned bankID = bankMachine.getBank().ID(); @@ -172,7 +172,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command return (writeBuffer[bank.ID()].size() >= 2); } -const std::vector &SchedulerGrpFrFcfsWm::getBufferDepth() const +const std::vector& SchedulerGrpFrFcfsWm::getBufferDepth() const { return bufferCounter->getBufferDepth(); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index 38f8b7f6..9e3932f2 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -35,28 +35,28 @@ #ifndef SCHEDULERGRPFRFCFSWM_H #define SCHEDULERGRPFRFCFSWM_H +#include "DRAMSys/controller/scheduler/SchedulerIF.h" +#include "DRAMSys/common/dramExtensions.h" +#include "DRAMSys/controller/BankMachine.h" +#include "DRAMSys/controller/scheduler/BufferCounterIF.h" +#include "DRAMSys/configuration/Configuration.h" + #include #include #include - #include -#include "SchedulerIF.h" -#include "../../common/dramExtensions.h" -#include "../BankMachine.h" -#include "BufferCounterIF.h" -#include "../../configuration/Configuration.h" class SchedulerGrpFrFcfsWm final : public SchedulerIF { public: explicit SchedulerGrpFrFcfsWm(const Configuration& config); - bool hasBufferSpace() const override; + [[nodiscard]] bool hasBufferSpace() const override; void storeRequest(tlm::tlm_generic_payload&) override; void removeRequest(tlm::tlm_generic_payload&) override; - tlm::tlm_generic_payload *getNextRequest(const BankMachine&) const override; - bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - bool hasFurtherRequest(Bank, tlm::tlm_command) const override; - const std::vector &getBufferDepth() const override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + [[nodiscard]] const std::vector& getBufferDepth() const override; private: void evaluateWriteMode(); diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index 3b45a0db..87a3c7b6 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -35,10 +35,10 @@ #ifndef SCHEDULERIF_H #define SCHEDULERIF_H -#include +#include "DRAMSys/common/dramExtensions.h" +#include #include -#include "../../common/dramExtensions.h" class BankMachine; @@ -46,13 +46,13 @@ class SchedulerIF { public: virtual ~SchedulerIF() = default; - virtual bool hasBufferSpace() const = 0; + [[nodiscard]] virtual bool hasBufferSpace() const = 0; virtual void storeRequest(tlm::tlm_generic_payload&) = 0; virtual void removeRequest(tlm::tlm_generic_payload&) = 0; - virtual tlm::tlm_generic_payload *getNextRequest(const BankMachine&) const = 0; - virtual bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const = 0; - virtual bool hasFurtherRequest(Bank, tlm::tlm_command) const = 0; - virtual const std::vector &getBufferDepth() const = 0; + [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const = 0; + [[nodiscard]] virtual bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const = 0; + [[nodiscard]] virtual bool hasFurtherRequest(Bank, tlm::tlm_command) const = 0; + [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; #endif // SCHEDULERIF_H diff --git a/src/libdramsys/DRAMSys/error/ECC/Bit.cpp b/src/libdramsys/DRAMSys/error/ECC/Bit.cpp deleted file mode 100644 index ee012016..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/Bit.cpp +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#include "Bit.h" - -#include - -using std::cout; - -CBit::CBit(VALUE nVal) -{ - m_nValue = nVal; -} - - -CBit::~CBit() -{ -} - -void CBit::Print() -{ - if (m_nValue == ZERO) { - cout << "0"; - } else { - cout << "1"; - } -} diff --git a/src/libdramsys/DRAMSys/error/ECC/Bit.h b/src/libdramsys/DRAMSys/error/ECC/Bit.h deleted file mode 100644 index 5e4b6779..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/Bit.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#pragma once -class CBit -{ -public: - enum VALUE { - ZERO = 0, - ONE = 1 - }; - -protected: - VALUE m_nValue; - -public: - CBit(VALUE nVal = ZERO); - virtual ~CBit(); - - inline void Set() - { - m_nValue = ONE; - }; - inline void Clear() - { - m_nValue = ZERO; - }; - inline unsigned Get() - { - if (m_nValue == ONE) - return 1; - else - return 0; - }; - - void Print(); - - CBit &operator=(unsigned d) - { - if (d == 0 ) { - m_nValue = ZERO; - } else { - m_nValue = ONE; - } - return *this; - } - - friend CBit operator^(CBit l, const CBit &r) - { - if (l.m_nValue == r.m_nValue) { - return CBit(ZERO); - } else { - return CBit(ONE); - } - } - - CBit &operator^=(const CBit &r) - { - if (m_nValue == r.m_nValue) { - m_nValue = ZERO; - } else { - m_nValue = ONE; - } - return *this; - } - - inline bool operator==(const CBit::VALUE &r) - { - return m_nValue == r; - } -}; - diff --git a/src/libdramsys/DRAMSys/error/ECC/ECC.cpp b/src/libdramsys/DRAMSys/error/ECC/ECC.cpp deleted file mode 100644 index fba2c953..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/ECC.cpp +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#include "ECC.h" - -// ************************************************************************************************ -// Function which calculates the number of additional bits needed for a given number of data bits -// to store the hamming code and parity bit for a SECDED implementation -unsigned ECC::GetNumParityBits(unsigned nDataBits) -{ - unsigned nParityBits = 0; - - // Function to calculate the nube of bits: n = 2^k - k - 1 - // ( Source: Hacker's Delight; p. 310; math. function 1 ) - while (nDataBits > ((1 << nParityBits) - nParityBits - 1)) { - ++nParityBits; - } - - return nParityBits + 1; // +1 for the parity bit -} - - -// ************************************************************************************************ -// Function which extends a given data word to the needed length for a SECDED code -void ECC::ExtendWord(CWord &v) -{ - unsigned end = v.GetLength() + ECC::GetNumParityBits(v.GetLength()); - - // Insert x bits for the hamming code at positions where pos = 2^a; a = [0..N] - // In "Hacker's Delight" the smallest index is 1 - But in this beautiful C-Code it's 0 as it - // should be. That's why there is a '-1' in the call of v.Insert. - unsigned i = 1; - while (i < end) { - v.Insert(i - 1, CBit()); - i <<= 1; - } - - // Append one bit for the parity - v.Append(CBit()); -} - -// ************************************************************************************************ -// Function which calculates the Hamming Code bits of an extended Data word. -// Function ExtendWord must be called before calling this function -// The calculated bits are stored in p, so the length of p should be at least -// 'GetNumParityBits(#data bits)-1' -void ECC::CalculateCheckbits(CWord &v, CWord &p) -{ - unsigned i = 1, l = 0; - - // Last bit is the parity bit - don't use this in the algorithm for hamming code - unsigned len = v.GetLength() - 1; - - // Following Graph should show you the behaviour of this algorithm - // #Data bits: 11 #Hamming bits: 4 -> SECDED bits: 16 (incl. parity bit) - // Hamming Code Bit: | Bits used -> data(X)/Hamming Code(H) // Bit unused - - // 0 | H-X-X-X-X-X-X-X - // 1 | -HX--XX--XX--XX - // 2 | ---HXXX----XXXX - // 3 | -------HXXXXXXX - // For further information read "Hacker's delight" chapter 15 - // ATTENTION: The order of indices is different from the one in the book, - // but it doesn't matter in which order your data or check bits are. - // But it should be the same for encoding and decoding - while (i < len) { - for (unsigned j = (i - 1); j < len; j += (i << 1)) { - for (unsigned k = 0; k < (i); k++) { - if (j + k >= len) - break; - p[l] ^= v[j + k]; - } - } - l++; - i <<= 1; - } -} - -// ************************************************************************************************ -// Function which inserts the checkbits which were calculated with 'CalculateCheckbits' in the -// extended data word. This is needed to calculate a proper parity of ALL bits to achive a SECDED -// behaviour. -void ECC::InsertCheckbits(CWord &v, CWord p) -{ - unsigned i = 1, j = 0; - while (i <= v.GetLength() - 1) { - v[i - 1] = p[j++]; - i <<= 1; - } -} - - -// ************************************************************************************************ -// Function which extracts the checkbits out of an extended data word. This is needed to check for -// bit error in the data word. -void ECC::ExtractCheckbits(CWord v, CWord &p) -{ - unsigned i = 1, j = 0; - while (i <= v.GetLength() - 1) { - p[j++] = v[i - 1]; - i <<= 1; - } -} - -// ************************************************************************************************ -// Function which calculates the overal parity -// Simply XOR all bits -void ECC::CalculateParityBit(CWord v, CBit &p) -{ - // Paritybit - p = CBit::ZERO; - for (unsigned i = 0; i < v.GetLength(); i++) { - p ^= v[i]; - } -} - -// ************************************************************************************************ -// Function to insert the parity bit into the extended data word -void ECC::InsertParityBit(CWord &v, CBit p) -{ - v[v.GetLength() - 1] = p; -} - -// ************************************************************************************************ -// Function to extract the parity bit out of an extended data word. -void ECC::ExtractParityBit(CWord v, CBit &p) -{ - p = v[v.GetLength() - 1]; -} diff --git a/src/libdramsys/DRAMSys/error/ECC/ECC.h b/src/libdramsys/DRAMSys/error/ECC/ECC.h deleted file mode 100644 index db2ed2ce..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/ECC.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#pragma once - -#include "Word.h" -#include "Bit.h" - -// ************************************************************************************************ -// -// | __/ __/ __| | __| _ _ _ __| |_(_)___ _ _ ___ -// | _| (_| (__ | _| || | ' \/ _| _| / _ \ ' \(_-< -// |___\___\___| |_| \_,_|_||_\__|\__|_\___/_||_/__/ -// -// ------------------------------------------------------------------------------------------------ -// ECC Implementation as described in "Hacker's Delight - second Edition" by Henry S. Warren, Jr. -// ------------------------------------------------------------------------------------------------ -// This namespace gives you some handy functions to get a SEC-DED implementation. -// -// SEC-DED: Single Error Correction - Double Error Detection -// This is the most common error correction code (ECC). -// It consists of two different correction codes: Haming code + parity code. -// -// For further details read chapter 15 of "Hacker's Delight - second Edition" -// ************************************************************************************************ - -namespace ECC { -unsigned GetNumParityBits(unsigned nDataBits); - -// Extends the data word that it can be used with hamming code -// Several bits will be included at specific places -void ExtendWord(CWord &v); - -void CalculateCheckbits(CWord &v, CWord &p); -void InsertCheckbits(CWord &v, CWord p); -void ExtractCheckbits(CWord v, CWord &p); - -void CalculateParityBit(CWord v, CBit &p); -void InsertParityBit(CWord &v, CBit p); -void ExtractParityBit(CWord v, CBit &p); -} diff --git a/src/libdramsys/DRAMSys/error/ECC/ECC_Test.cpp b/src/libdramsys/DRAMSys/error/ECC/ECC_Test.cpp deleted file mode 100644 index 42a6a3f0..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/ECC_Test.cpp +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -// ECC_Test.cpp : Entry point for the console application. -// - -#include "stdafx.h" -#include -#include "ECC.h" - -int main() -{ - // Random number init - srand(time(NULL)); - - // Erstellen - unsigned size = 4; - CWord p(ECC::GetNumParityBits(size)), v(size); - - // Daten eingeben - for (unsigned a = 0; a < 16; a++) { - v = a; - v.Rotate(); - - ECC::ExtendWord(v); - printf("%d:\t", a); - - p = 0; - ECC::CalculateCheckbits(v, p); - ECC::InsertCheckbits(v, p); - ECC::CalculateParityBit(v, p[3]); - ECC::InsertParityBit(v, p[3]); - - v.Print(); - - v.Resize(size); - } - - printf("\r\n"); - - for (unsigned x = 0; x < 100; x++) { - //Get random number - unsigned a = rand() % 16; - - v.Resize(size); - v = a; - v.Rotate(); - - ECC::ExtendWord(v); - - p = 0; - ECC::CalculateCheckbits(v, p); - ECC::InsertCheckbits(v, p); - ECC::CalculateParityBit(v, p[3]); - ECC::InsertParityBit(v, p[3]); - v.Print(); - - // Insert error - unsigned pos = rand() % 8; - v[pos] ^= CBit(CBit::ONE); - - printf("Data: %d, Error at pos %d: ", a, pos + 1); - v[pos].Print(); - printf("\r\n"); - v.Print(); - - p = 0; - ECC::CalculateCheckbits(v, p); - ECC::CalculateParityBit(v, p[3]); - - printf("%d:\t", a); - - p.Print(); - - // Interpreting Data - - unsigned syndrome = 0; - for (unsigned i = 0; i < p.GetLength() - 1; i++) { - if (p[i] == CBit::ONE) - syndrome += (1 << i); - } - - if (p[3] == CBit::ZERO) { - // Parity even - - if (syndrome) { - // Double error - printf("Double error detected.\r\n"); - break; - } else { - // No Error - printf("No error detected.\r\n"); - break; - } - } else { - // Parity odd - - if (syndrome) { - // Bit error - printf("Error detected in Bit %d.\r\n", syndrome); - if (syndrome == pos + 1) - continue; - else - break; - } else { - // Overall parity Error - printf("Overall parity error detected.\r\n"); - if (pos == 7 || pos == 3 || pos == 1 || pos == 0) - continue; - else - break; - } - } - } - system("pause"); - - return 0; -} - diff --git a/src/libdramsys/DRAMSys/error/ECC/Word.cpp b/src/libdramsys/DRAMSys/error/ECC/Word.cpp deleted file mode 100644 index 928af5ce..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/Word.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#include "Word.h" - -#include -#include -#include - -using std::cout; -using std::deque; - -CWord::CWord(unsigned nBitLength) - : m_nBitLength(nBitLength) -{ - m_word.resize(nBitLength); -} - - -CWord::~CWord() -{ -} - -CBit *CWord::GetAt(unsigned nBitPos) -{ - if (nBitPos < m_nBitLength) { - return &m_word.at(nBitPos); - } - - return nullptr; -} - -void CWord::Set(unsigned data) -{ - deque::iterator it; - if (m_nBitLength < sizeof(data)) { - it = m_word.begin(); - for (unsigned i = 0; i < m_nBitLength; i++) { - (*it++) = data & 1; - data >>= 1; - } - } else { - for (it = m_word.begin(); it != m_word.end(); it++) { - (*it) = data & 1; - data >>= 1; - } - } -} - -void CWord::Set(const unsigned char *data, unsigned lengthInBits) -{ - deque::iterator it; - if (m_nBitLength < lengthInBits) { - it = m_word.begin(); - for (unsigned pos = 0; pos < m_nBitLength; pos++) { - (*it) = data[pos >> 3] & (1 << (7 - (pos & 7))); - it++; - } - } else { - unsigned pos = 0; - for (it = m_word.begin(); it != m_word.end(); it++) { - (*it) = data[pos >> 3] & (1 << (7 - (pos & 7))); - ++pos; - } - } -} - -void CWord::Rotate() -{ - deque buffer = m_word; - for (unsigned i = 0; i < m_nBitLength; i++) { - m_word.at(m_nBitLength - i - 1) = buffer.at(i); - } -} - -bool CWord::Insert(unsigned npos, CBit b) -{ - if (npos >= m_nBitLength) - return false; - - deque::iterator it = m_word.begin() + npos; - m_word.insert(it, b); - - m_nBitLength++; - - return true; -} - -bool CWord::Delete(unsigned npos) -{ - if (npos >= m_nBitLength) - return false; - - deque::iterator it = m_word.begin() + npos; - m_word.erase(it); - - m_nBitLength++; - - return true; -} - -void CWord::Append(CBit b) -{ - m_word.push_back(b); - - m_nBitLength++; -} - -void CWord::Resize(unsigned nsize) -{ - m_word.resize(nsize); - m_nBitLength = nsize; -} - -bool CWord::PartShiftRight(unsigned nPos, unsigned /*nShift*/) -{ - if (nPos >= m_nBitLength) - return false; - - /*for (unsigned i = 0; i < nShift; i++) - { - m_word.insert() - }*/ - - return true; -} - -void CWord::Print() -{ - deque::iterator it; - for (it = m_word.begin(); it != m_word.end(); it++) { - (*it).Print(); - } - cout << "\r\n"; -} - -void CWord::Copy(unsigned char *ptr) -{ - unsigned len = ceil(m_word.size() / 8); - memset(ptr, 0, len); - - unsigned pos = 0; - for (auto it = m_word.begin(); it != m_word.end(); it++) { - ptr[pos >> 3] |= (*it).Get() << (7 - (pos & 7)); - ++pos; - } -} diff --git a/src/libdramsys/DRAMSys/error/ECC/Word.h b/src/libdramsys/DRAMSys/error/ECC/Word.h deleted file mode 100644 index dec8606b..00000000 --- a/src/libdramsys/DRAMSys/error/ECC/Word.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#pragma once - -#include -#include "Bit.h" - -class CWord -{ -protected: - - unsigned m_nBitLength; - std::deque m_word; - - -public: - CWord(unsigned nBitLength); - virtual ~CWord(); - - CBit *GetAt(unsigned nBitPos); - - void Set(unsigned data); - void Set(const unsigned char *data, unsigned lengthInBits); - void Rotate(); - - bool Insert(unsigned npos, CBit b); - bool Delete(unsigned npos); - - void Copy(unsigned char *ptr); - - void Append(CBit b); - - void Resize(unsigned nsize); - - bool PartShiftRight(unsigned nPos, unsigned nShift); - - inline unsigned GetLength() const - { - return m_nBitLength; - }; - - void Print(); - - CWord &operator=(unsigned d) - { - Set(d); - return *this; - } - - CBit &operator[](unsigned nPos) - { - return m_word.at(nPos); - } - - friend CWord operator >> (CWord l, const unsigned &r) - { - for (unsigned i = 0; i < r; i++) { - l.m_word.pop_front(); - l.m_word.push_back(CBit(CBit::VALUE::ZERO)); - } - return l; - } -}; - diff --git a/src/libdramsys/DRAMSys/error/eccbaseclass.cpp b/src/libdramsys/DRAMSys/error/eccbaseclass.cpp deleted file mode 100644 index 3f266077..00000000 --- a/src/libdramsys/DRAMSys/error/eccbaseclass.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#include "eccbaseclass.h" - -using namespace sc_core; -using namespace tlm; - -tlm::tlm_sync_enum ECCBaseClass::nb_transport_fw( int id, - tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay ) -{ - if (trans.get_command() == TLM_WRITE_COMMAND && phase == BEGIN_REQ) { - // Allocate memory for encoded data using the size provided by AllocationEncode - unsigned nEncodedDataSize = AllocationSize(trans.get_data_length()); - assert(nEncodedDataSize != 0); - unsigned char *pEncodedData = new unsigned char[nEncodedDataSize]; - - // Save memory pointer and size - m_mDataPointer[pEncodedData].pData = trans.get_data_ptr(); - m_mDataPointer[pEncodedData].nDataSize = trans.get_data_length(); - - // Data Encoding - Encode(trans.get_data_ptr(), trans.get_data_length(), pEncodedData, - nEncodedDataSize); - - // Change transport data length and pointer - trans.set_data_length(nEncodedDataSize); - trans.set_data_ptr(pEncodedData); - } else if (trans.get_command() == TLM_READ_COMMAND && phase == BEGIN_REQ) { - // Allocate memory for reading data using the size provided by AllocationEncode - unsigned nReadDataSize = AllocationSize(trans.get_data_length()); - assert(nReadDataSize != 0); - unsigned char *pReadData = new unsigned char[nReadDataSize]; - - // Save memory pointer and size - m_mDataPointer[pReadData].pData = trans.get_data_ptr(); - m_mDataPointer[pReadData].nDataSize = trans.get_data_length(); - - // Change transport data length and pointer - trans.set_data_length(nReadDataSize); - trans.set_data_ptr(pReadData); - } - - return i_socket[id]->nb_transport_fw( trans, phase, delay ); -} - - -// Backward interface -tlm::tlm_sync_enum ECCBaseClass::nb_transport_bw( int id, - tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay ) -{ - if (trans.get_command() == TLM_READ_COMMAND && phase == BEGIN_RESP) { - //Look for the corresponding data pointer for decoding - auto it = m_mDataPointer.find(trans.get_data_ptr()); - assert(it != m_mDataPointer.end()); - - // Data Decoding - Decode(trans.get_data_ptr(), trans.get_data_length(), it->second.pData, - it->second.nDataSize); - - // delete data pointer from map - m_mDataPointer.erase(it); - - // Delete data pointer used for encoded data - delete[] trans.get_data_ptr(); - - // Set data pointer and size for decoded data - trans.set_data_ptr(it->second.pData); - trans.set_data_length(it->second.nDataSize); - } else if (trans.get_command() == TLM_WRITE_COMMAND && phase == BEGIN_RESP) { - //Look for the corresponding data pointer for decoding - auto it = m_mDataPointer.find(trans.get_data_ptr()); - assert(it != m_mDataPointer.end()); - - // delete data pointer from map - m_mDataPointer.erase(it); - - // Delete data pointer used for encoded data - delete[] trans.get_data_ptr(); - - // Set data pointer and size for decoded data - trans.set_data_ptr(it->second.pData); - trans.set_data_length(it->second.nDataSize); - } - - return t_socket[id]->nb_transport_bw( trans, phase, delay ); -} diff --git a/src/libdramsys/DRAMSys/error/eccbaseclass.h b/src/libdramsys/DRAMSys/error/eccbaseclass.h deleted file mode 100644 index 9a9d52bb..00000000 --- a/src/libdramsys/DRAMSys/error/eccbaseclass.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#ifndef ECCBASECLASS_H -#define ECCBASECLASS_H - -#include -#include -#include -#include - -#include "ECC/ECC.h" - -#include "../common/DebugManager.h" - -class ECCBaseClass : sc_core::sc_module -{ -public: - struct DataStruct { - unsigned char *pData; - unsigned int nDataSize; - }; - -private: - std::map m_mDataPointer; - -public: - // Function prototype for calculated the size of memory needed for saving the encoded data - // Input nBytes: Number of bytes which have to be encoded - // Return value: Number of bytes which have to be allocated for storing the encoded data - virtual unsigned AllocationSize(unsigned nBytes) = 0; - -protected: - // Function prototype for encoding data. - // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn - // Result should be written in pDataOut, which has a size of nDataOut. - // pDataOut is already allocated with a size given by function AllocationEncode - virtual void Encode(const unsigned char *pDataIn, unsigned nDataIn, - unsigned char *pDataOut, unsigned nDataOut) = 0; - - - // Function prototype for decoding data. - // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn - // Result should be written in pDataOut, which has a size of nDataOut. - // pDataOut is already allocated with a size given by function AllocationDecode - virtual void Decode(const unsigned char *pDataIn, unsigned nDataIn, - unsigned char *pDataOut, unsigned nDataOut) = 0; - -public: - tlm_utils::multi_passthrough_target_socket t_socket; - tlm_utils::multi_passthrough_initiator_socket i_socket; - - SC_CTOR(ECCBaseClass) - : t_socket("t_socket") - , i_socket("i_socket") - { - t_socket.register_nb_transport_fw(this, &ECCBaseClass::nb_transport_fw); - i_socket.register_nb_transport_bw(this, &ECCBaseClass::nb_transport_bw); - } - // Forward interface - tlm::tlm_sync_enum nb_transport_fw( int id, tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_core::sc_time &delay ); - - // Backward interface - tlm::tlm_sync_enum nb_transport_bw( int id, tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_core::sc_time &delay ); -}; - -#endif // ECCBASECLASS_H diff --git a/src/libdramsys/DRAMSys/error/ecchamming.cpp b/src/libdramsys/DRAMSys/error/ecchamming.cpp deleted file mode 100644 index 65255532..00000000 --- a/src/libdramsys/DRAMSys/error/ecchamming.cpp +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#include "ecchamming.h" - -#include "ECC/ECC.h" - -unsigned ECCHamming::AllocationSize(unsigned nBytes) -{ - // For this hamming for 8 bytes one extra byte is needed:l - return nBytes + ceil(nBytes / m_nDatawordSize) * m_nCodewordSize; -} - -void ECCHamming::Encode(const unsigned char *pDataIn, const unsigned nDataIn, - unsigned char *pDataOut, const unsigned nDataOut) -{ - // Calculate how many 8 byte blocks are there - unsigned nBlocks = nDataIn / m_nDatawordSize; - - // No partly filled blocks are supported - assert(nDataIn % m_nDatawordSize == 0); - - // Create ECC data for every block - for (unsigned i = 0; i < nBlocks; i++) { - // Create all variables needed for calulation - CWord dataword(InBits(m_nDatawordSize)); // Size in bits - CWord codeword(InBits(m_nCodewordSize)); // Size in bits - - // Fill in current data block - dataword.Set(&pDataIn[i * m_nDatawordSize], InBits(m_nDatawordSize)); - - // Extend data word. It grows from m_nDatawordSize to m_nDatawordSize + m_nCodewordSize - ECC::ExtendWord(dataword); - - // Initialize the codeword with zeros - codeword = 0; - - // Calculate Checkbits - ECC::CalculateCheckbits(dataword, codeword); - ECC::InsertCheckbits(dataword, codeword); - - // Calculate Parity - ECC::CalculateParityBit(dataword, codeword[7]); - - // Check if there is enough space in the output array (should always be) - assert((i + 1) * (m_nDatawordSize + m_nCodewordSize) <= nDataOut); - - // Copy old data - memcpy(&pDataOut[i * (m_nDatawordSize + m_nCodewordSize)], - &pDataIn[i * m_nDatawordSize], m_nDatawordSize); - - // Save hamming code + parity bit in the last byte - codeword.Copy(&pDataOut[i * (m_nDatawordSize + m_nCodewordSize) + - m_nDatawordSize]); - } -} - -void ECCHamming::Decode(const unsigned char *pDataIn, const unsigned nDataIn, - unsigned char *pDataOut, const unsigned nDataOut) -{ - // Calculate how many 9 byte blocks are there - unsigned nBlocks = nDataIn / (m_nDatawordSize + m_nCodewordSize); - - // No partly filled blocks are supported - assert(nDataIn % (m_nDatawordSize + m_nCodewordSize) == 0); - - // Verify ECC data for every block - for (unsigned i = 0; i < nBlocks; i++) { - // Create all variables needed for calulation - CWord dataword(InBits(m_nDatawordSize)); // Size in bits - CWord codeword(InBits(m_nCodewordSize)); // Size in bits - - // Fill in current data block - dataword.Set(&pDataIn[i * (m_nDatawordSize + m_nCodewordSize)], - InBits(m_nDatawordSize)); - codeword.Set(&pDataIn[i * (m_nDatawordSize + m_nCodewordSize) + - m_nDatawordSize], InBits(m_nCodewordSize)); - - // Extend data word. It grows from m_nDatawordSize to m_nDatawordSize + m_nCodewordSize - ECC::ExtendWord(dataword); - - // Insert old codeword - ECC::InsertCheckbits(dataword, codeword); - ECC::InsertParityBit(dataword, codeword[7]); - - // Reset codeword - codeword = 0; - - // Calculate Checkbits again - ECC::CalculateCheckbits(dataword, codeword); - - // Calculate Parity again - ECC::CalculateParityBit(dataword, codeword[7]); - - // Translate codeword - bool bParity = codeword[7] == CBit::ONE; - - // calculate syndrome - unsigned char c = 0; - codeword.Rotate(); - codeword.Copy(&c); - c &= 0x7F; - - // Parity Error? - if (bParity) { - // Parity Error - - if (c == 0) { - // Only Parity Bit broken - continue - std::cout << "Parity Bit error" << std::endl; - } else { - // Data or Hamming Code Bit broken - std::cout << "Single Error Detected" << std::endl; - } - } else { - // No Parity Error - - if (c == 0) { - // No error at all - continue - } else { - // Double error detected - std::cout << "Double Error Detected (Block " << i << ")." << std::endl; - } - } - - // Check if there is enough space in the output array (should always be) - assert((i + 1) * (m_nDatawordSize) <= nDataOut); - - // Copy data - memcpy(&pDataOut[i * m_nDatawordSize], - &pDataIn[i * (m_nDatawordSize + m_nCodewordSize)], m_nDatawordSize); - } -} diff --git a/src/libdramsys/DRAMSys/error/ecchamming.h b/src/libdramsys/DRAMSys/error/ecchamming.h deleted file mode 100644 index 14986cd7..00000000 --- a/src/libdramsys/DRAMSys/error/ecchamming.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2017, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Johannes Feldmann - * Eder F. Zulian - */ - -#ifndef ECCHAMMIMG_H -#define ECCHAMMIMG_H - -#include "eccbaseclass.h" - - -class ECCHamming : public ECCBaseClass -{ -private: - // Hamming constants for this special implementation - const unsigned m_nDatawordSize = 8; // bytes - const unsigned m_nCodewordSize = 1; // bytes - - inline unsigned InBits(unsigned n) - { - return n << 3; - }; // use this if constants are needed in bits - -public: - // Function prototype for calculated the size of memory needed for saving the encoded data - // Input nBytes: Number of bytes which have to be encoded - // Return value: Number of bytes which have to be allocated for storing the encoded data - virtual unsigned AllocationSize(unsigned nBytes); - -protected: - // Function prototype for encoding data. - // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn - // Result should be written in pDataOut, which has a size of nDataOut. - // pDataOut is already allocated with a size given by function AllocationEncode - virtual void Encode(const unsigned char *pDataIn, unsigned nDataIn, - unsigned char *pDataOut, unsigned nDataOut); - - - // Function prototype for decoding data. - // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn - // Result should be written in pDataOut, which has a size of nDataOut. - // pDataOut is already allocated with a size given by function AllocationDecode - virtual void Decode(const unsigned char *pDataIn, unsigned nDataIn, - unsigned char *pDataOut, unsigned nDataOut); - -public: - ECCHamming(::sc_core::sc_module_name name) : ECCBaseClass(name) - {}; -}; - -#endif // ECCHAMMIMG_H diff --git a/src/libdramsys/DRAMSys/error/errormodel.cpp b/src/libdramsys/DRAMSys/error/errormodel.cpp deleted file mode 100644 index 86e86a03..00000000 --- a/src/libdramsys/DRAMSys/error/errormodel.cpp +++ /dev/null @@ -1,753 +0,0 @@ -/* - * Copyright (c) 2015, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -#include "errormodel.h" -#include "../common/DebugManager.h" -#include "../simulation/TemperatureController.h" -#include "../simulation/AddressDecoder.h" -#include "../common/dramExtensions.h" - -#ifdef DRAMPOWER -#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#endif - -#include -#include -#include -#include -#include -#include - -using namespace sc_core; - -errorModel::errorModel(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController, libDRAMPower *dramPower) - : sc_module(name), memSpec(*config.memSpec), temperatureController(temperatureController) -{ - this->DRAMPower = dramPower; - init(config); -} - -void errorModel::init(const Configuration& config) -{ - powerAnalysis = config.powerAnalysis; - thermalSim = config.thermalSimulation; - // Get Configuration parameters: - burstLenght = config.memSpec->defaultBurstLength; - numberOfColumns = config.memSpec->columnsPerRow; - bytesPerColumn = std::log2(config.memSpec->dataBusWidth); - - // Adjust number of bytes per column dynamically to the selected ecc controller - //TODO: bytesPerColumn = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerColumn); - - numberOfRows = config.memSpec->rowsPerBank; - numberOfBitErrorEvents = 0; - - - // Initialize the lastRow Access array: - lastRowAccess = new sc_time[numberOfRows]; - for (unsigned int i = 0; i < numberOfRows; i++) - lastRowAccess[i] = SC_ZERO_TIME; - - // The name is set when the context is clear. - contextStr = ""; - - // Parse data input: - parseInputData(config); - prepareWeakCells(); - - // Initialize context variables: - myChannel = -1; - myRank = -1; - myBankgroup = -1; - myBank = -1; - - // Test 1: - // If you want to test the function that get the number - // of bit errors for a given temperature and time - // uncomment the following lines: - // - //std::cout << "MAXTemp:" << maxTemperature << std::endl; - //std::cout << "MAXTime:" << maxTime << std::endl; - //getNumberOfFlips(45.0,sc_time(200.0,SC_MS)); - //getNumberOfFlips(45.0,sc_time(190.0,SC_MS)); - //getNumberOfFlips(45.0,sc_time(180.0,SC_MS)); - //getNumberOfFlips(75.0,sc_time(200.0,SC_MS)); - //getNumberOfFlips(75.0,sc_time(190.0,SC_MS)); - //getNumberOfFlips(75.0,sc_time(180.0,SC_MS)); - //getNumberOfFlips(85.0,sc_time(200.0,SC_MS)); - //getNumberOfFlips(85.0,sc_time(190.0,SC_MS)); - //getNumberOfFlips(85.0,sc_time(180.0,SC_MS)); - //getNumberOfFlips(88.0,sc_time(200.0,SC_MS)); - //getNumberOfFlips(88.0,sc_time(190.0,SC_MS)); - //getNumberOfFlips(88.0,sc_time(180.0,SC_MS)); - //getNumberOfFlips(89.0,sc_time(64.0,SC_MS)); - //getNumberOfFlips(89.0,sc_time(64.0,SC_MS)); - //getNumberOfFlips(89.0,sc_time(64.0,SC_MS)); - - // Test 2: - // X X X - // X 1 1 - // X 1 1 - //weakCells[0].bit = 0; - //weakCells[0].col = 0; - //weakCells[0].row = 0; - //weakCells[0].dependent = true; - - markBitFlips(); -} - -errorModel::~errorModel() -{ - // Remove all data from the dataMap: - for (std::map::iterator it = dataMap.begin(); - it != dataMap.end(); ++it ) { - delete it->second; - } - // Delete all elements from the dataMap: - dataMap.clear(); - - // Remove all data from the lastRowAccess - delete [] lastRowAccess; - - // Clean errorMap - errorMap.clear(); - - // Clean list of weak cells: - delete [] weakCells; - - // If an access happened to a bank the numner of error events should be shown: - if (myChannel != -1 && myBank != -1 && myBankgroup != -1 && myRank != -1 ) { - std::cout << contextStr - << ": Number of Retention Error Events = " << numberOfBitErrorEvents - << std::endl; - } -} - -void errorModel::store(tlm::tlm_generic_payload &trans) -{ - // Check wich bits have flipped during the last access and mark them as flipped: - markBitFlips(); - - // Get the key for the dataMap from the transaction's dram extension: - // FIXME -// ControllerExtension &ext = ControllerExtension::getExtension(trans); -// DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), -// ext.getBankGroup().ID(), ext.getBank().ID(), -// ext.getRow().ID(), ext.getColumn().ID(), 0); - DecodedAddress key; -// Set context: - setContext(key); - - std::stringstream msg; - msg << "bank: " << key.bank << " group: " << key.bankgroup << " bytes: " << - key.byte << " channel: " << key.channel << " column: " << key.column << - " rank: " << key.rank << " row: " << key.row; - PRINTDEBUGMESSAGE(name(), msg.str()); - - // Check if the provided data length is correct: - assert((bytesPerColumn * burstLenght) == trans.get_data_length()); - - PRINTDEBUGMESSAGE(name(), ("Data length: " + std::to_string(trans.get_data_length()) + - " bytesPerColumn: " + std::to_string(bytesPerColumn)).c_str()); - - // Handle the DRAM burst, - for (unsigned int i = 0; i < trans.get_data_length(); i += bytesPerColumn) { - unsigned char *data; - - // Check if address is not already stored: - if (dataMap.count(key) == 0) { - // Generate a new data entry - data = new unsigned char[bytesPerColumn]; - } else { // In case the address was stored before: - data = dataMap[key]; - } - - // Copy the data from the transaction to the data pointer - memcpy(data, trans.get_data_ptr() + i, bytesPerColumn); - - // Save part of the burst in the dataMap - // TODO: Check if we can have double entries, is key unique? - dataMap.insert(std::pair(key, data)); - - // Reset flipped weak cells in this area, since they are rewritten now - for (unsigned int j = 0; j < maxNumberOfWeakCells; j++) { - // If the current written column in a row has a week cell: - if (weakCells[j].row == key.row && weakCells[j].col == key.column) { - // If the bit was marked as flipped due to a retention error - // mark it as unflipped: - if (weakCells[j].flipped == true) { - weakCells[j].flipped = false; - } - } - } - - // The next burst element is handled, therfore the column address must be increased - key.column++; - - // Check that there is no column overfow: - std::stringstream msg; - msg << "key.column is " << key.column << " columnsPerRow is " << - numberOfColumns; - PRINTDEBUGMESSAGE(name(), msg.str()); - assert(key.column <= numberOfColumns); - } -} - -void errorModel::load(tlm::tlm_generic_payload &trans) -{ - // Check wich bits have flipped during the last access and mark them as flipped: - markBitFlips(); - - // Get the key for the dataMap from the transaction's dram extension: - // FIXME -// DramExtension &ext = DramExtension::getExtension(trans); -// DecodedAddress key = DecodedAddress(ext.getChannel().ID(), ext.getRank().ID(), -// ext.getBankGroup().ID(), ext.getBank().ID(), -// ext.getRow().ID(), ext.getColumn().ID(), 0); - DecodedAddress key; - // Set context: - setContext(key); - - // Check if the provided data length is correct: - assert((bytesPerColumn * burstLenght) == trans.get_data_length()); - - // Handle the DRAM burst: - for (unsigned int i = 0; i < trans.get_data_length(); i += bytesPerColumn) { - // Check if address is not stored: - if (dataMap.count(key) == 0) { - SC_REPORT_FATAL("errormodel", "Reading from an empty memory location"); - } - - // Copy the dataMap to the transaction data pointer - memcpy(trans.get_data_ptr() + i, dataMap[key], bytesPerColumn); - - // The next burst element is handled, therfore the column address must be increased - key.column++; - - // Check that there is no column overfow: - assert(key.column <= numberOfColumns); - } -} - -void errorModel::markBitFlips() -{ - double temp = getTemperature(); - for (unsigned int row = 0; - row < memSpec.rowsPerBank; row++) { - // If the row has never been accessed ignore it and go to the next one - if (lastRowAccess[row] != SC_ZERO_TIME) { - // Get the time interval between now and the last acivate/refresh - sc_time interval = sc_time_stamp() - lastRowAccess[row]; - - // Obtain the number of bit flips for the current temperature and the time interval: - unsigned int n = getNumberOfFlips(temp, interval); - - // Check if the current row is in the range of bit flips for this interval - // and temperature, if yes mark it as flipped: - for (unsigned int i = 0; i < n; i++) { - // Check if Bit has marked as flipped yet, if yes mark it as flipped - if (!weakCells[i].flipped && weakCells[i].row == row) { - std::stringstream msg; - msg << "Maked weakCell[" << i << "] as flipped" << std::endl; - PRINTDEBUGMESSAGE(name(), msg.str()); - - weakCells[i].flipped = true; - } - } - } - } -} - -void errorModel::refresh(unsigned int row) -{ - // A refresh is internally composed of ACT and PRE that are executed - // on all banks, therefore we call the activate method: - activate(row); -} - -void errorModel::activate(unsigned int row) -{ - // Check wich bits have flipped during the last access and mark them as flipped: - markBitFlips(); - - // The Activate command is responsible that an retention error is manifested. - // Therefore, Flip the bit in the data structure if it is marked as flipped - // and if it is a one. Transisitons from 0 to 1 are only happening - // in DRAM with anticells. This behavior is not implemented yet. - for (unsigned int i = 0; i < maxNumberOfWeakCells; i++) { - if (weakCells[i].flipped == true && weakCells[i].row == row) { - // Estimate key to access column data - DecodedAddress key; - key.bank = myBank; - key.bankgroup = myBankgroup; - key.channel = myChannel; - key.column = weakCells[i].col; - key.rank = myRank; - key.row = row; - - // Byte position in column: - unsigned int byte = weakCells[i].bit / 8; - - // Bit position in byte: - unsigned int bitInByte = weakCells[i].bit % 8; - - // Check if the bit is 1 (only 1->0 transitions are supported) - // DRAMs based on anti cells are not supported yet by this model - if (getBit(key, byte, bitInByte) == 1) { - // Prepare bit mask: invert mask and AND it later - unsigned char mask = pow(2, bitInByte); - mask = ~mask; - - // Temporal storage for modification: - unsigned char tempByte; - - if (weakCells[i].dependent == false) { - // Load the affected byte to tempByte - memcpy(&tempByte, dataMap[key] + byte, 1); - - // Flip the bit: - tempByte = (tempByte & mask); - - // Output on the Console: - std::stringstream msg; - msg << "Bit Flipped!" - << " row: " << key.row - << " col: " << key.column - << " bit: " << weakCells[i].bit; - PRINTDEBUGMESSAGE(name(), msg.str()); - - numberOfBitErrorEvents++; - - // Copy the modified byte back to the dataMap: - memcpy(dataMap[key] + byte, &tempByte, 1); - } else { // if(weakCells[i].dependent == true) - // Get the neighbourhood of the bit and store it in the - // grid variable: - // | 0 1 2 | - // grid = | 3 4 5 | - // | 6 7 8 | - - unsigned int grid[9]; - - grid[0] = getBit(key.row - 1, key.column, byte, bitInByte - 1); - grid[1] = getBit(key.row - 1, key.column, byte, bitInByte ); - grid[2] = getBit(key.row - 1, key.column, byte, bitInByte + 1); - - grid[3] = getBit(key.row , key.column, byte, bitInByte - 1); - grid[4] = getBit(key.row , key.column, byte, bitInByte ); - grid[5] = getBit(key.row , key.column, byte, bitInByte + 1); - - grid[6] = getBit(key.row + 1, key.column, byte, bitInByte - 1); - grid[7] = getBit(key.row + 1, key.column, byte, bitInByte ); - grid[8] = getBit(key.row + 1, key.column, byte, bitInByte + 1); - - unsigned int sum = 0; - for (int s = 0; s < 9; s++) { - sum += grid[s]; - } - - if (sum <= 4) { - // Load the affected byte to tempByte - memcpy(&tempByte, dataMap[key] + byte, 1); - - // Flip the bit: - tempByte = (tempByte & mask); - numberOfBitErrorEvents++; - - // Copy the modified byte back to the dataMap: - memcpy(dataMap[key] + byte, &tempByte, 1); - - // Output on the Console: - std::stringstream msg; - msg << "Dependent Bit Flipped!" - << " row: " << key.row - << " col: " << key.column - << " bit: " << weakCells[i].bit - << " sum: " << sum << std::endl - << grid[0] << grid[1] << grid[2] << std::endl - << grid[3] << grid[4] << grid[5] << std::endl - << grid[6] << grid[7] << grid[8]; - PRINTDEBUGMESSAGE(name(), msg.str()); - } else { - // Output on the Console: - std::stringstream msg; - msg << "Dependent Bit NOT Flipped!" - << " row: " << key.row - << " col: " << key.column - << " bit: " << weakCells[i].bit - << " sum: " << sum << std::endl - << grid[0] << grid[1] << grid[2] << std::endl - << grid[3] << grid[4] << grid[5] << std::endl - << grid[6] << grid[7] << grid[8]; - PRINTDEBUGMESSAGE(name(), msg.str()); - } - } - } - } - } - - lastRowAccess[row] = sc_time_stamp(); -} - -// This method is used to get a bit with a key, usually for independent case: -unsigned int errorModel::getBit(DecodedAddress key, unsigned int byteInColumn, - unsigned int bitInByte) -{ - // If the data was not writte by the produce yet it is zero: - if (dataMap.count(key) == 0) { - return 0; - } else { // Return the value of the bit - unsigned char tempByte; - - // Copy affected byte to a temporal variable: - memcpy(&tempByte, dataMap[key] + byteInColumn, 1); - unsigned char mask = pow(2, bitInByte); - unsigned int result = (tempByte & mask) >> bitInByte; - std::bitset<8> x(mask); - - std::stringstream msg; - msg << "mask = " << x - << " bitInByte = " << bitInByte - << " tempByte = " << (unsigned int)tempByte - << " result = " << result; - - PRINTDEBUGMESSAGE(name(), msg.str()); - - return result; - } -} - -// This method is used to get neighbourhoods, for the dependent case: -unsigned int errorModel::getBit(int row, int column, int byteInColumn, - int bitInByte) -{ - // Border-Exception handling: - - // Switch the byte if bit under/overflow: - if (bitInByte < 0) { - byteInColumn--; - bitInByte = 7; - } else if (bitInByte >= 8) { - byteInColumn++; - bitInByte = 0; - } - - // Switch the column if byte under/overflow - if (byteInColumn < 0) { - column--; - byteInColumn = bytesPerColumn; - } else if (byteInColumn >= int(byteInColumn)) { - column++; - byteInColumn = 0; - } - - // If we switch the row we return 0 (culumn under/overflow) - if (column < 0) { - return 0; - } else if (column >= int(numberOfColumns)) { - return 0; - } - - // Row over/underflow return 0 - if (row < 0) { - return 0; - } else if (row >= int(numberOfRows)) { - return 0; - } - - DecodedAddress key; - key.bank = myBank; - key.bankgroup = myBankgroup; - key.channel = myChannel; - key.rank = myRank; - key.column = column; - key.row = row; - - return getBit(key, byteInColumn, bitInByte); -} - -double errorModel::getTemperature() -{ - // FIXME - // make sure the context is set (myChannel has the proper value) before - // requesting the temperature. - double temperature = 89; - - if (this->myChannel != -1) - { -#ifdef DRAMPOWER - if (thermalSim && powerAnalysis) - { - // TODO - // check if this is best way to request information to DRAMPower. - unsigned long long clk_cycles = sc_time_stamp() / memSpec.tCK; - DRAMPower->calcWindowEnergy(clk_cycles); - float average_power = (float)DRAMPower->getPower().average_power; - temperature = temperatureController.getTemperature(this->myChannel, average_power); - } else { - temperature = temperatureController.getTemperature(this->myChannel, 0); - } -#else - temperature = temperatureController.getTemperature(this->myChannel, 0); -#endif - } - - return temperature; -} - -void errorModel::parseInputData(const Configuration& config) -{ - std::string fileName = config.errorCSVFile; - std::ifstream inputFile(fileName); - - if (inputFile.is_open()) { - std::string line; - while (std::getline(inputFile, line)) { - std::istringstream iss(line); - std::string str_temperature; - std::string str_retentionTime; - std::string str_mu_independent; - std::string str_sigma_independent; - std::string str_mu_dependent; - std::string str_sigma_dependent; - - // Parse file: - iss >> str_temperature - >> str_retentionTime - >> str_mu_independent - >> str_sigma_independent - >> str_mu_dependent - >> str_sigma_dependent; - - double temp = std::stod(str_temperature.c_str(), 0); - sc_time retentionTime = sc_time(std::stod(str_retentionTime.c_str(), 0), - SC_MS); - - unsigned int mu_independent = std::stod(str_mu_independent.c_str(), 0); - unsigned int sigma_independent = std::stod(str_sigma_independent.c_str(), 0); - unsigned int mu_dependent = std::stod(str_mu_dependent.c_str(), 0); - unsigned int sigma_dependent = std::stod(str_sigma_dependent.c_str(), 0); - - errors e; - - //calculate normal distribution of # of independent errors - unsigned seed = std::chrono::system_clock::now().time_since_epoch().count(); - std::default_random_engine generator(seed); - std::normal_distribution distribution(mu_independent, - sigma_independent); - e.independent = ceil(distribution(generator)); - - // calculate normal distribution of # of dependent errors - unsigned seed2 = std::chrono::system_clock::now().time_since_epoch().count(); - std::default_random_engine generator2(seed2); - std::normal_distribution distribution2(mu_dependent, sigma_dependent); - e.dependent = ceil(distribution2(generator2)); - - // Store parsed data to the errorMap: - errorMap[temp][retentionTime] = e; - - std::stringstream msg; - msg << "Temperature = " << temp - << " Time = " << retentionTime - << " independent = " << errorMap[temp][retentionTime].independent - << " dependent = " << errorMap[temp][retentionTime].dependent; - - PRINTDEBUGMESSAGE(name(), msg.str()); - } - inputFile.close(); - } else { - SC_REPORT_FATAL("errormodel", "Cannot open ErrorCSVFile"); - } -} - -void errorModel::prepareWeakCells() -{ - // Get the Maxium number of weak cells by iterating over the errorMap: - maxNumberOfWeakCells = 0; - maxNumberOfDepWeakCells = 0; - for ( const auto &i : errorMap ) { - for ( const auto &j : i.second ) { - // Get number of dependent weak cells: - if ( j.second.dependent > maxNumberOfDepWeakCells) { - maxNumberOfDepWeakCells = j.second.dependent; - } - - // Get the total number of weak cells (independet + dependent): - if ( j.second.independent + j.second.dependent > maxNumberOfWeakCells) { - maxNumberOfWeakCells = j.second.independent + j.second.dependent; - } - } - } - - // Get the highest temperature in the error map: - maxTemperature = 0; - for ( const auto &i : errorMap ) { - if (i.first > maxTemperature) { - maxTemperature = i.first; - } - } - - // Get the highest time in the error map: - maxTime = SC_ZERO_TIME; - for ( const auto &i : errorMap ) { - for ( const auto &j : i.second ) { - if (j.first > maxTime) { - maxTime = j.first; - } - } - } - - // Generate weak cells: - - weakCells = new weakCell[maxNumberOfWeakCells]; - - for (unsigned int i = 0; i < maxNumberOfWeakCells; i++) { - unsigned int row, col, bit; - - // Select positions of weak cells randomly, uniformly distributed: - row = (unsigned int) (rand() % numberOfRows); - col = (unsigned int) (rand() % numberOfColumns); - bit = (unsigned int) (rand() % (bytesPerColumn * 8)); - - // Test if weak cell has been chosen already before: - bool found = false; - for (unsigned int k = 0; k < i; k++) { - if ((weakCells[k].row == row) && (weakCells[k].col == col) - && (weakCells[k].bit == bit)) { - found = true; - break; - } - } - // If a cell was already choosen as weak we have to roll the dice again: - if (found) { - i--; - } else { - weakCells[i].row = row; // Row in the bank - weakCells[i].col = col; // Column in the row - weakCells[i].bit = bit; // Bit position in column - weakCells[i].flipped = - false; // Flag whether this position has already flipped - weakCells[i].dependent = - false; // init dependency flag with false, dependent cells will be estimated in the next step - } - } - - // Generate dependent weak cells: - for (unsigned int i = 1; i <= maxNumberOfDepWeakCells; i++) { - unsigned int r = (rand() % maxNumberOfWeakCells); - - // If the dependent weak cell was choosen before roll the dice again: - if (weakCells[r].dependent) { - i--; - } else { - weakCells[r].dependent = true; - } - - } - - // Debug output where the weak cells are located: - for (unsigned int i = 0; i < maxNumberOfWeakCells; i++) { - std::stringstream msg; - msg << "row=" << weakCells[i].row - << " col=" << weakCells[i].col - << " bit=" << weakCells[i].bit - << " flip=" << weakCells[i].flipped - << " dep=" << weakCells[i].dependent; - PRINTDEBUGMESSAGE(name(), msg.str()); - } -} - -// Retrieve number of flipping bits which fits best to temperature input and time since last refresh -unsigned int errorModel::getNumberOfFlips(double temp, sc_time time) -{ - // Check if the provided temperature and retention time are in a valid - // range that is covered by the input data stored in the errorMap. In case - // of values out of the valid range the simulation will be aborted. - if (temp > maxTemperature) { - SC_REPORT_FATAL("errormodel", "temperature out of range"); - } - - if (time > maxTime) { - SC_REPORT_FATAL("errormodel", "time out of range"); - } - - // Find nearest temperature: - double nearestTemperature = 0; - for ( const auto &i : errorMap ) { - if (i.first >= temp) { // for worst case reasons we go to the next bin - nearestTemperature = i.first; - break; - } - } - - // Find nearest time: - sc_time nearestTime; - for ( const auto &i : errorMap[nearestTemperature]) { - if (i.first >= time) { // for worst case reasons we go to the next bin - nearestTime = i.first; - break; - } - } - - errors e = errorMap[nearestTemperature][nearestTime]; - - //std::stringstream msg; - //msg << "ACT/REF temp:" << temp - // << " time:" << time - // << " nearestTemp:" << nearestTemperature - // << " nearestTime:" << nearestTime - // << " ind:" << e.independent - // << " dep:" << e.dependent; - - //printDebugMessage(msg.str()); - - return e.independent + e.dependent; -} - -void errorModel::setContext(DecodedAddress addr) -{ - // This function is called the first store ore load to get the context in - // which channel, rank or bank the error model is used. - if (myChannel == -1 && myBank == -1 && myBankgroup == -1 && myRank == -1 ) { - myChannel = addr.channel; - myBank = addr.bank; - myBankgroup = addr.bankgroup; - myRank = addr.rank; - - contextStr = "Channel_" + std::to_string(myChannel) + "_Bank_" + std::to_string( - myBank) + " "; - } -} diff --git a/src/libdramsys/DRAMSys/error/errormodel.h b/src/libdramsys/DRAMSys/error/errormodel.h deleted file mode 100644 index e86ea65b..00000000 --- a/src/libdramsys/DRAMSys/error/errormodel.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2015, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -#ifndef ERRORMODEL_H -#define ERRORMODEL_H - -#include - -#include -#include -#include "../simulation/AddressDecoder.h" -#include "../simulation/TemperatureController.h" - -class libDRAMPower; - -class errorModel : public sc_core::sc_module -{ -public: - errorModel(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController, libDRAMPower* dramPower = nullptr); - ~errorModel() override; - - // Access Methods: - void store(tlm::tlm_generic_payload &trans); - void load(tlm::tlm_generic_payload &trans); - void refresh(unsigned int row); - void activate(unsigned int row); - void setTemperature(double t); - double getTemperature(); - -private: - void init(const Configuration& config); - bool powerAnalysis; - libDRAMPower *DRAMPower; - bool thermalSim; - TemperatureController& temperatureController; - const MemSpec& memSpec; - // Configuration Parameters: - unsigned int burstLenght; - unsigned int numberOfColumns; - unsigned int bytesPerColumn; - unsigned int numberOfRows; - - // context: - std::string contextStr; - - // Online Parameters: - unsigned int numberOfBitErrorEvents; - - // Private Methods: - void parseInputData(const Configuration& config); - void prepareWeakCells(); - void markBitFlips(); - unsigned int getNumberOfFlips(double temp, sc_core::sc_time time); - void setContext(DecodedAddress addr); - unsigned int getBit(DecodedAddress key, unsigned int byte, - unsigned int bitInByte); - unsigned int getBit(int row, int column, int byteInColumn, int bitInByte); - - // Input related data structures: - - struct errors { - double independent; - double dependent; - }; - - // temperature time number of errors - // | | | - std::map > errorMap; - - unsigned int maxNumberOfWeakCells; - unsigned int maxNumberOfDepWeakCells; - double maxTemperature; - sc_core::sc_time maxTime; - - // Storage of weak cells: - struct weakCell { - unsigned int row; - unsigned int col; - unsigned int bit; - bool flipped; - bool dependent; - }; - - weakCell *weakCells; - - // To use a map for storing the data a comparing function must be defined - struct DecodedAddressComparer - { - bool operator() (const DecodedAddress &first , - const DecodedAddress &second) const - { - if (first.row == second.row) - return first.column < second.column; - else - return first.row < second.row; - } - }; - - // The data structure stores complete column accesses - // A DRAM burst will be splitted up in several column accesses - // e.g. BL=4 means that 4 elements will be added to the dataMap! - std::map dataMap; - - // An array to save when the last ACT/REF to a row happened: - sc_core::sc_time *lastRowAccess; - - // Context Variables (will be written by the first dram access) - int myChannel; - int myRank; - int myBankgroup; - int myBank; -}; - -#endif // ERRORMODEL_H diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index cc0bfb14..60f1c6b0 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -36,56 +36,54 @@ * Derek Christ */ +#include "AddressDecoder.h" + #include #include #include #include -#include "AddressDecoder.h" -#include "../common/utils.h" -#include - -AddressDecoder::AddressDecoder(const Configuration& config, const DRAMSys::Config::AddressMapping &addressMapping) +AddressDecoder::AddressDecoder(const Configuration& config, const DRAMSys::Config::AddressMapping& addressMapping) { - if (const auto &channelBits = addressMapping.channelBits) + if (const auto& channelBits = addressMapping.channelBits) { std::copy(channelBits->begin(), channelBits->end(), std::back_inserter(vChannelBits)); } - if (const auto &rankBits = addressMapping.rankBits) + if (const auto& rankBits = addressMapping.rankBits) { std::copy(rankBits->begin(), rankBits->end(), std::back_inserter(vRankBits)); } - if (const auto &bankGroupBits = addressMapping.bankGroupBits) + if (const auto& bankGroupBits = addressMapping.bankGroupBits) { std::copy(bankGroupBits->begin(), bankGroupBits->end(), std::back_inserter(vBankGroupBits)); } - if (const auto &byteBits = addressMapping.byteBits) + if (const auto& byteBits = addressMapping.byteBits) { std::copy(byteBits->begin(), byteBits->end(), std::back_inserter(vByteBits)); } - if (const auto &xorBits = addressMapping.xorBits) + if (const auto& xorBits = addressMapping.xorBits) { - for (const auto &xorBit : *xorBits) + for (const auto& xorBit : *xorBits) { vXor.emplace_back(xorBit.first, xorBit.second); } } - if (const auto &bankBits = addressMapping.bankBits) + if (const auto& bankBits = addressMapping.bankBits) { std::copy(bankBits->begin(), bankBits->end(), std::back_inserter(vBankBits)); } - if (const auto &rowBits = addressMapping.rowBits) + if (const auto& rowBits = addressMapping.rowBits) { std::copy(rowBits->begin(), rowBits->end(), std::back_inserter(vRowBits)); } - if (const auto &columnBits = addressMapping.columnBits) + if (const auto& columnBits = addressMapping.columnBits) { std::copy(columnBits->begin(), columnBits->end(), std::back_inserter(vColumnBits)); } @@ -154,7 +152,7 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto &it : vXor) + for (auto& it : vXor) { uint64_t xoredBit; xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); @@ -199,7 +197,7 @@ unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto &it : vXor) + for (auto& it : vXor) { uint64_t xoredBit; xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.h b/src/libdramsys/DRAMSys/simulation/AddressDecoder.h index 00966061..57f2f324 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.h +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.h @@ -39,10 +39,12 @@ #ifndef ADDRESSDECODER_H #define ADDRESSDECODER_H +#include "DRAMSys/configuration/Configuration.h" + +#include "DRAMSys/config/DRAMSysConfiguration.h" + #include #include -#include -#include struct DecodedAddress { @@ -67,9 +69,9 @@ struct DecodedAddress class AddressDecoder { public: - AddressDecoder(const Configuration& config, const DRAMSys::Config::AddressMapping &addressMapping); - DecodedAddress decodeAddress(uint64_t encAddr) const; - unsigned decodeChannel(uint64_t encAddr) const; + AddressDecoder(const Configuration& config, const DRAMSys::Config::AddressMapping& addressMapping); + [[nodiscard]] DecodedAddress decodeAddress(uint64_t encAddr) const; + [[nodiscard]] unsigned decodeChannel(uint64_t encAddr) const; void print() const; private: diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index 8807e45a..692cc0fe 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -38,15 +38,16 @@ */ #include "Arbiter.h" -#include "AddressDecoder.h" -#include -#include +#include "DRAMSys/simulation/AddressDecoder.h" +#include "DRAMSys/configuration/Configuration.h" + +#include "DRAMSys/config/DRAMSysConfiguration.h" using namespace sc_core; using namespace tlm; -Arbiter::Arbiter(const sc_module_name &name, const Configuration& config, +Arbiter::Arbiter(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : sc_module(name), addressDecoder(addressDecoder), payloadEventQueue(this, &Arbiter::peqCallback), tCK(config.memSpec->tCK), @@ -64,12 +65,12 @@ ArbiterSimple::ArbiterSimple(const sc_module_name& name, const Configuration& co const AddressDecoder& addressDecoder) : Arbiter(name, config, addressDecoder) {} -ArbiterFifo::ArbiterFifo(const sc_module_name &name, const Configuration& config, +ArbiterFifo::ArbiterFifo(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : Arbiter(name, config, addressDecoder), maxActiveTransactions(config.maxActiveTransactions) {} -ArbiterReorder::ArbiterReorder(const sc_module_name &name, const Configuration& config, +ArbiterReorder::ArbiterReorder(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : Arbiter(name, config, addressDecoder), maxActiveTransactions(config.maxActiveTransactions) {} @@ -82,8 +83,8 @@ void Arbiter::end_of_elaboration() // channel side channelIsBusy = std::vector(iSocket.size(), false); - pendingRequests = std::vector>(iSocket.size(), - std::queue()); + pendingRequests = std::vector>(iSocket.size(), + std::queue()); nextChannelPayloadIDToAppend = std::vector(iSocket.size(), 1); } @@ -92,8 +93,8 @@ void ArbiterSimple::end_of_elaboration() Arbiter::end_of_elaboration(); // initiator side - pendingResponses = std::vector>(tSocket.size(), - std::queue()); + pendingResponses = std::vector>(tSocket.size(), + std::queue()); } void ArbiterFifo::end_of_elaboration() @@ -102,9 +103,9 @@ void ArbiterFifo::end_of_elaboration() // initiator side activeTransactions = std::vector(tSocket.size(), 0); - outstandingEndReq = std::vector(tSocket.size(), nullptr); - pendingResponses = std::vector>(tSocket.size(), - std::queue()); + outstandingEndReq = std::vector(tSocket.size(), nullptr); + pendingResponses = std::vector>(tSocket.size(), + std::queue()); lastEndReq = std::vector(iSocket.size(), sc_max_time()); lastEndResp = std::vector(tSocket.size(), sc_max_time()); @@ -116,17 +117,17 @@ void ArbiterReorder::end_of_elaboration() // initiator side activeTransactions = std::vector(tSocket.size(), 0); - outstandingEndReq = std::vector(tSocket.size(), nullptr); - pendingResponses = std::vector> - (tSocket.size(), std::set()); + outstandingEndReq = std::vector(tSocket.size(), nullptr); + pendingResponses = std::vector> + (tSocket.size(), std::set()); nextThreadPayloadIDToReturn = std::vector(tSocket.size(), 1); lastEndReq = std::vector(iSocket.size(), sc_max_time()); lastEndResp = std::vector(tSocket.size(), sc_max_time()); } -tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay) +tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, + tlm_phase& phase, sc_time& fwDelay) { sc_time clockOffset = sc_time::from_value((sc_time_stamp() + fwDelay).value() % tCK.value()); sc_time notDelay = (clockOffset == SC_ZERO_TIME) ? fwDelay : (fwDelay + tCK - clockOffset); @@ -135,23 +136,23 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, { // TODO: do not adjust address permanently // adjust address offset: - uint64_t adjustedAddress = payload.get_address() - addressOffset; - payload.set_address(adjustedAddress); + uint64_t adjustedAddress = trans.get_address() - addressOffset; + trans.set_address(adjustedAddress); unsigned channel = addressDecoder.decodeChannel(adjustedAddress); - assert(addressDecoder.decodeChannel(adjustedAddress + payload.get_data_length() - 1) == channel); - ArbiterExtension::setAutoExtension(payload, Thread(id), Channel(channel)); - payload.acquire(); + assert(addressDecoder.decodeChannel(adjustedAddress + trans.get_data_length() - 1) == channel); + ArbiterExtension::setAutoExtension(trans, Thread(id), Channel(channel)); + trans.acquire(); } PRINTDEBUGMESSAGE(name(), "[fw] " + getPhaseName(phase) + " notification in " + notDelay.to_string()); - payloadEventQueue.notify(payload, phase, notDelay); + payloadEventQueue.notify(trans, phase, notDelay); return TLM_ACCEPTED; } -tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay) +tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload, + tlm_phase& phase, sc_time& bwDelay) { PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + bwDelay.to_string()); @@ -159,7 +160,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload &payload, return TLM_ACCEPTED; } -unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) +unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans) { trans.set_address(trans.get_address() - addressOffset); @@ -167,14 +168,14 @@ unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) return iSocket[static_cast(decodedAddress.channel)]->transport_dbg(trans); } -void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) +void ArbiterSimple::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbPhase) { - unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); - unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); + unsigned int threadId = ArbiterExtension::getThread(cbTrans).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbTrans).ID(); if (cbPhase == BEGIN_REQ) // from initiator { - ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, sc_time_stamp()); + ArbiterExtension::setIDAndTimeOfGeneration(cbTrans, nextThreadPayloadIDToAppend[threadId]++, sc_time_stamp()); if (!channelIsBusy[channelId]) { @@ -183,10 +184,10 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = arbitrationDelayFw; - iSocket[static_cast(channelId)]->nb_transport_fw(cbPayload, tPhase, tDelay); + iSocket[static_cast(channelId)]->nb_transport_fw(cbTrans, tPhase, tDelay); } else - pendingRequests[channelId].push(&cbPayload); + pendingRequests[channelId].push(&cbTrans); } else if (cbPhase == END_REQ) // from target { @@ -194,7 +195,7 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - tSocket[static_cast(threadId)]->nb_transport_bw(cbPayload, tPhase, tDelay); + tSocket[static_cast(threadId)]->nb_transport_bw(cbTrans, tPhase, tDelay); } if (!pendingRequests[channelId].empty()) @@ -217,14 +218,14 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = arbitrationDelayBw; - tlm_sync_enum returnValue = tSocket[static_cast(threadId)]->nb_transport_bw(cbPayload, tPhase, tDelay); + tlm_sync_enum returnValue = tSocket[static_cast(threadId)]->nb_transport_bw(cbTrans, tPhase, tDelay); // Early completion from initiator if (returnValue == TLM_UPDATED) - payloadEventQueue.notify(cbPayload, tPhase, tDelay); + payloadEventQueue.notify(cbTrans, tPhase, tDelay); threadIsBusy[threadId] = true; } else - pendingResponses[threadId].push(&cbPayload); + pendingResponses[threadId].push(&cbTrans); } else if (cbPhase == END_RESP) // from initiator { @@ -232,9 +233,9 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase tlm_phase tPhase = END_RESP; sc_time tDelay = SC_ZERO_TIME; - iSocket[static_cast(channelId)]->nb_transport_fw(cbPayload, tPhase, tDelay); + iSocket[static_cast(channelId)]->nb_transport_fw(cbTrans, tPhase, tDelay); } - cbPayload.release(); + cbTrans.release(); if (!pendingResponses[threadId].empty()) { @@ -256,10 +257,10 @@ void ArbiterSimple::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); } -void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) +void ArbiterFifo::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbPhase) { - unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); - unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); + unsigned int threadId = ArbiterExtension::getThread(cbTrans).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbTrans).ID(); if (cbPhase == BEGIN_REQ) // from initiator { @@ -267,18 +268,18 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c { activeTransactions[threadId]++; - ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, + ArbiterExtension::setIDAndTimeOfGeneration(cbTrans, nextThreadPayloadIDToAppend[threadId]++, sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - tSocket[static_cast(threadId)]->nb_transport_bw(cbPayload, tPhase, tDelay); + tSocket[static_cast(threadId)]->nb_transport_bw(cbTrans, tPhase, tDelay); - payloadEventQueue.notify(cbPayload, REQ_ARBITRATION, arbitrationDelayFw); + payloadEventQueue.notify(cbTrans, REQ_ARBITRATION, arbitrationDelayFw); } else - outstandingEndReq[threadId] = &cbPayload; + outstandingEndReq[threadId] = &cbTrans; } else if (cbPhase == END_REQ) // from memory controller { @@ -303,15 +304,15 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c tlm_phase tPhase = END_RESP; sc_time tDelay = SC_ZERO_TIME; - iSocket[static_cast(channelId)]->nb_transport_fw(cbPayload, tPhase, tDelay); + iSocket[static_cast(channelId)]->nb_transport_fw(cbTrans, tPhase, tDelay); } - payloadEventQueue.notify(cbPayload, RESP_ARBITRATION, arbitrationDelayBw); + payloadEventQueue.notify(cbTrans, RESP_ARBITRATION, arbitrationDelayBw); } else if (cbPhase == END_RESP) // from initiator { lastEndResp[threadId] = sc_time_stamp(); - cbPayload.release(); + cbTrans.release(); if (outstandingEndReq[threadId] != nullptr) { @@ -347,7 +348,7 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c } else if (cbPhase == REQ_ARBITRATION) { - pendingRequests[channelId].push(&cbPayload); + pendingRequests[channelId].push(&cbTrans); if (!channelIsBusy[channelId]) { @@ -363,7 +364,7 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c } else if (cbPhase == RESP_ARBITRATION) { - pendingResponses[threadId].push(&cbPayload); + pendingResponses[threadId].push(&cbTrans); if (!threadIsBusy[threadId]) { @@ -384,10 +385,10 @@ void ArbiterFifo::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &c SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); } -void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase &cbPhase) +void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& cbPhase) { - unsigned int threadId = ArbiterExtension::getThread(cbPayload).ID(); - unsigned int channelId = ArbiterExtension::getChannel(cbPayload).ID(); + unsigned int threadId = ArbiterExtension::getThread(cbTrans).ID(); + unsigned int channelId = ArbiterExtension::getChannel(cbTrans).ID(); if (cbPhase == BEGIN_REQ) // from initiator { @@ -395,18 +396,18 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase { activeTransactions[threadId]++; - ArbiterExtension::setIDAndTimeOfGeneration(cbPayload, nextThreadPayloadIDToAppend[threadId]++, + ArbiterExtension::setIDAndTimeOfGeneration(cbTrans, nextThreadPayloadIDToAppend[threadId]++, sc_time_stamp()); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; - tSocket[static_cast(threadId)]->nb_transport_bw(cbPayload, tPhase, tDelay); + tSocket[static_cast(threadId)]->nb_transport_bw(cbTrans, tPhase, tDelay); - payloadEventQueue.notify(cbPayload, REQ_ARBITRATION, arbitrationDelayFw); + payloadEventQueue.notify(cbTrans, REQ_ARBITRATION, arbitrationDelayFw); } else - outstandingEndReq[threadId] = &cbPayload; + outstandingEndReq[threadId] = &cbTrans; } else if (cbPhase == END_REQ) // from memory controller { @@ -430,15 +431,15 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase { tlm_phase tPhase = END_RESP; sc_time tDelay = SC_ZERO_TIME; - iSocket[static_cast(channelId)]->nb_transport_fw(cbPayload, tPhase, tDelay); + iSocket[static_cast(channelId)]->nb_transport_fw(cbTrans, tPhase, tDelay); } - payloadEventQueue.notify(cbPayload, RESP_ARBITRATION, arbitrationDelayBw); + payloadEventQueue.notify(cbTrans, RESP_ARBITRATION, arbitrationDelayBw); } else if (cbPhase == END_RESP) // from initiator { lastEndResp[threadId] = sc_time_stamp(); - cbPayload.release(); + cbTrans.release(); if (outstandingEndReq[threadId] != nullptr) { @@ -478,7 +479,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase } else if (cbPhase == REQ_ARBITRATION) { - pendingRequests[channelId].push(&cbPayload); + pendingRequests[channelId].push(&cbTrans); if (!channelIsBusy[channelId]) { @@ -494,7 +495,7 @@ void ArbiterReorder::peqCallback(tlm_generic_payload &cbPayload, const tlm_phase } else if (cbPhase == RESP_ARBITRATION) { - pendingResponses[threadId].insert(&cbPayload); + pendingResponses[threadId].insert(&cbTrans); if (!threadIsBusy[threadId]) { diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index f99e997e..7865eff6 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -40,18 +40,18 @@ #ifndef ARBITER_H #define ARBITER_H +#include "DRAMSys/simulation/AddressDecoder.h" +#include "DRAMSys/common/dramExtensions.h" + #include #include #include #include - -#include #include +#include #include #include #include -#include "AddressDecoder.h" -#include "../common/dramExtensions.h" DECLARE_EXTENDED_PHASE(REQ_ARBITRATION); DECLARE_EXTENDED_PHASE(RESP_ARBITRATION); @@ -63,7 +63,7 @@ public: tlm_utils::multi_passthrough_target_socket tSocket; protected: - Arbiter(const sc_core::sc_module_name &name, const Configuration& config, + Arbiter(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(Arbiter); @@ -72,21 +72,21 @@ protected: const AddressDecoder& addressDecoder; tlm_utils::peq_with_cb_and_phase payloadEventQueue; - virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) = 0; + virtual void peqCallback(tlm::tlm_generic_payload& payload, const tlm::tlm_phase& phase) = 0; std::vector threadIsBusy; std::vector channelIsBusy; - std::vector> pendingRequests; + std::vector> pendingRequests; std::vector nextThreadPayloadIDToAppend; std::vector nextChannelPayloadIDToAppend; - tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_core::sc_time &fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); - unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans); + tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); + tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& bwDelay); + unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); const sc_core::sc_time tCK; const sc_core::sc_time arbitrationDelayFw; @@ -99,33 +99,33 @@ protected: class ArbiterSimple final : public Arbiter { public: - ArbiterSimple(const sc_core::sc_module_name &name, const Configuration& config, + ArbiterSimple(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterSimple); private: void end_of_elaboration() override; - void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; + void peqCallback(tlm::tlm_generic_payload& cbTrans, const tlm::tlm_phase& phase) override; - std::vector> pendingResponses; + std::vector> pendingResponses; }; class ArbiterFifo final : public Arbiter { public: - ArbiterFifo(const sc_core::sc_module_name &name, const Configuration& config, + ArbiterFifo(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterFifo); private: void end_of_elaboration() override; - void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; + void peqCallback(tlm::tlm_generic_payload& cbTrans, const tlm::tlm_phase& phase) override; std::vector activeTransactions; const unsigned maxActiveTransactions; - std::vector outstandingEndReq; - std::vector> pendingResponses; + std::vector outstandingEndReq; + std::vector> pendingResponses; std::vector lastEndReq; std::vector lastEndResp; @@ -134,26 +134,26 @@ private: class ArbiterReorder final : public Arbiter { public: - ArbiterReorder(const sc_core::sc_module_name &name, const Configuration& config, + ArbiterReorder(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder); SC_HAS_PROCESS(ArbiterReorder); private: void end_of_elaboration() override; - void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; + void peqCallback(tlm::tlm_generic_payload& cbTrans, const tlm::tlm_phase& phase) override; std::vector activeTransactions; const unsigned maxActiveTransactions; struct ThreadPayloadIDCompare { - bool operator() (const tlm::tlm_generic_payload *lhs, const tlm::tlm_generic_payload *rhs) const + bool operator() (const tlm::tlm_generic_payload* lhs, const tlm::tlm_generic_payload* rhs) const { return ArbiterExtension::getThreadPayloadID(*lhs) < ArbiterExtension::getThreadPayloadID(*rhs); } }; - std::vector outstandingEndReq; + std::vector outstandingEndReq; std::vector> pendingResponses; std::vector lastEndReq; diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index c44fefb1..afb71a20 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -38,48 +38,47 @@ * Derek Christ */ +#include "DRAMSys.h" + +#include "DRAMSys/common/DebugManager.h" +#include "DRAMSys/common/utils.h" +#include "DRAMSys/controller/Controller.h" +#include "DRAMSys/simulation/dram/DramDDR3.h" +#include "DRAMSys/simulation/dram/DramDDR4.h" +#include "DRAMSys/simulation/dram/DramWideIO.h" +#include "DRAMSys/simulation/dram/DramLPDDR4.h" +#include "DRAMSys/simulation/dram/DramWideIO2.h" +#include "DRAMSys/simulation/dram/DramHBM2.h" +#include "DRAMSys/simulation/dram/DramGDDR5.h" +#include "DRAMSys/simulation/dram/DramGDDR5X.h" +#include "DRAMSys/simulation/dram/DramGDDR6.h" +#include "DRAMSys/simulation/dram/DramSTTMRAM.h" + +#ifdef DDR5_SIM +#include "DRAMSys/simulation/dram/DramDDR5.h" +#endif +#ifdef LPDDR5_SIM +#include "DRAMSys/simulation/dram/DramLPDDR5.h" +#endif +#ifdef HBM3_SIM +#include "DRAMSys/simulation/dram/DramHBM3.h" +#endif + #include #include #include #include #include -#include "DRAMSys.h" -#include "../common/DebugManager.h" -#include "../common/utils.h" -#include "../simulation/TemperatureController.h" -#include "../error/ecchamming.h" -#include "dram/DramDDR3.h" -#include "dram/DramDDR4.h" -#include "dram/DramWideIO.h" -#include "dram/DramLPDDR4.h" -#include "dram/DramWideIO2.h" -#include "dram/DramHBM2.h" -#include "dram/DramGDDR5.h" -#include "dram/DramGDDR5X.h" -#include "dram/DramGDDR6.h" -#include "dram/DramSTTMRAM.h" -#include "../controller/Controller.h" - -#ifdef DDR5_SIM -#include -#endif -#ifdef LPDDR5_SIM -#include -#endif -#ifdef HBM3_SIM -#include "dram/DramHBM3.h" -#endif - namespace DRAMSys { -DRAMSys::DRAMSys(const sc_core::sc_module_name &name, - const ::DRAMSys::Config::Configuration &configLib) +DRAMSys::DRAMSys(const sc_core::sc_module_name& name, + const ::DRAMSys::Config::Configuration& configLib) : DRAMSys(name, configLib, true) {} -DRAMSys::DRAMSys(const sc_core::sc_module_name &name, - const ::DRAMSys::Config::Configuration &configLib, +DRAMSys::DRAMSys(const sc_core::sc_module_name& name, + const ::DRAMSys::Config::Configuration& configLib, bool initAndBind) : sc_module(name), tSocket("DRAMSys_tSocket") { @@ -91,9 +90,6 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name, config.loadMCConfig(configLib.mcConfig); config.loadSimConfig(configLib.simConfig); - if (const auto &thermalConfig = configLib.thermalConfig) - config.loadTemperatureSimConfig(*thermalConfig); - // Setup the debug manager: setupDebugManager(config.simulationName); @@ -146,7 +142,7 @@ void DRAMSys::logo() #undef BOLDTXT } -void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName)) const +void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string& traceName)) const { #ifndef NDEBUG auto& dbg = DebugManager::getInstance(); @@ -161,8 +157,6 @@ void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName)) con void DRAMSys::instantiateModules(const ::DRAMSys::Config::AddressMapping& addressMapping) { - temperatureController = std::make_unique("TemperatureController", config); - addressDecoder = std::make_unique(config, addressMapping); addressDecoder->print(); @@ -182,35 +176,25 @@ void DRAMSys::instantiateModules(const ::DRAMSys::Config::AddressMapping& addres *addressDecoder)); if (memoryType == MemSpec::MemoryType::DDR3) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::DDR4) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::WideIO) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::LPDDR4) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::WideIO2) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::HBM2) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::GDDR5) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::GDDR5X) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::GDDR6) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); else if (memoryType == MemSpec::MemoryType::STTMRAM) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config)); #ifdef DDR5_SIM else if (memoryType == MemSpec::MemoryType::DDR5) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, @@ -252,7 +236,7 @@ void DRAMSys::bindSockets() } } -void DRAMSys::report(const std::string &message) +void DRAMSys::report(const std::string& message) { PRINTDEBUGMESSAGE(name(), message); std::cout << message << std::endl; diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index 06d716f2..94ca9388 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -41,20 +41,20 @@ #ifndef DRAMSYS_H #define DRAMSYS_H -#include "dram/Dram.h" -#include "Arbiter.h" -#include "ReorderBuffer.h" -#include "../common/tlm2_base_protocol_checker.h" -#include "../error/eccbaseclass.h" -#include "../controller/ControllerIF.h" -#include "TemperatureController.h" -#include "AddressDecoder.h" +#include "DRAMSys/simulation/dram/Dram.h" +#include "DRAMSys/simulation/Arbiter.h" +#include "DRAMSys/simulation/ReorderBuffer.h" +#include "DRAMSys/common/tlm2_base_protocol_checker.h" +#include "DRAMSys/controller/ControllerIF.h" +#include "DRAMSys/simulation/AddressDecoder.h" + +#include "DRAMSys/config/DRAMSysConfiguration.h" -#include #include -#include #include #include +#include +#include #include #include @@ -66,22 +66,20 @@ public: tlm_utils::multi_passthrough_target_socket tSocket; SC_HAS_PROCESS(DRAMSys); - DRAMSys(const sc_core::sc_module_name &name, - const ::DRAMSys::Config::Configuration &configLib); + DRAMSys(const sc_core::sc_module_name& name, + const ::DRAMSys::Config::Configuration& configLib); const Configuration& getConfig(); protected: - DRAMSys(const sc_core::sc_module_name &name, - const ::DRAMSys::Config::Configuration &configLib, + DRAMSys(const sc_core::sc_module_name& name, + const ::DRAMSys::Config::Configuration& configLib, bool initAndBind); void end_of_simulation() override; Configuration config; - std::unique_ptr temperatureController; - //TLM 2.0 Protocol Checkers std::vector>> controllersTlmCheckers; @@ -99,15 +97,13 @@ protected: std::unique_ptr addressDecoder; - void report(const std::string &message); + void report(const std::string& message); void bindSockets(); private: static void logo(); - - void instantiateModules(const ::DRAMSys::Config::AddressMapping &addressMapping); - - void setupDebugManager(const std::string &traceName) const; + void instantiateModules(const ::DRAMSys::Config::AddressMapping& addressMapping); + void setupDebugManager(const std::string& traceName) const; }; } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp index 2cc2308b..52894b8d 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp @@ -34,38 +34,34 @@ * Derek Christ */ -#include - #include "DRAMSysRecordable.h" -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include +#include "DRAMSys/controller/ControllerRecordable.h" +#include "DRAMSys/common/TlmRecorder.h" +#include "DRAMSys/simulation/dram/DramRecordable.h" +#include "DRAMSys/simulation/dram/DramDDR3.h" +#include "DRAMSys/simulation/dram/DramDDR4.h" +#include "DRAMSys/simulation/dram/DramWideIO.h" +#include "DRAMSys/simulation/dram/DramLPDDR4.h" +#include "DRAMSys/simulation/dram/DramWideIO2.h" +#include "DRAMSys/simulation/dram/DramHBM2.h" +#include "DRAMSys/simulation/dram/DramGDDR5.h" +#include "DRAMSys/simulation/dram/DramGDDR5X.h" +#include "DRAMSys/simulation/dram/DramGDDR6.h" +#include "DRAMSys/simulation/dram/DramSTTMRAM.h" #ifdef DDR5_SIM -#include +#include "DRAMSys/simulation/dram/DramDDR5.h" #endif #ifdef LPDDR5_SIM -#include +#include "DRAMSys/simulation/dram/DramLPDDR5.h" #endif #ifdef HBM3_SIM -#include +#include "DRAMSys/simulation/dram/DramHBM3.h" #endif +#include + using namespace sc_core; DRAMSysRecordable::DRAMSysRecordable(const sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib) @@ -123,8 +119,6 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName, const :: void DRAMSysRecordable::instantiateModules(const std::string &traceName, const ::DRAMSys::Config::Configuration &configLib) { - temperatureController = std::make_unique("TemperatureController", config); - addressDecoder = std::make_unique(config, configLib.addressMapping); addressDecoder->print(); @@ -149,34 +143,34 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, if (memoryType == MemSpec::MemoryType::DDR3) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::DDR4) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::WideIO) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::LPDDR4) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::WideIO2) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::HBM2) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR5) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR5X) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR6) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::STTMRAM) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); + config, tlmRecorders[i])); #ifdef DDR5_SIM else if (memoryType == MemSpec::MemoryType::DDR5) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h index 8cf294a6..64eb636e 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h @@ -37,15 +37,15 @@ #ifndef DRAMSYSRECORDABLE_H #define DRAMSYSRECORDABLE_H -#include "DRAMSys.h" -#include "../common/TlmRecorder.h" +#include "DRAMSys/simulation/DRAMSys.h" +#include "DRAMSys/common/TlmRecorder.h" -#include +#include "DRAMSys/config/DRAMSysConfiguration.h" class DRAMSysRecordable : public DRAMSys::DRAMSys { public: - DRAMSysRecordable(const sc_core::sc_module_name &name, const ::DRAMSys::Config::Configuration &configLib); + DRAMSysRecordable(const sc_core::sc_module_name &name, const ::DRAMSys::Config::Configuration& configLib); protected: void end_of_simulation() override; @@ -55,8 +55,8 @@ private: // They generate the output databases. std::vector tlmRecorders; - void setupTlmRecorders(const std::string &traceName, const ::DRAMSys::Config::Configuration &configLib); - void instantiateModules(const std::string &traceName, const ::DRAMSys::Config::Configuration &configLib); + void setupTlmRecorders(const std::string &traceName, const ::DRAMSys::Config::Configuration& configLib); + void instantiateModules(const std::string &traceName, const ::DRAMSys::Config::Configuration& configLib); }; #endif // DRAMSYSRECORDABLE_H diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index 28e86492..a69bbaef 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -40,7 +40,6 @@ #include #include - #include #include #include @@ -63,55 +62,55 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; - std::deque pendingRequestsInOrder; - std::set receivedResponses; + std::deque pendingRequestsInOrder; + std::set receivedResponses; bool responseIsPendingInInitator; // Initiated by dram side - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, - sc_core::sc_time &bwDelay) + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + sc_core::sc_time& bwDelay) { - payloadEventQueue.notify(payload, phase, bwDelay); + payloadEventQueue.notify(trans, phase, bwDelay); return tlm::TLM_ACCEPTED; } // Initiated by initator side (players) - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, - sc_core::sc_time &fwDelay) + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, + sc_core::sc_time& fwDelay) { if (phase == tlm::BEGIN_REQ) { - payload.acquire(); + trans.acquire(); } else if (phase == tlm::END_RESP) { - payload.release(); + trans.release(); } - payloadEventQueue.notify(payload, phase, fwDelay); + payloadEventQueue.notify(trans, phase, fwDelay); return tlm::TLM_ACCEPTED; } - void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) + void peqCallback(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase) { //Phases initiated by initiator side if (phase == tlm::BEGIN_REQ) { - pendingRequestsInOrder.push_back(&payload); - sendToTarget(payload, phase, sc_core::SC_ZERO_TIME); + pendingRequestsInOrder.push_back(&trans); + sendToTarget(trans, phase, sc_core::SC_ZERO_TIME); } else if (phase == tlm::END_RESP) { responseIsPendingInInitator = false; pendingRequestsInOrder.pop_front(); - receivedResponses.erase(&payload); + receivedResponses.erase(&trans); sendNextResponse(); } //Phases initiated by dram side else if (phase == tlm::END_REQ) { - sendToInitiator(payload, phase, sc_core::SC_ZERO_TIME); + sendToInitiator(trans, phase, sc_core::SC_ZERO_TIME); } else if (phase == tlm::BEGIN_RESP) { - sendToTarget(payload, tlm::END_RESP, sc_core::SC_ZERO_TIME); - receivedResponses.emplace(&payload); + sendToTarget(trans, tlm::END_RESP, sc_core::SC_ZERO_TIME); + receivedResponses.emplace(&trans); sendNextResponse(); } @@ -122,24 +121,24 @@ private: } } - void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_core::sc_time &delay) + void sendToTarget(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay) { tlm::tlm_phase TPhase = phase; sc_core::sc_time TDelay = delay; - iSocket->nb_transport_fw(payload, TPhase, TDelay); + iSocket->nb_transport_fw(trans, TPhase, TDelay); } - void sendToInitiator(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_core::sc_time &delay) + void sendToInitiator(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase, const sc_core::sc_time& delay) { sc_assert(phase == tlm::END_REQ || - (phase == tlm::BEGIN_RESP && pendingRequestsInOrder.front() == &payload - && receivedResponses.count(&payload))); + (phase == tlm::BEGIN_RESP && pendingRequestsInOrder.front() == &trans + && receivedResponses.count(&trans))); tlm::tlm_phase TPhase = phase; sc_core::sc_time TDelay = delay; - tSocket->nb_transport_bw(payload, TPhase, TDelay); + tSocket->nb_transport_bw(trans, TPhase, TDelay); } void sendNextResponse() diff --git a/src/libdramsys/DRAMSys/simulation/TemperatureController.cpp b/src/libdramsys/DRAMSys/simulation/TemperatureController.cpp deleted file mode 100644 index 11087383..00000000 --- a/src/libdramsys/DRAMSys/simulation/TemperatureController.cpp +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2015, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Eder F. Zulian - * Matthias Jung - * Derek Christ - */ - -#include - -#include "TemperatureController.h" -#include - -using namespace sc_core; - -double TemperatureController::temperatureConvert(double tKelvin) -{ - if (temperatureScale == TemperatureSimConfig::TemperatureScale::Celsius) { - return tKelvin - 273.15; - } else if (temperatureScale == TemperatureSimConfig::TemperatureScale::Fahrenheit) { - return (tKelvin - 273.15) * 1.8 + 32; - } - - return tKelvin; -} - -double TemperatureController::getTemperature(int deviceId, float currentPower) -{ - PRINTDEBUGMESSAGE(name(), "Temperature requested by device " + std::to_string( - deviceId) + " current power is " + std::to_string(currentPower)); - - if (dynamicTempSimEnabled) - { - currentPowerValues.at(deviceId) = currentPower; - checkPowerThreshold(deviceId); - - // FIXME: using the static temperature value until the vector of temperatures is filled - if (temperatureValues.empty()) - return temperatureConvert(staticTemperature + 273.15); - - return temperatureConvert(temperatureValues.at(deviceId)); - } - else - { - PRINTDEBUGMESSAGE(name(), "Temperature is " + std::to_string(staticTemperature)); - return staticTemperature; - } -} - -void TemperatureController::updateTemperatures() -{ -#ifdef THERMALSIM - thermalSimulation->sendPowerValues(¤tPowerValues); - thermalSimulation->simulate(); - thermalSimulation->getTemperature(temperaturesBuffer, TDICE_OUTPUT_INSTANT_SLOT, - TDICE_OUTPUT_TYPE_TFLPEL, TDICE_OUTPUT_QUANTITY_AVERAGE); - - std::string mapfile; - sc_time ts = sc_time_stamp(); - if (genTempMap == true) { - mapfile = temperatureMapFile + "_" + std::to_string(ts.to_default_time_units()) - + ".txt"; - thermalSimulation->getTemperatureMap(mapfile); - } - if (genPowerMap == true) { - mapfile = powerMapFile + "_" + std::to_string(ts.to_default_time_units()) + - ".txt"; - thermalSimulation->getPowerMap(mapfile); - } -#endif - // Save values just obtained for posterior use - temperatureValues = temperaturesBuffer; - // Clear the buffer, otherwise it will grow every request - temperaturesBuffer.clear(); -} - -void TemperatureController::checkPowerThreshold(int deviceId) -{ - if (std::abs(lastPowerValues.at(deviceId) - currentPowerValues.at( - deviceId)) > powerThresholds.at(deviceId)) { - decreaseSimPeriod = true; - } - lastPowerValues.at(deviceId) = currentPowerValues.at(deviceId); -} - -double TemperatureController::adjustThermalSimPeriod() -{ - // Temperature Simulation Period Dynamic Adjustment - // - // 1. Adjustment is requierd when: - // - // 1.1. The power dissipation of one or more devices change considerably - // (exceeds the configured threshold for that device in any direction, - // i.e. increases or decreases substantially) during the current - // simulaiton period. - // - // 1.1.1. The simulation period will be reduced by a factor of 'n' so the - // simulation occurs 'n' times more often. - // - // 1.1.2. The step 1.1.1 will be repeated until the point that there are - // no sustantial changes in power dissipation between two consecutive - // executions of the thermal simulation, i.e. all changes for all devices - // are less than the configured threshold. - // - // 1.2. The current simulation period differs from the target period - // defined in the configuration by the user. - // - // 1.2.1 Provided a scenario in which power dissipation changes do not - // exceed the thresholds, the situation period will be kept for a number - // of simulation cycles 'nc' and after 'nc' the period will be increased - // again in steps of 'n/2' until it achieves the desired value given by - // configuration or the described in 1.1 occurs. - - if (decreaseSimPeriod) - { - period = period / periodAdjustFactor; - cyclesSinceLastPeriodAdjust = 0; - decreaseSimPeriod = false; - PRINTDEBUGMESSAGE(name(), "Thermal Simulation period reduced to " + std::to_string( - period) + ". Target is " + std::to_string(targetPeriod)); - } - else - { - if (period != targetPeriod) { - cyclesSinceLastPeriodAdjust++; - if (cyclesSinceLastPeriodAdjust >= nPowStableCyclesToIncreasePeriod) { - cyclesSinceLastPeriodAdjust = 0; - period = period * ((double)periodAdjustFactor / 2); - if (period > targetPeriod) - period = targetPeriod; - PRINTDEBUGMESSAGE(name(), "Thermal Simulation period increased to " - + std::to_string(period) + ". Target is " + std::to_string(targetPeriod)); - } - } - } - - return period; -} - -void TemperatureController::temperatureThread() -{ - while (true) - { - updateTemperatures(); - double p = adjustThermalSimPeriod(); - - NDEBUG_UNUSED(int i) = 0; - for (NDEBUG_UNUSED(auto t) : temperatureValues) { - PRINTDEBUGMESSAGE(name(), "Temperature[" + std::to_string(i++) - + "] is " + std::to_string(t)); - } - PRINTDEBUGMESSAGE(name(), "Thermal simulation period is " + std::to_string(p)); - - wait(sc_time(p, t_unit)); - } -} diff --git a/src/libdramsys/DRAMSys/simulation/TemperatureController.h b/src/libdramsys/DRAMSys/simulation/TemperatureController.h deleted file mode 100644 index 8bb7a183..00000000 --- a/src/libdramsys/DRAMSys/simulation/TemperatureController.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2015, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Eder F. Zulian - * Matthias Jung - * Derek Christ - */ - -#ifndef TEMPERATURECONTROLLER_H -#define TEMPERATURECONTROLLER_H - -#include - -#include -#include "../common/DebugManager.h" -#include "../common/utils.h" -#include - -#ifdef THERMALSIM -#include "IceWrapper.h" -#endif - -class TemperatureController : sc_core::sc_module -{ -public: - TemperatureController(const TemperatureController&) = delete; - TemperatureController& operator=(const TemperatureController&) = delete; - - SC_HAS_PROCESS(TemperatureController); - TemperatureController() = default; - TemperatureController(const sc_core::sc_module_name& name, const Configuration& config) : sc_core::sc_module(name) - { - temperatureScale = config.temperatureSim.temperatureScale; - dynamicTempSimEnabled = config.thermalSimulation; - staticTemperature = config.temperatureSim.staticTemperatureDefaultValue; - - if (dynamicTempSimEnabled) - { -#ifdef THERMALSIM - // Connect to the server - std::string ip = config.temperatureSim.iceServerIp; - unsigned int port = config.temperatureSim.iceServerPort; - thermalSimulation = new IceWrapper(ip, port); - PRINTDEBUGMESSAGE(name(), "Dynamic temperature simulation. Server @ " - + ip + ":" + std::to_string(port)); -#else - SC_REPORT_FATAL(sc_module::name(), - "DRAMSys was build without support to dynamic temperature simulation. Check the README file for further details."); -#endif - // Initial power dissipation values (got from config) - currentPowerValues = config.temperatureSim.powerInitialValues; - lastPowerValues = currentPowerValues; - - // Substantial changes in power will trigger adjustments in the simulaiton period. Get the thresholds from config. - powerThresholds = config.temperatureSim.powerThresholds; - decreaseSimPeriod = false; - periodAdjustFactor = config.temperatureSim.simPeriodAdjustFactor; - nPowStableCyclesToIncreasePeriod = config.temperatureSim.nPowStableCyclesToIncreasePeriod; - cyclesSinceLastPeriodAdjust = 0; - - // Get the target period for the thermal simulation from config. - targetPeriod = config.temperatureSim.thermalSimPeriod; - period = targetPeriod; - t_unit = config.temperatureSim.thermalSimUnit; - - genTempMap = config.temperatureSim.generateTemperatureMap; - temperatureMapFile = "temperature_map"; - std::system("rm -f temperature_map*"); - - genPowerMap = config.temperatureSim.generatePowerMap; - powerMapFile = "power_map"; - std::system("rm -f power_map*"); - - SC_THREAD(temperatureThread); - } - else - { - PRINTDEBUGMESSAGE(sc_module::name(), "Static temperature simulation. Temperature set to " + - std::to_string(staticTemperature)); - } - } - - double getTemperature(int deviceId, float currentPower); - -private: - TemperatureSimConfig::TemperatureScale temperatureScale; - double temperatureConvert(double tKelvin); - - double staticTemperature; - - bool dynamicTempSimEnabled; - -#ifdef THERMALSIM - IceWrapper *thermalSimulation; -#endif - std::vector temperaturesBuffer; - std::vector temperatureValues; - - std::vector currentPowerValues; - std::vector lastPowerValues; - std::vector powerThresholds; - - double targetPeriod; - double period; - enum sc_core::sc_time_unit t_unit; - void temperatureThread(); - void updateTemperatures(); - double adjustThermalSimPeriod(); - void checkPowerThreshold(int deviceId); - bool decreaseSimPeriod; - unsigned int periodAdjustFactor; - unsigned int cyclesSinceLastPeriodAdjust; - unsigned int nPowStableCyclesToIncreasePeriod; - - bool genTempMap; - std::string temperatureMapFile; - bool genPowerMap; - std::string powerMapFile; -}; - -#endif // TEMPERATURECONTROLLER_H - diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index 189d7c97..e94fdd66 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -37,31 +37,25 @@ * Felipe S. Prado */ -#ifdef _WIN32 - #include -#else - #include -#endif - -#include -#include -#include -#include -#include -#include -#include - #include "Dram.h" -#include "../../common/DebugManager.h" -#include "../../common/dramExtensions.h" -#include "../../common/utils.h" -#include "../../controller/Command.h" + +#include "DRAMSys/common/DebugManager.h" #ifdef DRAMPOWER #include "../../common/third_party/DRAMPower/src/MemCommand.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #endif +#include +#include +#include + +#ifdef _WIN32 + #include +#else + #include +#endif + using namespace sc_core; using namespace tlm; @@ -131,15 +125,14 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { assert(phase >= BEGIN_RD && phase <= END_SREF); +#ifdef DRAMPOWER if (powerAnalysis) { int bank = static_cast(ControllerExtension::getBank(payload).ID()); int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); - -#ifdef DRAMPOWER DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); -#endif } +#endif if (storeMode == Configuration::StoreMode::Store) { diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.h b/src/libdramsys/DRAMSys/simulation/dram/Dram.h index 7b0f66df..f9b339ce 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.h +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.h @@ -40,20 +40,20 @@ #ifndef DRAM_H #define DRAM_H -#include +#include "DRAMSys/configuration/Configuration.h" +#include "DRAMSys/configuration/memspec/MemSpec.h" +#include #include #include #include -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpec.h" class libDRAMPower; class Dram : public sc_core::sc_module { protected: - Dram(const sc_core::sc_module_name &name, const Configuration& config); + Dram(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(Dram); const MemSpec& memSpec; @@ -61,17 +61,17 @@ protected: // Data Storage: const Configuration::StoreMode storeMode; const bool powerAnalysis; - unsigned char *memory; + unsigned char* memory; const bool useMalloc; #ifdef DRAMPOWER std::unique_ptr DRAMPower; #endif - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_core::sc_time &delay); + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, + tlm::tlm_phase& phase, sc_core::sc_time& delay); - virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans); + virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans); public: tlm_utils::simple_target_socket tSocket; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp index 5ae93b05..3c9469f0 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp @@ -35,9 +35,7 @@ #include "DramDDR3.h" -#include -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecDDR3.h" +#include "DRAMSys/configuration/memspec/MemSpecDDR3.h" #ifdef DRAMPOWER #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" @@ -46,20 +44,16 @@ using namespace DRAMPower; using namespace sc_core; -DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); - +#ifdef DRAMPOWER if (powerAnalysis) { const auto *memSpecDDR3 = dynamic_cast(config.memSpec.get()); if (memSpecDDR3 == nullptr) SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); -#ifdef DRAMPOWER MemArchitectureSpec memArchSpec; memArchSpec.burstLength = memSpecDDR3->defaultBurstLength; memArchSpec.dataRate = memSpecDDR3->dataRate; @@ -147,6 +141,6 @@ DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config, powerSpec.memArchSpec = memArchSpec; DRAMPower = std::make_unique(powerSpec, false); -#endif } +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h index bfd2c172..ee9e6cf9 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h @@ -36,16 +36,14 @@ #ifndef DRAMDDR3_H #define DRAMDDR3_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramDDR3 : public Dram { public: - DramDDR3(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramDDR3(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramDDR3); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp index c358d0fe..998bb7e8 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp @@ -35,9 +35,7 @@ #include "DramDDR4.h" -#include -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecDDR4.h" +#include "DRAMSys/configuration/memspec/MemSpecDDR4.h" #ifdef DRAMPOWER #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" @@ -46,20 +44,16 @@ using namespace DRAMPower; using namespace sc_core; -DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); - +#ifdef DRAMPOWER if (powerAnalysis) { const auto *memSpecDDR4 = dynamic_cast(config.memSpec.get()); if (memSpecDDR4 == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); -#ifdef DRAMPOWER MemArchitectureSpec memArchSpec; memArchSpec.burstLength = memSpecDDR4->defaultBurstLength; memArchSpec.dataRate = memSpecDDR4->dataRate; @@ -147,6 +141,6 @@ DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config, powerSpec.memArchSpec = memArchSpec; DRAMPower = std::make_unique(powerSpec, false); -#endif } +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h index eeca3d29..d51d71e9 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h @@ -36,16 +36,14 @@ #ifndef DRAMDDR4_H #define DRAMDDR4_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramDDR4 : public Dram { public: - DramDDR4(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramDDR4(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramDDR4); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp index 2f6301c4..515aa9a7 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp @@ -33,19 +33,15 @@ * Lukas Steiner */ -#include "DramGDDR5.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecGDDR5.h" +#include "DRAMSys/simulation/dram/DramGDDR5.h" using namespace sc_core; -DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5"); - +#ifdef DRAMPOWER if (powerAnalysis) SC_REPORT_FATAL("DramGDDR5", "DRAMPower does not support GDDR5"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h index b5a12196..645dfbee 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h @@ -36,16 +36,14 @@ #ifndef DRAMGDDR5_H #define DRAMGDDR5_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramGDDR5 : public Dram { public: - DramGDDR5(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramGDDR5(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramGDDR5); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp index 377d515c..c1a3b334 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp @@ -34,18 +34,14 @@ */ #include "DramGDDR5X.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecGDDR5X.h" using namespace sc_core; -DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X"); - +#ifdef DRAMPOWER if (powerAnalysis) SC_REPORT_FATAL("DramGDDR5X", "DRAMPower does not support GDDR5X"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h index 5c8af942..bed8cc01 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h @@ -36,16 +36,14 @@ #ifndef DRAMGDDR5X_H #define DRAMGDDR5X_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramGDDR5X : public Dram { public: - DramGDDR5X(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramGDDR5X(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramGDDR5X); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp index 57b0df97..7a8d0a11 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp @@ -34,18 +34,14 @@ */ #include "DramGDDR6.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecGDDR6.h" using namespace sc_core; -DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6"); - +#ifdef DRAMPOWER if (powerAnalysis) SC_REPORT_FATAL("DramGDDR6", "DRAMPower does not support GDDR6"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h index cdffebee..f2c82249 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h @@ -36,16 +36,14 @@ #ifndef DRAMGDDR6_H #define DRAMGDDR6_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramGDDR6 : public Dram { public: - DramGDDR6(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramGDDR6(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramGDDR6); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp index 40f54d53..f5891399 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp @@ -34,18 +34,14 @@ */ #include "DramHBM2.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecHBM2.h" using namespace sc_core; -DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2"); - +#ifdef DRAMPOWER if (powerAnalysis) SC_REPORT_FATAL("DramHBM2", "DRAMPower does not support HBM2"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h index f78746b2..2789a245 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h @@ -36,16 +36,14 @@ #ifndef DRAMHBM2_H #define DRAMHBM2_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramHBM2 : public Dram { public: - DramHBM2(const sc_core::sc_module_name &name, const Configuration& config, - TemperatureController& temperatureController); + DramHBM2(const sc_core::sc_module_name &name, const Configuration& config); SC_HAS_PROCESS(DramHBM2); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM3.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramHBM3.cpp deleted file mode 100644 index 0fee7304..00000000 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM3.cpp +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2019, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#include "DramHBM3.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecHBM3.h" - -using namespace sc_core; - -DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) - : Dram(name, config) -{ - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramHBM3", "Error Model not supported for HBM3"); - - if (powerAnalysis) - SC_REPORT_FATAL("DramHBM3", "DRAMPower does not support HBM3"); -} diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM3.h b/src/libdramsys/DRAMSys/simulation/dram/DramHBM3.h deleted file mode 100644 index e1137002..00000000 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM3.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2019, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#ifndef DRAMHBM3_H -#define DRAMHBM3_H - -#include - -#include "Dram.h" -#include "../TemperatureController.h" - -class DramHBM3 : public Dram -{ -public: - DramHBM3(const sc_core::sc_module_name &name, const Configuration& config, - TemperatureController& temperatureController); - SC_HAS_PROCESS(DramHBM3); -}; - -#endif // DRAMHBM3_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp index e55cfdb0..0134fcf3 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp @@ -34,18 +34,14 @@ */ #include "DramLPDDR4.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecLPDDR4.h" using namespace sc_core; -DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4"); - +#ifdef DRAMPOWER if (powerAnalysis) SC_REPORT_FATAL("DramLPDDR4", "DRAMPower does not support LPDDR4"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h index 401c119b..94d93498 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h @@ -36,16 +36,14 @@ #ifndef DRAMLPDDR4_H #define DRAMLPDDR4_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramLPDDR4 : public Dram { public: - DramLPDDR4(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramLPDDR4(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramLPDDR4); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp index 83fe2e4d..95ab5efd 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp @@ -35,40 +35,36 @@ #include "DramRecordable.h" -#include - - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "DRAMSys/common/TlmRecorder.h" +#include "DRAMSys/common/utils.h" +#include "DRAMSys/simulation/dram/DramDDR3.h" +#include "DRAMSys/simulation/dram/DramDDR4.h" +#include "DRAMSys/simulation/dram/DramWideIO.h" +#include "DRAMSys/simulation/dram/DramLPDDR4.h" +#include "DRAMSys/simulation/dram/DramWideIO2.h" +#include "DRAMSys/simulation/dram/DramHBM2.h" +#include "DRAMSys/simulation/dram/DramGDDR5.h" +#include "DRAMSys/simulation/dram/DramGDDR5X.h" +#include "DRAMSys/simulation/dram/DramGDDR6.h" +#include "DRAMSys/simulation/dram/DramSTTMRAM.h" #ifdef DDR5_SIM -#include +#include "DRAMSys/simulation/dram/DramDDR5.h" #endif #ifdef LPDDR5_SIM -#include +#include "DRAMSys/simulation/dram/DramLPDDR5.h" #endif #ifdef HBM3_SIM -#include +#include "DRAMSys/simulation/dram/DramHBM3.h" #endif using namespace sc_core; using namespace tlm; -template +template DramRecordable::DramRecordable(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController, TlmRecorder& tlmRecorder) - : BaseDram(name, config, temperatureController), tlmRecorder(tlmRecorder), + TlmRecorder& tlmRecorder) + : BaseDram(name, config), tlmRecorder(tlmRecorder), powerWindowSize(config.memSpec->tCK * config.windowSize) { #ifdef DRAMPOWER @@ -79,7 +75,7 @@ DramRecordable::DramRecordable(const sc_module_name& name, const Confi #endif } -template +template void DramRecordable::reportPower() { BaseDram::reportPower(); @@ -90,18 +86,18 @@ void DramRecordable::reportPower() #endif } -template -tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, +template +tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload& trans, tlm_phase &phase, sc_time &delay) { - tlmRecorder.recordPhase(payload, phase, delay); - return BaseDram::nb_transport_fw(payload, phase, delay); + tlmRecorder.recordPhase(trans, phase, delay); + return BaseDram::nb_transport_fw(trans, phase, delay); } #ifdef DRAMPOWER // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for visualization purposes. -template +template void DramRecordable::powerWindow() { int64_t clkCycles = 0; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h index 517aedeb..7dac1e6b 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h @@ -36,29 +36,28 @@ #ifndef DRAMRECORDABLE_H #define DRAMRECORDABLE_H -#include -#include -#include "../../common/TlmRecorder.h" -#include "../../configuration/Configuration.h" -#include "../TemperatureController.h" +#include "DRAMSys/common/TlmRecorder.h" +#include "DRAMSys/configuration/Configuration.h" #ifdef DRAMPOWER #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #endif -template +#include +#include + +template class DramRecordable final : public BaseDram { public: - DramRecordable(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController, TlmRecorder& tlmRecorder); + DramRecordable(const sc_core::sc_module_name& name, const Configuration& config, TlmRecorder& tlmRecorder); SC_HAS_PROCESS(DramRecordable); void reportPower() override; private: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_core::sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) override; TlmRecorder& tlmRecorder; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp index c42de13e..d31c8fe1 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp @@ -34,18 +34,14 @@ */ #include "DramSTTMRAM.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecSTTMRAM.h" using namespace sc_core; -DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramSTTMRAM", "Error Model not supported for STT-MRAM"); - +#ifdef DRAMPOWER if (powerAnalysis) SC_REPORT_FATAL("DramSTTMRAM", "DRAMPower does not support STT-MRAM"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h index 33d3b3ef..647db1a0 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h @@ -36,16 +36,14 @@ #ifndef DRAMSTTMRAM_H #define DRAMSTTMRAM_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramSTTMRAM : public Dram { public: - DramSTTMRAM(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramSTTMRAM(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramSTTMRAM); }; diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp index 38e15eaa..309bae4c 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp @@ -38,7 +38,6 @@ #include "DramWideIO.h" #include "../../configuration/Configuration.h" -#include "../../error/errormodel.h" #include "../../configuration/memspec/MemSpecWideIO.h" #ifdef DRAMPOWER @@ -50,13 +49,12 @@ using namespace sc_core; using namespace tlm; -DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config) : Dram(name, config) { +#ifdef DRAMPOWER if (powerAnalysis) { -#ifdef DRAMPOWER const auto* memSpecWideIO = dynamic_cast(config.memSpec.get()); if (memSpecWideIO == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); @@ -148,75 +146,6 @@ DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config, powerSpec.memArchSpec = memArchSpec; DRAMPower = std::make_unique(powerSpec, false); - - - // For each bank in a channel a error Model is created: - if (storeMode == Configuration::StoreMode::ErrorModel) - { - for (unsigned i = 0; i < memSpec.banksPerChannel; i++) - { - std::string errorModelStr = "errorModel_bank" + std::to_string(i); - ememory.emplace_back(std::make_unique(errorModelStr.c_str(), config, - temperatureController, DRAMPower.get())); - } - } -#endif - } - else - { - if (storeMode == Configuration::StoreMode::ErrorModel) - { - for (unsigned i = 0; i < memSpec.banksPerChannel; i++) - { - std::string errorModelStr = "errorModel_bank" + std::to_string(i); - ememory.emplace_back(std::make_unique(errorModelStr.c_str(), config, - temperatureController)); - } - } - } -} - -tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay) -{ - assert(phase >= 5 && phase <= 19); - -#ifdef DRAMPOWER - if (powerAnalysis) - { - int bank = static_cast(ControllerExtension::getBank(payload).ID()); - int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); - DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } #endif - - if (storeMode == Configuration::StoreMode::Store) - { - if (phase == BEGIN_RD || phase == BEGIN_RDA) - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - else if (phase == BEGIN_WR || phase == BEGIN_WRA) - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } - } - else if (storeMode == Configuration::StoreMode::ErrorModel) - { - // TODO: delay should be considered here! - unsigned bank = ControllerExtension::getBank(payload).ID(); - - if (phase == BEGIN_ACT) - ememory[bank]->activate(ControllerExtension::getRow(payload).ID()); - else if (phase == BEGIN_RD || phase == BEGIN_RDA) - ememory[bank]->load(payload); - else if (phase == BEGIN_WR || phase == BEGIN_WRA) - ememory[bank]->store(payload); - else if (phase == BEGIN_REFAB) - ememory[bank]->refresh(ControllerExtension::getRow(payload).ID()); - } - - return TLM_ACCEPTED; } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h index 00985c0e..523d2e30 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h @@ -36,28 +36,15 @@ #ifndef DRAMWIDEIO_H #define DRAMWIDEIO_H -#include -#include +#include "DRAMSys/simulation/dram/Dram.h" #include -#include -#include "Dram.h" -#include "../../error/errormodel.h" -#include "../TemperatureController.h" class DramWideIO : public Dram { public: - DramWideIO(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramWideIO(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramWideIO); - -protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_core::sc_time &delay) override; - -private: - std::vector> ememory; }; #endif // DRAMWIDEIO_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp index 80a02955..a2d85c70 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp @@ -34,18 +34,14 @@ */ #include "DramWideIO2.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/memspec/MemSpecWideIO2.h" using namespace sc_core; -DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController) +DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config) : Dram(name, config) { - if (storeMode == Configuration::StoreMode::ErrorModel) - SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2"); - +#ifdef DRAMPOWER if (config.powerAnalysis) SC_REPORT_FATAL("DramWideIO2", "DRAMPower does not support WideIO2"); +#endif } diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h index 524fb843..9ba5329a 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h @@ -36,16 +36,14 @@ #ifndef DRAMWIDEIO2_H #define DRAMWIDEIO2_H -#include +#include "DRAMSys/simulation/dram/Dram.h" -#include "Dram.h" -#include "../TemperatureController.h" +#include class DramWideIO2 : public Dram { public: - DramWideIO2(const sc_core::sc_module_name& name, const Configuration& config, - TemperatureController& temperatureController); + DramWideIO2(const sc_core::sc_module_name& name, const Configuration& config); SC_HAS_PROCESS(DramWideIO2); }; diff --git a/src/libdramsys/sources.lst b/src/libdramsys/sources.lst deleted file mode 100644 index e60bea4d..00000000 --- a/src/libdramsys/sources.lst +++ /dev/null @@ -1,195 +0,0 @@ -set(SOURCE_FILES - DRAMSys/common/DebugManager.cpp - DRAMSys/common/dramExtensions.cpp - DRAMSys/common/TlmRecorder.cpp - DRAMSys/common/tlm2_base_protocol_checker.h - DRAMSys/common/utils.cpp - - DRAMSys/configuration/memspec/MemSpec.cpp - DRAMSys/configuration/memspec/MemSpecDDR3.cpp - DRAMSys/configuration/memspec/MemSpecDDR4.cpp - DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp - DRAMSys/configuration/memspec/MemSpecWideIO.cpp - DRAMSys/configuration/memspec/MemSpecWideIO2.cpp - DRAMSys/configuration/memspec/MemSpecGDDR5.cpp - DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp - DRAMSys/configuration/memspec/MemSpecGDDR6.cpp - DRAMSys/configuration/memspec/MemSpecHBM2.cpp - DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp - DRAMSys/configuration/Configuration.cpp - DRAMSys/configuration/TemperatureSimConfig.h - - DRAMSys/simulation/DRAMSysRecordable.cpp - DRAMSys/simulation/dram/DramRecordable.cpp - - DRAMSys/controller/BankMachine.cpp - DRAMSys/controller/Command.cpp - DRAMSys/controller/ControllerIF.h - DRAMSys/controller/ControllerRecordable.cpp - DRAMSys/controller/Controller.cpp - - DRAMSys/controller/checker/CheckerIF.h - DRAMSys/controller/checker/CheckerDDR3.cpp - DRAMSys/controller/checker/CheckerDDR4.cpp - DRAMSys/controller/checker/CheckerLPDDR4.cpp - DRAMSys/controller/checker/CheckerWideIO.cpp - DRAMSys/controller/checker/CheckerWideIO2.cpp - DRAMSys/controller/checker/CheckerGDDR5.cpp - DRAMSys/controller/checker/CheckerGDDR5X.cpp - DRAMSys/controller/checker/CheckerGDDR6.cpp - DRAMSys/controller/checker/CheckerHBM2.cpp - DRAMSys/controller/checker/CheckerSTTMRAM.cpp - - DRAMSys/controller/cmdmux/CmdMuxIF.h - DRAMSys/controller/cmdmux/CmdMuxOldest.cpp - DRAMSys/controller/cmdmux/CmdMuxStrict.cpp - - DRAMSys/controller/powerdown/PowerDownManagerIF.h - DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp - DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp - - DRAMSys/controller/refresh/RefreshManagerIF.h - DRAMSys/controller/refresh/RefreshManagerDummy.cpp - DRAMSys/controller/refresh/RefreshManagerAllBank.cpp - DRAMSys/controller/refresh/RefreshManagerPerBank.cpp - DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp - DRAMSys/controller/refresh/RefreshManagerSameBank.cpp - - DRAMSys/controller/respqueue/RespQueueIF.h - DRAMSys/controller/respqueue/RespQueueFifo.cpp - DRAMSys/controller/respqueue/RespQueueReorder.cpp - - DRAMSys/controller/scheduler/SchedulerIF.h - DRAMSys/controller/scheduler/SchedulerFifo.cpp - DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp - DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp - DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp - DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp - - DRAMSys/controller/scheduler/BufferCounterIF.h - DRAMSys/controller/scheduler/BufferCounterBankwise.cpp - DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp - DRAMSys/controller/scheduler/BufferCounterShared.cpp - - DRAMSys/error/eccbaseclass.cpp - DRAMSys/error/ecchamming.cpp - DRAMSys/error/errormodel.cpp - - DRAMSys/error/ECC/Bit.cpp - DRAMSys/error/ECC/ECC.cpp - DRAMSys/error/ECC/Word.cpp - - DRAMSys/simulation/Arbiter.cpp - DRAMSys/simulation/AddressDecoder.cpp - DRAMSys/simulation/DRAMSys.cpp - DRAMSys/simulation/ReorderBuffer.h - DRAMSys/simulation/TemperatureController.cpp - - DRAMSys/simulation/dram/Dram.cpp - DRAMSys/simulation/dram/DramDDR3.cpp - DRAMSys/simulation/dram/DramDDR4.cpp - DRAMSys/simulation/dram/DramLPDDR4.cpp - DRAMSys/simulation/dram/DramWideIO.cpp - DRAMSys/simulation/dram/DramWideIO2.cpp - DRAMSys/simulation/dram/DramGDDR5.cpp - DRAMSys/simulation/dram/DramGDDR5X.cpp - DRAMSys/simulation/dram/DramGDDR6.cpp - DRAMSys/simulation/dram/DramHBM2.cpp - DRAMSys/simulation/dram/DramSTTMRAM.cpp -) - -set(HEADER_FILES - DRAMSys/common/DebugManager.h - DRAMSys/common/dramExtensions.h - DRAMSys/common/tlm2_base_protocol_checker.h - DRAMSys/common/utils.h - - DRAMSys/configuration/Configuration.h - DRAMSys/configuration/TemperatureSimConfig.h - - DRAMSys/configuration/memspec/MemSpec.h - DRAMSys/configuration/memspec/MemSpecDDR3.h - DRAMSys/configuration/memspec/MemSpecDDR4.h - DRAMSys/configuration/memspec/MemSpecLPDDR4.h - DRAMSys/configuration/memspec/MemSpecWideIO.h - DRAMSys/configuration/memspec/MemSpecWideIO2.h - DRAMSys/configuration/memspec/MemSpecGDDR5.h - DRAMSys/configuration/memspec/MemSpecGDDR5X.h - DRAMSys/configuration/memspec/MemSpecGDDR6.h - DRAMSys/configuration/memspec/MemSpecHBM2.h - DRAMSys/configuration/memspec/MemSpecSTTMRAM.h - - DRAMSys/controller/BankMachine.h - DRAMSys/controller/Command.h - DRAMSys/controller/ControllerIF.h - DRAMSys/controller/Controller.h - - DRAMSys/controller/checker/CheckerIF.h - DRAMSys/controller/checker/CheckerDDR3.h - DRAMSys/controller/checker/CheckerDDR4.h - DRAMSys/controller/checker/CheckerLPDDR4.h - DRAMSys/controller/checker/CheckerWideIO.h - DRAMSys/controller/checker/CheckerWideIO2.h - DRAMSys/controller/checker/CheckerGDDR5.h - DRAMSys/controller/checker/CheckerGDDR5X.h - DRAMSys/controller/checker/CheckerGDDR6.h - DRAMSys/controller/checker/CheckerHBM2.h - DRAMSys/controller/checker/CheckerSTTMRAM.h - - DRAMSys/controller/cmdmux/CmdMuxIF.h - DRAMSys/controller/cmdmux/CmdMuxOldest.h - DRAMSys/controller/cmdmux/CmdMuxStrict.h - - DRAMSys/controller/powerdown/PowerDownManagerIF.h - DRAMSys/controller/powerdown/PowerDownManagerDummy.h - DRAMSys/controller/powerdown/PowerDownManagerStaggered.h - - DRAMSys/controller/refresh/RefreshManagerIF.h - DRAMSys/controller/refresh/RefreshManagerDummy.h - DRAMSys/controller/refresh/RefreshManagerAllBank.h - DRAMSys/controller/refresh/RefreshManagerPerBank.h - DRAMSys/controller/refresh/RefreshManagerPer2Bank.h - DRAMSys/controller/refresh/RefreshManagerSameBank.h - - DRAMSys/controller/respqueue/RespQueueIF.h - DRAMSys/controller/respqueue/RespQueueFifo.h - DRAMSys/controller/respqueue/RespQueueReorder.h - - DRAMSys/controller/scheduler/SchedulerIF.h - DRAMSys/controller/scheduler/SchedulerFifo.h - DRAMSys/controller/scheduler/SchedulerFrFcfs.h - DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h - DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h - DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h - - DRAMSys/controller/scheduler/BufferCounterIF.h - DRAMSys/controller/scheduler/BufferCounterBankwise.h - DRAMSys/controller/scheduler/BufferCounterReadWrite.h - DRAMSys/controller/scheduler/BufferCounterShared.h - - DRAMSys/error/eccbaseclass.h - DRAMSys/error/ecchamming.h - DRAMSys/error/errormodel.h - - DRAMSys/error/ECC/Bit.h - DRAMSys/error/ECC/ECC.h - DRAMSys/error/ECC/Word.h - - DRAMSys/simulation/Arbiter.h - DRAMSys/simulation/AddressDecoder.h - DRAMSys/simulation/DRAMSys.h - DRAMSys/simulation/ReorderBuffer.h - DRAMSys/simulation/TemperatureController.h - - DRAMSys/simulation/dram/Dram.h - DRAMSys/simulation/dram/DramDDR3.h - DRAMSys/simulation/dram/DramDDR4.h - DRAMSys/simulation/dram/DramLPDDR4.h - DRAMSys/simulation/dram/DramWideIO.h - DRAMSys/simulation/dram/DramWideIO2.h - DRAMSys/simulation/dram/DramGDDR5.h - DRAMSys/simulation/dram/DramGDDR5X.h - DRAMSys/simulation/dram/DramGDDR6.h - DRAMSys/simulation/dram/DramHBM2.h - DRAMSys/simulation/dram/DramSTTMRAM.h -) \ No newline at end of file diff --git a/src/simulator/CMakeLists.txt b/src/simulator/CMakeLists.txt index eb0dd1c2..7a798552 100644 --- a/src/simulator/CMakeLists.txt +++ b/src/simulator/CMakeLists.txt @@ -53,6 +53,7 @@ endif() target_link_libraries(DRAMSys PRIVATE Threads::Threads + SystemC::systemc DRAMSys::libdramsys ) diff --git a/src/simulator/simulator/MemoryManager.h b/src/simulator/simulator/MemoryManager.h index 8296d8b1..31179c10 100644 --- a/src/simulator/simulator/MemoryManager.h +++ b/src/simulator/simulator/MemoryManager.h @@ -45,7 +45,7 @@ class MemoryManager : public tlm::tlm_mm_interface { public: - MemoryManager(bool storageEnabled); + explicit MemoryManager(bool storageEnabled); ~MemoryManager() override; tlm::tlm_generic_payload& allocate(unsigned dataLength); void free(tlm::tlm_generic_payload* payload) override; diff --git a/src/simulator/simulator/TrafficGenerator.h b/src/simulator/simulator/TrafficGenerator.h index 4b72fb84..4176cbee 100644 --- a/src/simulator/simulator/TrafficGenerator.h +++ b/src/simulator/simulator/TrafficGenerator.h @@ -39,13 +39,13 @@ #ifndef TRAFFICGENERATOR_H #define TRAFFICGENERATOR_H -#include "TrafficInitiator.h" -#include "TraceSetup.h" - #include #include #include +#include +#include + class TrafficGeneratorIf : public TrafficInitiator { public: diff --git a/src/simulator/simulator/TrafficInitiator.cpp b/src/simulator/simulator/TrafficInitiator.cpp index d0829e8e..ca24082b 100644 --- a/src/simulator/simulator/TrafficInitiator.cpp +++ b/src/simulator/simulator/TrafficInitiator.cpp @@ -38,7 +38,6 @@ */ #include "TrafficInitiator.h" -#include "TraceSetup.h" using namespace sc_core; using namespace tlm; diff --git a/src/simulator/simulator/TrafficInitiator.h b/src/simulator/simulator/TrafficInitiator.h index 202505e0..00324649 100644 --- a/src/simulator/simulator/TrafficInitiator.h +++ b/src/simulator/simulator/TrafficInitiator.h @@ -52,7 +52,7 @@ #include #include -#include "TraceSetup.h" +#include class TrafficInitiator : public sc_core::sc_module { diff --git a/src/simulator/main.cpp b/src/simulator/simulator/main.cpp similarity index 100% rename from src/simulator/main.cpp rename to src/simulator/simulator/main.cpp diff --git a/src/util/DRAMSys/util/json.h b/src/util/DRAMSys/util/json.h index 471b0990..7270acca 100644 --- a/src/util/DRAMSys/util/json.h +++ b/src/util/DRAMSys/util/json.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Technische Universität Kaiserslautern + * Copyright (c) 2021, Technische Universität Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without