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Minor refactor.

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This commit is contained in:
Lukas Steiner
2023-03-22 10:44:48 +01:00
parent 04ca902cf4
commit d18778a40a
2 changed files with 23 additions and 28 deletions
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47
src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
View File

@@ -83,7 +83,8 @@ Dram::Dram(const sc_module_name& name, const Configuration& config)
SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported");
memory = 0; // FIXME
#else
memory = (unsigned char *)mmap(nullptr, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
memory = (unsigned char *)mmap(nullptr, channelSize,
PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
#endif
}
}
@@ -121,15 +122,14 @@ void Dram::reportPower()
#endif
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay)
{
assert(phase >= BEGIN_RD && phase <= END_SREF);
#ifdef DRAMPOWER
if (powerAnalysis)
{
int bank = static_cast<int>(ControllerExtension::getBank(payload).ID());
int bank = static_cast<int>(ControllerExtension::getBank(trans).ID());
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}
@@ -139,40 +139,39 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
if (phase == BEGIN_RD || phase == BEGIN_RDA)
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
unsigned char* phyAddr = memory + trans.get_address();
memcpy(trans.get_data_ptr(), phyAddr, trans.get_data_length());
}
else if (phase == BEGIN_WR || phase == BEGIN_WRA)
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
unsigned char* phyAddr = memory + trans.get_address();
memcpy(phyAddr, trans.get_data_ptr(), trans.get_data_length());
}
}
return TLM_ACCEPTED;
}
unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
unsigned int Dram::transport_dbg(tlm_generic_payload& trans)
{
PRINTDEBUGMESSAGE(name(), "transport_dgb");
// TODO: This part is not tested yet, neither with traceplayers nor with GEM5 coupling
if (storeMode == Configuration::StoreMode::NoStorage)
{
SC_REPORT_FATAL("DRAM",
"Debug Transport is used in combination with NoStorage");
SC_REPORT_FATAL("DRAM", "Debug Transport is used in combination with NoStorage");
}
else
{
tlm_command cmd = trans.get_command();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if (cmd == TLM_READ_COMMAND)
{
if (storeMode == Configuration::StoreMode::Store)
{
unsigned char *phyAddr = memory + trans.get_address();
unsigned char* phyAddr = memory + trans.get_address();
memcpy(ptr, phyAddr, trans.get_data_length());
}
else
@@ -185,7 +184,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
{
if (storeMode == Configuration::StoreMode::Store)
{
unsigned char *phyAddr = memory + trans.get_address();
unsigned char* phyAddr = memory + trans.get_address();
memcpy(phyAddr, ptr, trans.get_data_length());
}
else
@@ -199,7 +198,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
return 0;
}
void Dram::b_transport(tlm_generic_payload &trans, sc_time &delay)
void Dram::b_transport(tlm_generic_payload& trans, sc_time& delay)
{
static bool printedWarning = false;
@@ -211,19 +210,15 @@ void Dram::b_transport(tlm_generic_payload &trans, sc_time &delay)
if (storeMode == Configuration::StoreMode::Store)
{
tlm_command cmd = trans.get_command();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if (cmd == TLM_READ_COMMAND)
if (trans.is_read())
{
unsigned char *phyAddr = memory + trans.get_address();
memcpy(ptr, phyAddr, trans.get_data_length());
unsigned char* phyAddr = memory + trans.get_address();
memcpy(trans.get_data_ptr(), phyAddr, trans.get_data_length());
}
else if (cmd == TLM_WRITE_COMMAND)
else
{
unsigned char *phyAddr = memory + trans.get_address();
memcpy(phyAddr, ptr, trans.get_data_length());
unsigned char* phyAddr = memory + trans.get_address();
memcpy(phyAddr, trans.get_data_ptr(), trans.get_data_length());
}
}
else if (storeMode != Configuration::StoreMode::NoStorage)

4
src/libdramsys/DRAMSys/simulation/dram/Dram.h
View File

@@ -69,9 +69,9 @@ protected:
std::unique_ptr<libDRAMPower> DRAMPower;
#endif
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload,
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_core::sc_time& delay);
virtual void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& delay);
virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
public: