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Refactor configuration library

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The configuration library has been refactored to make use of nlohmann
macros to reduce boilerplate code.
The nlohmann parser callback is used to decide whether to include
configuration json objects directly, or if they need to be loaded
from a sperate file.
This commit is contained in:
Derek Christ
2022-12-16 12:39:47 +01:00
parent a95db95030
commit d27a29ca80
50 changed files with 2194 additions and 1711 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
extensions/apps/traceAnalyzer/simulationdialog.cpp
View File

@@ -217,7 +217,7 @@ void SimulationDialog::saveConfiguration(QFile &file)
loadConfigurationFromTextFields();
std::string dump = DRAMSys::Config::dump(configuration, 4);
std::string dump = nlohmann::json(configuration).dump(4);
out << dump.c_str();
}
@@ -252,13 +252,13 @@ void SimulationDialog::loadConfigurationFromTextFields()
try
{
from_dump(ui->addressMappingTextEdit->toPlainText().toStdString(), addressMapping);
from_dump(ui->mcConfigTextEdit->toPlainText().toStdString(), mcConfig);
from_dump(ui->memSpecTextEdit->toPlainText().toStdString(), memSpec);
from_dump(ui->simConfigTextEdit->toPlainText().toStdString(), simConfig);
nlohmann::json::parse(ui->addressMappingTextEdit->toPlainText().toStdString()).get_to(addressMapping);
nlohmann::json::parse(ui->mcConfigTextEdit->toPlainText().toStdString()).get_to(mcConfig);
nlohmann::json::parse(ui->memSpecTextEdit->toPlainText().toStdString()).get_to(memSpec);
nlohmann::json::parse(ui->simConfigTextEdit->toPlainText().toStdString()).get_to(simConfig);
if (!ui->traceSetupTextEdit->toPlainText().toStdString().empty())
from_dump(ui->traceSetupTextEdit->toPlainText().toStdString(), traceSetup);
nlohmann::json::parse(ui->traceSetupTextEdit->toPlainText().toStdString()).get_to(traceSetup);
}
catch (const std::exception &e)
{
@@ -300,9 +300,9 @@ void SimulationDialog::loadConfiguration()
{
ui->simulationIdLabel->setEnabled(true);
ui->simulationId->setEnabled(true);
ui->simulationId->setText(configuration.simulationId.c_str());
ui->simulationId->setText(configuration.simulationid.c_str());
ui->simulationIdLineEdit->setText(configuration.simulationId.c_str());
ui->simulationIdLineEdit->setText(configuration.simulationid.c_str());
loadSimConfig();
loadMcConfig();
@@ -316,7 +316,7 @@ void SimulationDialog::loadSimConfig()
{
ui->simConfigTextEdit->clear();
std::string dump = DRAMSys::Config::dump(configuration.simConfig, 4);
std::string dump = nlohmann::json(configuration.simconfig).dump(4);
ui->simConfigTextEdit->setText(dump.c_str());
}
@@ -324,7 +324,7 @@ void SimulationDialog::loadMcConfig()
{
ui->mcConfigTextEdit->clear();
std::string dump = DRAMSys::Config::dump(configuration.mcConfig, 4);
std::string dump = nlohmann::json(configuration.mcconfig).dump(4);
ui->mcConfigTextEdit->setText(dump.c_str());
}
@@ -332,7 +332,7 @@ void SimulationDialog::loadMemSpec()
{
ui->memSpecTextEdit->clear();
std::string dump = DRAMSys::Config::dump(configuration.memSpec, 4);
std::string dump = nlohmann::json(configuration.memspec).dump(4);
ui->memSpecTextEdit->setText(dump.c_str());
}
@@ -340,7 +340,7 @@ void SimulationDialog::loadAddressMapping()
{
ui->addressMappingTextEdit->clear();
std::string dump = DRAMSys::Config::dump(configuration.addressMapping, 4);
std::string dump = nlohmann::json(configuration.addressmapping).dump(4);
ui->addressMappingTextEdit->setText(dump.c_str());
}
@@ -348,9 +348,9 @@ void SimulationDialog::loadTraceSetup()
{
ui->traceSetupTextEdit->clear();
if (const auto &traceSetup = configuration.traceSetup)
if (const auto &traceSetup = configuration.tracesetup)
{
std::string dump = DRAMSys::Config::dump(*traceSetup, 4);
std::string dump = nlohmann::json(*traceSetup).dump(4);
ui->traceSetupTextEdit->setText(dump.c_str());
}
}
@@ -359,7 +359,7 @@ void SimulationDialog::loadPreview()
{
ui->previewTextEdit->clear();
std::string dump = DRAMSys::Config::dump(configuration, 4);
std::string dump = nlohmann::json(configuration).dump(4);
ui->previewTextEdit->setText(dump.c_str());
}
@@ -372,7 +372,7 @@ QFileInfoList SimulationDialog::getSimulationResults()
for (const auto &fileInfo : baseDir.entryInfoList())
{
if (fileInfo.baseName().startsWith(configuration.simulationId.c_str()))
if (fileInfo.baseName().startsWith(configuration.simulationid.c_str()))
{
// Dont open tracefiles that are older than a few seconds
if (fileInfo.metadataChangeTime().secsTo(QDateTime::currentDateTime()) > 30)

140
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -45,80 +45,80 @@ using namespace tlm;
MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR5,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
dimmRanksPerChannel(memSpec.memArchitectureSpec.entries.at("nbrOfDIMMRanks")),
physicalRanksPerDimmRank(memSpec.memArchitectureSpec.entries.at("nbrOfPhysicalRanks")),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
dimmRanksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfDIMMRanks")),
physicalRanksPerDimmRank(memSpec.memarchitecturespec.entries.at("nbrOfPhysicalRanks")),
physicalRanksPerChannel(physicalRanksPerDimmRank * dimmRanksPerChannel),
logicalRanksPerPhysicalRank(memSpec.memArchitectureSpec.entries.at("nbrOfLogicalRanks")),
logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.entries.at("nbrOfLogicalRanks")),
logicalRanksPerChannel(logicalRanksPerPhysicalRank * physicalRanksPerChannel),
cmdMode(memSpec.memArchitectureSpec.entries.at("cmdMode")),
refMode(memSpec.memArchitectureSpec.entries.at("refMode")),
RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")),
RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
cmdMode(memSpec.memarchitecturespec.entries.at("cmdMode")),
refMode(memSpec.memarchitecturespec.entries.at("refMode")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAACDR(memSpec.memarchitecturespec.entries.at("RAACDR")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tRAS + tRP),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRPRE (tCK * memSpec.memTimingSpec.entries.at("RPRE")),
tRPST (tCK * memSpec.memTimingSpec.entries.at("RPST")),
tRDDQS (tCK * memSpec.memTimingSpec.entries.at("RDDQS")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")),
tWPST (tCK * memSpec.memTimingSpec.entries.at("WPST")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tCCD_L_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_slr")),
tCCD_L_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR_slr")),
tCCD_L_WR2_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR2_slr")),
tCCD_M_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_M_slr")),
tCCD_M_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_M_WR_slr")),
tCCD_S_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_slr")),
tCCD_S_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_WR_slr")),
tCCD_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_dlr")),
tCCD_WR_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_WR_dlr")),
tCCD_WR_dpr (tCK * memSpec.memTimingSpec.entries.at("CCD_WR_dpr")),
tRRD_L_slr (tCK * memSpec.memTimingSpec.entries.at("RRD_L_slr")),
tRRD_S_slr (tCK * memSpec.memTimingSpec.entries.at("RRD_S_slr")),
tRRD_dlr (tCK * memSpec.memTimingSpec.entries.at("RRD_dlr")),
tFAW_slr (tCK * memSpec.memTimingSpec.entries.at("FAW_slr")),
tFAW_dlr (tCK * memSpec.memTimingSpec.entries.at("FAW_dlr")),
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
tWTR_M (tCK * memSpec.memTimingSpec.entries.at("WTR_M")),
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
tRFC_slr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_slr")
: tCK * memSpec.memTimingSpec.entries.at("RFC2_slr")),
tRFC_dlr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dlr")
: tCK * memSpec.memTimingSpec.entries.at("RFC2_dlr")),
tRFC_dpr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dpr")
: tCK * memSpec.memTimingSpec.entries.at("RFC2_dpr")),
tRFCsb_slr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_slr")),
tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_dlr")),
tREFI ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("REFI1")
: tCK * memSpec.memTimingSpec.entries.at("REFI2")),
tREFIsb (tCK * memSpec.memTimingSpec.entries.at("REFISB")),
tREFSBRD_slr (tCK * memSpec.memTimingSpec.entries.at("REFSBRD_slr")),
tREFSBRD_dlr (tCK * memSpec.memTimingSpec.entries.at("REFSBRD_dlr")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
tCPDED (tCK * memSpec.memTimingSpec.entries.at("CPDED")),
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRPRE (tCK * memSpec.memtimingspec.entries.at("RPRE")),
tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")),
tRDDQS (tCK * memSpec.memtimingspec.entries.at("RDDQS")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWPRE (tCK * memSpec.memtimingspec.entries.at("WPRE")),
tWPST (tCK * memSpec.memtimingspec.entries.at("WPST")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tCCD_L_slr (tCK * memSpec.memtimingspec.entries.at("CCD_L_slr")),
tCCD_L_WR_slr (tCK * memSpec.memtimingspec.entries.at("CCD_L_WR_slr")),
tCCD_L_WR2_slr (tCK * memSpec.memtimingspec.entries.at("CCD_L_WR2_slr")),
tCCD_M_slr (tCK * memSpec.memtimingspec.entries.at("CCD_M_slr")),
tCCD_M_WR_slr (tCK * memSpec.memtimingspec.entries.at("CCD_M_WR_slr")),
tCCD_S_slr (tCK * memSpec.memtimingspec.entries.at("CCD_S_slr")),
tCCD_S_WR_slr (tCK * memSpec.memtimingspec.entries.at("CCD_S_WR_slr")),
tCCD_dlr (tCK * memSpec.memtimingspec.entries.at("CCD_dlr")),
tCCD_WR_dlr (tCK * memSpec.memtimingspec.entries.at("CCD_WR_dlr")),
tCCD_WR_dpr (tCK * memSpec.memtimingspec.entries.at("CCD_WR_dpr")),
tRRD_L_slr (tCK * memSpec.memtimingspec.entries.at("RRD_L_slr")),
tRRD_S_slr (tCK * memSpec.memtimingspec.entries.at("RRD_S_slr")),
tRRD_dlr (tCK * memSpec.memtimingspec.entries.at("RRD_dlr")),
tFAW_slr (tCK * memSpec.memtimingspec.entries.at("FAW_slr")),
tFAW_dlr (tCK * memSpec.memtimingspec.entries.at("FAW_dlr")),
tWTR_L (tCK * memSpec.memtimingspec.entries.at("WTR_L")),
tWTR_M (tCK * memSpec.memtimingspec.entries.at("WTR_M")),
tWTR_S (tCK * memSpec.memtimingspec.entries.at("WTR_S")),
tRFC_slr ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_slr")
: tCK * memSpec.memtimingspec.entries.at("RFC2_slr")),
tRFC_dlr ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dlr")
: tCK * memSpec.memtimingspec.entries.at("RFC2_dlr")),
tRFC_dpr ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dpr")
: tCK * memSpec.memtimingspec.entries.at("RFC2_dpr")),
tRFCsb_slr (tCK * memSpec.memtimingspec.entries.at("RFCsb_slr")),
tRFCsb_dlr (tCK * memSpec.memtimingspec.entries.at("RFCsb_dlr")),
tREFI ((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("REFI1")
: tCK * memSpec.memtimingspec.entries.at("REFI2")),
tREFIsb (tCK * memSpec.memtimingspec.entries.at("REFISB")),
tREFSBRD_slr (tCK * memSpec.memtimingspec.entries.at("REFSBRD_slr")),
tREFSBRD_dlr (tCK * memSpec.memtimingspec.entries.at("REFSBRD_dlr")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
tCPDED (tCK * memSpec.memtimingspec.entries.at("CPDED")),
tPD (tCK * memSpec.memtimingspec.entries.at("PD")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK),
longCmdOffset (cmdMode == 2 ? 3 * tCK : 1 * tCK),
tBURST16 (tCK * 8),

86
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
View File

@@ -44,51 +44,51 @@ using namespace tlm;
MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::HBM3,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")),
RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tPL (tCK * memSpec.memTimingSpec.entries.at("PL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAACDR(memSpec.memarchitecturespec.entries.at("RAACDR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")),
tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")),
tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tPL (tCK * memSpec.memtimingspec.entries.at("PL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")),
tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")),
tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")),
tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")),
tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCKE + tCK),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD"))
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memtimingspec.entries.at("REFIPB")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD"))
{
commandLengthInCycles[Command::ACT] = 1.5;
commandLengthInCycles[Command::PREPB] = 0.5;

88
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -44,42 +44,42 @@ using namespace tlm;
MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::LPDDR5,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memArchitectureSpec.entries.at("per2BankOffset")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIpb")),
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCab")),
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCpb")),
tRPab (tCK * memSpec.memTimingSpec.entries.at("RPab")),
tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPpb")),
tRCab (tCK * memSpec.memTimingSpec.entries.at("RCab")),
tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCpb")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRCD_L (tCK * memSpec.memTimingSpec.entries.at("RCD_L")),
tRCD_S (tCK * memSpec.memTimingSpec.entries.at("RCD_S")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")),
tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")),
tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")),
tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")),
tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
//tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
//tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
tRBTP (tCK * memSpec.memTimingSpec.entries.at("RBTP")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
//tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
//tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
//tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
//tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
//tXP (tCK * parseUint(memspec["memtimingspec"] "XP")),
@@ -88,20 +88,20 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
//tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")),
//tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
//tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")),
BL_n_min_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_min_16")),
BL_n_max_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_max_16")),
BL_n_L_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_L_16")),
BL_n_S_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_S_16")),
BL_n_min_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_min_32")),
BL_n_max_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_max_32")),
BL_n_L_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_L_32")),
BL_n_S_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_S_32")),
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
tWCK2DQO(tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
tpbR2act(tCK * memSpec.memTimingSpec.entries.at("pbR2act")),
tpbR2pbR(tCK * memSpec.memTimingSpec.entries.at("pbR2pbR")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
BL_n_min_16(tCK * memSpec.memtimingspec.entries.at("BL_n_min_16")),
BL_n_max_16(tCK * memSpec.memtimingspec.entries.at("BL_n_max_16")),
BL_n_L_16(tCK * memSpec.memtimingspec.entries.at("BL_n_L_16")),
BL_n_S_16(tCK * memSpec.memtimingspec.entries.at("BL_n_S_16")),
BL_n_min_32(tCK * memSpec.memtimingspec.entries.at("BL_n_min_32")),
BL_n_max_32(tCK * memSpec.memtimingspec.entries.at("BL_n_max_32")),
BL_n_L_32(tCK * memSpec.memtimingspec.entries.at("BL_n_L_32")),
BL_n_S_32(tCK * memSpec.memtimingspec.entries.at("BL_n_S_32")),
tWTR_L (tCK * memSpec.memtimingspec.entries.at("WTR_L")),
tWTR_S (tCK * memSpec.memtimingspec.entries.at("WTR_S")),
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")),
tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
tBURST16(tCK * 16 / dataRate),
tBURST32(tCK * 32 / dataRate),
bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B))

79
src/configuration/DRAMSys/config/AddressMapping.cpp
View File

@@ -40,83 +40,4 @@
namespace DRAMSys::Config
{
void to_json(json_t &j, const AddressMapping &m)
{
auto congen = json_t{{"BYTE_BIT", m.byteBits},
{"COLUMN_BIT", m.columnBits},
{"ROW_BIT", m.rowBits},
{"BANK_BIT", m.bankBits},
{"BANKGROUP_BIT", m.bankGroupBits},
{"RANK_BIT", m.rankBits},
{"CHANNEL_BIT", m.channelBits},
{"XOR", m.xorBits}};
remove_null_values(congen);
j["CONGEN"] = congen;
}
void from_json(const json_t &j, AddressMapping &m)
{
json_t j_addressmapping = get_config_json(j, addressMappingPath, "CONGEN");
json_t congen;
if (j_addressmapping["CONGEN"].is_null())
congen = j_addressmapping;
else
congen = j_addressmapping["CONGEN"];
if (congen.contains("BYTE_BIT"))
congen.at("BYTE_BIT").get_to(m.byteBits);
if (congen.contains("COLUMN_BIT"))
congen.at("COLUMN_BIT").get_to(m.columnBits);
if (congen.contains("ROW_BIT"))
congen.at("ROW_BIT").get_to(m.rowBits);
if (congen.contains("BANK_BIT"))
congen.at("BANK_BIT").get_to(m.bankBits);
if (congen.contains("BANKGROUP_BIT"))
congen.at("BANKGROUP_BIT").get_to(m.bankGroupBits);
if (congen.contains("RANK_BIT"))
congen.at("RANK_BIT").get_to(m.rankBits);
// HBM pseudo channels are internally modelled as ranks
if (congen.contains("PSEUDOCHANNEL_BIT"))
congen.at("PSEUDOCHANNEL_BIT").get_to(m.rankBits);
if (congen.contains("CHANNEL_BIT"))
congen.at("CHANNEL_BIT").get_to(m.channelBits);
if (congen.contains("XOR"))
congen.at("XOR").get_to(m.xorBits);
}
void to_json(json_t &j, const XorPair &x)
{
j = json_t{{"FIRST", x.first}, {"SECOND", x.second}};
}
void from_json(const json_t &j, XorPair &x)
{
j.at("FIRST").get_to(x.first);
j.at("SECOND").get_to(x.second);
}
void from_dump(const std::string &dump, AddressMapping &c)
{
json_t json_addressmapping = json_t::parse(dump).at("addressmapping");
json_addressmapping.get_to(c);
}
std::string dump(const AddressMapping &c, unsigned int indentation)
{
json_t json_addressmapping;
json_addressmapping["addressmapping"] = c;
return json_addressmapping.dump(indentation);
}
} // namespace DRAMSys::Config

46
src/configuration/DRAMSys/config/AddressMapping.h
View File

@@ -42,34 +42,46 @@
namespace DRAMSys::Config
{
const std::string addressMappingPath = "addressmapping";
struct XorPair
{
unsigned int first;
unsigned int second;
unsigned int FIRST;
unsigned int SECOND;
};
void to_json(json_t &j, const XorPair &x);
void from_json(const json_t &j, XorPair &x);
NLOHMANN_JSONIFY_ALL_THINGS(XorPair, FIRST, SECOND)
struct AddressMapping
{
std::optional<std::vector<unsigned int>> byteBits;
std::optional<std::vector<unsigned int>> columnBits;
std::optional<std::vector<unsigned int>> rowBits;
std::optional<std::vector<unsigned int>> bankBits;
std::optional<std::vector<unsigned int>> bankGroupBits;
std::optional<std::vector<unsigned int>> rankBits;
std::optional<std::vector<unsigned int>> channelBits;
std::optional<std::vector<XorPair>> xorBits;
static constexpr std::string_view KEY = "addressmapping";
static constexpr std::string_view INNER_KEY = "CONGEN";
static constexpr std::string_view PATH = "addressmapping";
struct ConGen {
std::optional<std::vector<unsigned int>> BYTE_BIT;
std::optional<std::vector<unsigned int>> COLUMN_BIT;
std::optional<std::vector<unsigned int>> ROW_BIT;
std::optional<std::vector<unsigned int>> BANK_BIT;
std::optional<std::vector<unsigned int>> BANKGROUP_BIT;
std::optional<std::vector<unsigned int>> RANK_BIT;
std::optional<std::vector<unsigned int>> PSEUDOCHANNEL_BIT;
std::optional<std::vector<unsigned int>> CHANNEL_BIT;
std::optional<std::vector<XorPair>> XOR;
} CONGEN;
};
void to_json(json_t &j, const AddressMapping &m);
void from_json(const json_t &j, AddressMapping &m);
NLOHMANN_JSONIFY_ALL_THINGS(AddressMapping, CONGEN)
void from_dump(const std::string &dump, AddressMapping &c);
std::string dump(const AddressMapping &c, unsigned int indentation = -1);
NLOHMANN_JSONIFY_ALL_THINGS(AddressMapping::ConGen,
BYTE_BIT,
COLUMN_BIT,
ROW_BIT,
BANK_BIT,
BANKGROUP_BIT,
RANK_BIT,
PSEUDOCHANNEL_BIT,
CHANNEL_BIT,
XOR)
} // namespace Configuration

18
src/configuration/DRAMSys/config/ConfigUtil.cpp
View File

@@ -37,27 +37,11 @@
#include "DRAMSys/config/DRAMSysConfiguration.h"
#include <filesystem>
#include <fstream>
#include <iostream>
namespace DRAMSys::Config
{
json_t get_config_json(const json_t& j, const std::string& configPath, const std::string& objectName)
{
if (j.is_object())
{
return j;
}
else // j should be a string path to the real json file
{
std::string jsonFileName;
j.get_to(jsonFileName);
std::ifstream file(std::string(Configuration::resourceDirectory) + "/" + configPath + "/" + jsonFileName);
json_t j_object = json_t::parse(file);
return j_object.at(objectName);
}
}
} // namespace DRAMSys::Config

48
src/configuration/DRAMSys/config/ConfigUtil.h
View File

@@ -43,52 +43,6 @@
namespace DRAMSys::Config
{
//using json_t = nlohmann::json;
// template <typename T>
// class Optional : public std::pair<T, bool>
// {
// public:
// Optional() : std::pair<T, bool>{{}, false}
// {
// }
// Optional(const T &v) : std::pair<T, bool>{v, true}
// {
// }
// bool isValid() const
// {
// return this->second;
// }
// const T &getValue() const
// {
// assert(this->second == true);
// return this->first;
// }
// void setValue(const T &v)
// {
// this->first = v;
// this->second = true;
// }
// void invalidate()
// {
// this->second = false;
// }
// /**
// * This methods only purpose is to make a optional type
// * valid so that it can be written to by reference.
// */
// T &setByReference()
// {
// this->second = true;
// return this->first;
// }
// };
template <typename T>
void invalidateEnum(T& value)
{
@@ -96,8 +50,6 @@ namespace DRAMSys::Config
value.reset();
}
json_t get_config_json(const json_t& j, const std::string& configPath, const std::string& objectName);
inline void remove_null_values(json_t& j)
{
std::vector<std::string> keysToRemove;

133
src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp
View File

@@ -35,62 +35,103 @@
#include "DRAMSysConfiguration.h"
#include "DRAMSys/config/ConfigUtil.h"
#include "ConfigUtil.h"
#include <fstream>
#include <iostream>
namespace DRAMSys::Config
{
std::string Configuration::resourceDirectory;
void to_json(json_t &j, const Configuration &c)
Configuration from_path(std::string_view path, std::string_view resourceDirectory)
{
j = json_t{{"addressmapping", c.addressMapping}, {"mcconfig", c.mcConfig}, {"memspec", c.memSpec},
{"simulationid", c.simulationId}, {"simconfig", c.simConfig}, {"tracesetup", c.traceSetup}};
std::ifstream file(path.data());
remove_null_values(j);
}
void from_json(const json_t &j, Configuration &c)
{
j.at("addressmapping").get_to(c.addressMapping);
j.at("mcconfig").get_to(c.mcConfig);
j.at("memspec").get_to(c.memSpec);
j.at("simulationid").get_to(c.simulationId);
j.at("simconfig").get_to(c.simConfig);
if (j.contains("tracesetup"))
j.at("tracesetup").get_to(c.traceSetup);
}
void from_dump(const std::string &dump, Configuration &c)
{
json_t json_simulation = json_t::parse(dump).at("simulation");
json_simulation.get_to(c);
}
std::string dump(const Configuration &c, unsigned int indentation)
{
json_t json_simulation;
json_simulation["simulation"] = c;
return json_simulation.dump(indentation);
}
Configuration from_path(const std::string &path, const std::string &resourceDirectory)
{
Configuration::resourceDirectory = resourceDirectory;
std::ifstream file(path);
if (file.is_open())
enum class SubConfig
{
json_t simulation = json_t::parse(file).at("simulation");
MemSpec,
AddressMapping,
McConfig,
SimConfig,
TraceSetup,
Unkown
} current_sub_config;
std::function<bool(int depth, nlohmann::detail::parse_event_t event, json_t &parsed)>
parser_callback;
parser_callback =
[&parser_callback, &current_sub_config, resourceDirectory](
int depth, nlohmann::detail::parse_event_t event, json_t &parsed) -> bool {
using nlohmann::detail::parse_event_t;
if (depth != 2)
return true;
if (event == parse_event_t::key) {
assert(parsed.is_string());
if (parsed == MemSpec::KEY)
current_sub_config = SubConfig::MemSpec;
else if (parsed == AddressMapping::KEY)
current_sub_config = SubConfig::AddressMapping;
else if (parsed == McConfig::KEY)
current_sub_config = SubConfig::McConfig;
else if (parsed == SimConfig::KEY)
current_sub_config = SubConfig::SimConfig;
else if (parsed == TraceSetupConstants::KEY)
current_sub_config = SubConfig::TraceSetup;
else
current_sub_config = SubConfig::Unkown;
}
if (event == parse_event_t::value && current_sub_config != SubConfig::Unkown) {
// Replace name of json file with actual json data
auto parse_json = [&parser_callback,
resourceDirectory](std::string_view base_dir,
std::string_view sub_config_key,
const std::string &filename) -> json_t {
std::filesystem::path path(resourceDirectory);
path /= base_dir;
path /= filename;
std::ifstream json_file(path);
if (!json_file.is_open())
throw std::runtime_error("Failed to open file " + std::string(path));
json_t json =
json_t::parse(json_file, parser_callback, true, true).at(sub_config_key);
return json;
};
if (current_sub_config == SubConfig::MemSpec)
parsed = parse_json(MemSpec::PATH, MemSpec::KEY, parsed);
else if (current_sub_config == SubConfig::AddressMapping)
{
parsed = parse_json(AddressMapping::PATH, AddressMapping::INNER_KEY, parsed);
if (!parsed.contains(AddressMapping::INNER_KEY)) {
auto temp = parsed;
parsed = json_t();
parsed[AddressMapping::INNER_KEY] = temp;
}
}
else if (current_sub_config == SubConfig::McConfig)
parsed = parse_json(McConfig::PATH, McConfig::KEY, parsed);
else if (current_sub_config == SubConfig::SimConfig)
parsed = parse_json(SimConfig::PATH, SimConfig::KEY, parsed);
else if (current_sub_config == SubConfig::TraceSetup)
parsed = parse_json(TraceSetupConstants::PATH, TraceSetupConstants::KEY, parsed);
}
return true;
};
if (file.is_open()) {
json_t simulation = json_t::parse(file, parser_callback, true, true).at(Configuration::KEY);
return simulation.get<DRAMSys::Config::Configuration>();
}
else
{
throw std::runtime_error("Failed to open file " + path);
} else {
throw std::runtime_error("Failed to open file " + std::string(path));
}
}

34
src/configuration/DRAMSys/config/DRAMSysConfiguration.h
View File

@@ -54,29 +54,35 @@
* values will be provided by DRAMSys itself.
*
* To achieve static polymorphism, std::variant is used.
*
* To achieve backwards compatibility, this library manipulates the json
* data type as it is parsed in to substitute paths to sub-configurations
* with the actual json object that is stored at this path.
*/
namespace DRAMSys::Config {
struct Configuration
{
AddressMapping addressMapping;
McConfig mcConfig;
MemSpec memSpec;
SimConfig simConfig;
std::string simulationId;
std::optional<TraceSetup> traceSetup;
static std::string resourceDirectory;
static constexpr std::string_view KEY = "simulation";
AddressMapping addressmapping;
McConfig mcconfig;
MemSpec memspec;
SimConfig simconfig;
std::string simulationid;
std::optional<TraceSetup> tracesetup;
};
void to_json(json &j, const Configuration &p);
void from_json(const json &j, Configuration &p);
NLOHMANN_JSONIFY_ALL_THINGS(Configuration,
addressmapping,
mcconfig,
memspec,
simconfig,
simulationid,
tracesetup)
void from_dump(const std::string &dump, Configuration &c);
std::string dump(const Configuration &c, unsigned int indentation = -1);
Configuration from_path(const std::string &path, const std::string &resourceDirectory = DRAMSYS_RESOURCE_DIR);
Configuration from_path(std::string_view path, std::string_view resourceDirectory = DRAMSYS_RESOURCE_DIR);
} // namespace DRAMSys::Config

152
src/configuration/DRAMSys/config/McConfig.cpp
View File

@@ -38,162 +38,36 @@
namespace DRAMSys::Config
{
void to_json(json_t &j, const McConfig &c)
void to_json(json_t &j, const RefreshPolicyType &r)
{
j = json_t{{"PagePolicy", c.pagePolicy},
{"Scheduler", c.scheduler},
{"HighWatermark", c.highWatermark},
{"LowWatermark", c.lowWatermark},
{"SchedulerBuffer", c.schedulerBuffer},
{"RequestBufferSize", c.requestBufferSize},
{"CmdMux", c.cmdMux},
{"RespQueue", c.respQueue},
{"RefreshPolicy", c.refreshPolicy},
{"RefreshMaxPostponed", c.refreshMaxPostponed},
{"RefreshMaxPulledin", c.refreshMaxPulledin},
{"PowerDownPolicy", c.powerDownPolicy},
{"Arbiter", c.arbiter},
{"MaxActiveTransactions", c.maxActiveTransactions},
{"RefreshManagement", c.refreshManagement},
{"ArbitrationDelayFw", c.arbitrationDelayFw},
{"ArbitrationDelayBw", c.arbitrationDelayBw},
{"ThinkDelayFw", c.thinkDelayFw},
{"ThinkDelayBw", c.thinkDelayBw},
{"PhyDelayFw", c.phyDelayFw},
{"PhyDelayBw", c.phyDelayBw},
{"BlockingReadDelay", c.blockingReadDelay},
{"BlockingWriteDelay", c.blockingWriteDelay}};
remove_null_values(j);
}
void from_json(const json_t &j, McConfig &c)
{
json_t j_mcconfig = get_config_json(j, mcConfigPath, "mcconfig");
if (j_mcconfig.contains("PagePolicy"))
j_mcconfig.at("PagePolicy").get_to(c.pagePolicy);
if (j_mcconfig.contains("Scheduler"))
j_mcconfig.at("Scheduler").get_to(c.scheduler);
if (j_mcconfig.contains("HighWatermark"))
j_mcconfig.at("HighWatermark").get_to(c.highWatermark);
if (j_mcconfig.contains("LowWatermark"))
j_mcconfig.at("LowWatermark").get_to(c.lowWatermark);
if (j_mcconfig.contains("SchedulerBuffer"))
j_mcconfig.at("SchedulerBuffer").get_to(c.schedulerBuffer);
if (j_mcconfig.contains("RequestBufferSize"))
j_mcconfig.at("RequestBufferSize").get_to(c.requestBufferSize);
if (j_mcconfig.contains("CmdMux"))
j_mcconfig.at("CmdMux").get_to(c.cmdMux);
if (j_mcconfig.contains("RespQueue"))
j_mcconfig.at("RespQueue").get_to(c.respQueue);
if (j_mcconfig.contains("RefreshPolicy"))
j_mcconfig.at("RefreshPolicy").get_to(c.refreshPolicy);
if (j_mcconfig.contains("RefreshMaxPostponed"))
j_mcconfig.at("RefreshMaxPostponed").get_to(c.refreshMaxPostponed);
if (j_mcconfig.contains("RefreshMaxPulledin"))
j_mcconfig.at("RefreshMaxPulledin").get_to(c.refreshMaxPulledin);
if (j_mcconfig.contains("PowerDownPolicy"))
j_mcconfig.at("PowerDownPolicy").get_to(c.powerDownPolicy);
if (j_mcconfig.contains("Arbiter"))
j_mcconfig.at("Arbiter").get_to(c.arbiter);
if (j_mcconfig.contains("MaxActiveTransactions"))
j_mcconfig.at("MaxActiveTransactions").get_to(c.maxActiveTransactions);
if (j_mcconfig.contains("RefreshManagement"))
j_mcconfig.at("RefreshManagement").get_to(c.refreshManagement);
if (j_mcconfig.contains("ArbitrationDelayFw"))
j_mcconfig.at("ArbitrationDelayFw").get_to(c.arbitrationDelayFw);
if (j_mcconfig.contains("ArbitrationDelayBw"))
j_mcconfig.at("ArbitrationDelayBw").get_to(c.arbitrationDelayBw);
if (j_mcconfig.contains("ThinkDelayFw"))
j_mcconfig.at("ThinkDelayFw").get_to(c.thinkDelayFw);
if (j_mcconfig.contains("ThinkDelayBw"))
j_mcconfig.at("ThinkDelayBw").get_to(c.thinkDelayBw);
if (j_mcconfig.contains("PhyDelayFw"))
j_mcconfig.at("PhyDelayFw").get_to(c.phyDelayFw);
if (j_mcconfig.contains("PhyDelayBw"))
j_mcconfig.at("PhyDelayBw").get_to(c.phyDelayBw);
if (j_mcconfig.contains("BlockingReadDelay"))
j_mcconfig.at("BlockingReadDelay").get_to(c.blockingReadDelay);
if (j_mcconfig.contains("BlockingWriteDelay"))
j_mcconfig.at("BlockingWriteDelay").get_to(c.blockingWriteDelay);
invalidateEnum(c.pagePolicy);
invalidateEnum(c.scheduler);
invalidateEnum(c.schedulerBuffer);
invalidateEnum(c.cmdMux);
invalidateEnum(c.respQueue);
invalidateEnum(c.refreshPolicy);
invalidateEnum(c.respQueue);
invalidateEnum(c.powerDownPolicy);
invalidateEnum(c.arbiter);
}
void to_json(json_t &j, const RefreshPolicy &r)
{
if (r == RefreshPolicy::NoRefresh)
if (r == RefreshPolicyType::NoRefresh)
j = "NoRefresh";
else if (r == RefreshPolicy::AllBank)
else if (r == RefreshPolicyType::AllBank)
j = "AllBank";
else if (r == RefreshPolicy::PerBank)
else if (r == RefreshPolicyType::PerBank)
j = "PerBank";
else if (r == RefreshPolicy::Per2Bank)
else if (r == RefreshPolicyType::Per2Bank)
j = "Per2Bank";
else if (r == RefreshPolicy::SameBank)
else if (r == RefreshPolicyType::SameBank)
j = "SameBank";
else
j = nullptr;
}
void from_json(const json_t &j, RefreshPolicy &r)
void from_json(const json_t &j, RefreshPolicyType &r)
{
if (j == "NoRefresh")
r = RefreshPolicy::NoRefresh;
r = RefreshPolicyType::NoRefresh;
else if (j == "AllBank" || j == "Rankwise")
r = RefreshPolicy::AllBank;
r = RefreshPolicyType::AllBank;
else if (j == "PerBank" || j == "Bankwise")
r = RefreshPolicy::PerBank;
r = RefreshPolicyType::PerBank;
else if (j == "SameBank" || j == "Groupwise")
r = RefreshPolicy::SameBank;
r = RefreshPolicyType::SameBank;
else if (j == "Per2Bank")
r = RefreshPolicy::Per2Bank;
r = RefreshPolicyType::Per2Bank;
else
r = RefreshPolicy::Invalid;
}
void from_dump(const std::string &dump, McConfig &c)
{
json_t json_mcconfig = json_t::parse(dump).at("mcconfig");
json_mcconfig.get_to(c);
}
std::string dump(const McConfig &c, unsigned int indentation)
{
json_t json_mcconfig;
json_mcconfig["mcconfig"] = c;
return json_mcconfig.dump(indentation);
r = RefreshPolicyType::Invalid;
}
} // namespace DRAMSys::Config

156
src/configuration/DRAMSys/config/McConfig.h
View File

@@ -44,9 +44,8 @@
namespace DRAMSys::Config
{
const std::string mcConfigPath = "mcconfig";
enum class PagePolicy
enum class PagePolicyType
{
Open,
OpenAdaptive,
@@ -55,15 +54,15 @@ enum class PagePolicy
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(PagePolicy, {
{PagePolicy::Invalid, nullptr},
{PagePolicy::Open, "Open"},
{PagePolicy::OpenAdaptive, "OpenAdaptive"},
{PagePolicy::Closed, "Closed"},
{PagePolicy::ClosedAdaptive, "ClosedAdaptive"},
NLOHMANN_JSON_SERIALIZE_ENUM(PagePolicyType, {
{PagePolicyType::Invalid, nullptr},
{PagePolicyType::Open, "Open"},
{PagePolicyType::OpenAdaptive, "OpenAdaptive"},
{PagePolicyType::Closed, "Closed"},
{PagePolicyType::ClosedAdaptive, "ClosedAdaptive"},
})
enum class Scheduler
enum class SchedulerType
{
Fifo,
FrFcfs,
@@ -73,14 +72,14 @@ enum class Scheduler
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(Scheduler, {{Scheduler::Invalid, nullptr},
{Scheduler::Fifo, "Fifo"},
{Scheduler::FrFcfs, "FrFcfs"},
{Scheduler::FrFcfsGrp, "FrFcfsGrp"},
{Scheduler::GrpFrFcfs, "GrpFrFcfs"},
{Scheduler::GrpFrFcfsWm, "GrpFrFcfsWm"}})
NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerType, {{SchedulerType::Invalid, nullptr},
{SchedulerType::Fifo, "Fifo"},
{SchedulerType::FrFcfs, "FrFcfs"},
{SchedulerType::FrFcfsGrp, "FrFcfsGrp"},
{SchedulerType::GrpFrFcfs, "GrpFrFcfs"},
{SchedulerType::GrpFrFcfsWm, "GrpFrFcfsWm"}})
enum class SchedulerBuffer
enum class SchedulerBufferType
{
Bankwise,
ReadWrite,
@@ -88,33 +87,33 @@ enum class SchedulerBuffer
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerBuffer, {{SchedulerBuffer::Invalid, nullptr},
{SchedulerBuffer::Bankwise, "Bankwise"},
{SchedulerBuffer::ReadWrite, "ReadWrite"},
{SchedulerBuffer::Shared, "Shared"}})
NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerBufferType, {{SchedulerBufferType::Invalid, nullptr},
{SchedulerBufferType::Bankwise, "Bankwise"},
{SchedulerBufferType::ReadWrite, "ReadWrite"},
{SchedulerBufferType::Shared, "Shared"}})
enum class CmdMux
enum class CmdMuxType
{
Oldest,
Strict,
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(CmdMux,
{{CmdMux::Invalid, nullptr}, {CmdMux::Oldest, "Oldest"}, {CmdMux::Strict, "Strict"}})
NLOHMANN_JSON_SERIALIZE_ENUM(CmdMuxType,
{{CmdMuxType::Invalid, nullptr}, {CmdMuxType::Oldest, "Oldest"}, {CmdMuxType::Strict, "Strict"}})
enum class RespQueue
enum class RespQueueType
{
Fifo,
Reorder,
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(RespQueue, {{RespQueue::Invalid, nullptr},
{RespQueue::Fifo, "Fifo"},
{RespQueue::Reorder, "Reorder"}})
NLOHMANN_JSON_SERIALIZE_ENUM(RespQueueType, {{RespQueueType::Invalid, nullptr},
{RespQueueType::Fifo, "Fifo"},
{RespQueueType::Reorder, "Reorder"}})
enum class RefreshPolicy
enum class RefreshPolicyType
{
NoRefresh,
AllBank,
@@ -124,18 +123,18 @@ enum class RefreshPolicy
Invalid = -1
};
enum class PowerDownPolicy
enum class PowerDownPolicyType
{
NoPowerDown,
Staggered,
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(PowerDownPolicy, {{PowerDownPolicy::Invalid, nullptr},
{PowerDownPolicy::NoPowerDown, "NoPowerDown"},
{PowerDownPolicy::Staggered, "Staggered"}})
NLOHMANN_JSON_SERIALIZE_ENUM(PowerDownPolicyType, {{PowerDownPolicyType::Invalid, nullptr},
{PowerDownPolicyType::NoPowerDown, "NoPowerDown"},
{PowerDownPolicyType::Staggered, "Staggered"}})
enum class Arbiter
enum class ArbiterType
{
Simple,
Fifo,
@@ -143,46 +142,71 @@ enum class Arbiter
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(Arbiter, {{Arbiter::Invalid, nullptr},
{Arbiter::Simple, "Simple"},
{Arbiter::Fifo, "Fifo"},
{Arbiter::Reorder, "Reorder"}})
NLOHMANN_JSON_SERIALIZE_ENUM(ArbiterType, {{ArbiterType::Invalid, nullptr},
{ArbiterType::Simple, "Simple"},
{ArbiterType::Fifo, "Fifo"},
{ArbiterType::Reorder, "Reorder"}})
struct McConfig
{
std::optional<PagePolicy> pagePolicy;
std::optional<Scheduler> scheduler;
std::optional<unsigned int> highWatermark;
std::optional<unsigned int> lowWatermark;
std::optional<SchedulerBuffer> schedulerBuffer;
std::optional<unsigned int> requestBufferSize;
std::optional<CmdMux> cmdMux;
std::optional<RespQueue> respQueue;
std::optional<RefreshPolicy> refreshPolicy;
std::optional<unsigned int> refreshMaxPostponed;
std::optional<unsigned int> refreshMaxPulledin;
std::optional<PowerDownPolicy> powerDownPolicy;
std::optional<Arbiter> arbiter;
std::optional<unsigned int> maxActiveTransactions;
std::optional<bool> refreshManagement;
std::optional<unsigned int> arbitrationDelayFw;
std::optional<unsigned int> arbitrationDelayBw;
std::optional<unsigned int> thinkDelayFw;
std::optional<unsigned int> thinkDelayBw;
std::optional<unsigned int> phyDelayFw;
std::optional<unsigned int> phyDelayBw;
std::optional<unsigned int> blockingReadDelay;
std::optional<unsigned int> blockingWriteDelay;
static constexpr std::string_view KEY = "mcconfig";
static constexpr std::string_view PATH = "mcconfig";
std::optional<PagePolicyType> PagePolicy;
std::optional<SchedulerType> Scheduler;
std::optional<unsigned int> HighWatermark;
std::optional<unsigned int> LowWatermark;
std::optional<SchedulerBufferType> SchedulerBuffer;
std::optional<unsigned int> RequestBufferSize;
std::optional<CmdMuxType> CmdMux;
std::optional<RespQueueType> RespQueue;
std::optional<RefreshPolicyType> RefreshPolicy;
std::optional<unsigned int> RefreshMaxPostponed;
std::optional<unsigned int> RefreshMaxPulledin;
std::optional<PowerDownPolicyType> PowerDownPolicy;
std::optional<ArbiterType> Arbiter;
std::optional<unsigned int> MaxActiveTransactions;
std::optional<bool> RefreshManagement;
std::optional<unsigned int> ArbitrationDelayFw;
std::optional<unsigned int> ArbitrationDelayBw;
std::optional<unsigned int> ThinkDelayFw;
std::optional<unsigned int> ThinkDelayBw;
std::optional<unsigned int> PhyDelayFw;
std::optional<unsigned int> PhyDelayBw;
std::optional<unsigned int> BlockingReadDelay;
std::optional<unsigned int> BlockingWriteDelay;
};
void to_json(json_t &j, const McConfig &c);
void from_json(const json_t &j, McConfig &c);
NLOHMANN_JSONIFY_ALL_THINGS(McConfig,
PagePolicy,
Scheduler,
HighWatermark,
LowWatermark,
SchedulerBuffer,
RequestBufferSize,
CmdMux,
RespQueue,
RefreshPolicy,
RefreshMaxPostponed,
RefreshMaxPulledin,
PowerDownPolicy,
Arbiter,
MaxActiveTransactions,
RefreshManagement,
ArbitrationDelayFw,
ArbitrationDelayBw,
ThinkDelayFw,
ThinkDelayBw,
PhyDelayFw,
PhyDelayBw,
BlockingReadDelay,
BlockingWriteDelay)
void to_json(json_t &j, const RefreshPolicy &r);
void from_json(const json_t &j, RefreshPolicy &r);
void to_json(json_t &j, const RefreshPolicyType &r);
void from_json(const json_t &j, RefreshPolicyType &r);
void from_dump(const std::string &dump, McConfig &c);
std::string dump(const McConfig &c, unsigned int indentation = -1);
// void from_dump(const std::string &dump, McConfig &c);
// std::string dump(const McConfig &c, unsigned int indentation = -1);
} // namespace Configuration

80
src/configuration/DRAMSys/config/SimConfig.cpp
View File

@@ -38,84 +38,4 @@
namespace DRAMSys::Config
{
void to_json(json_t &j, const SimConfig &c)
{
j = json_t{{"AddressOffset", c.addressOffset},
{"CheckTLM2Protocol", c.checkTLM2Protocol},
{"DatabaseRecording", c.databaseRecording},
{"Debug", c.debug},
{"EnableWindowing", c.enableWindowing},
{"ErrorCSVFile", c.errorCsvFile},
{"ErrorChipSeed", c.errorChipSeed},
{"PowerAnalysis", c.powerAnalysis},
{"SimulationName", c.simulationName},
{"SimulationProgressBar", c.simulationProgressBar},
{"StoreMode", c.storeMode},
{"ThermalSimulation", c.thermalSimulation},
{"UseMalloc", c.useMalloc},
{"WindowSize", c.windowSize}};
}
void from_json(const json_t &j, SimConfig &c)
{
json_t j_simconfig = get_config_json(j, simConfigPath, "simconfig");
if (j_simconfig.contains("AddressOffset"))
j_simconfig.at("AddressOffset").get_to(c.addressOffset);
if (j_simconfig.contains("CheckTLM2Protocol"))
j_simconfig.at("CheckTLM2Protocol").get_to(c.checkTLM2Protocol);
if (j_simconfig.contains("DatabaseRecording"))
j_simconfig.at("DatabaseRecording").get_to(c.databaseRecording);
if (j_simconfig.contains("Debug"))
j_simconfig.at("Debug").get_to(c.debug);
if (j_simconfig.contains("EnableWindowing"))
j_simconfig.at("EnableWindowing").get_to(c.enableWindowing);
if (j_simconfig.contains("ErrorCSVFile"))
j_simconfig.at("ErrorCSVFile").get_to(c.errorCsvFile);
if (j_simconfig.contains("ErrorChipSeed"))
j_simconfig.at("ErrorChipSeed").get_to(c.errorChipSeed);
if (j_simconfig.contains("PowerAnalysis"))
j_simconfig.at("PowerAnalysis").get_to(c.powerAnalysis);
if (j_simconfig.contains("SimulationName"))
j_simconfig.at("SimulationName").get_to(c.simulationName);
if (j_simconfig.contains("SimulationProgressBar"))
j_simconfig.at("SimulationProgressBar").get_to(c.simulationProgressBar);
if (j_simconfig.contains("StoreMode"))
j_simconfig.at("StoreMode").get_to(c.storeMode);
if (j_simconfig.contains("ThermalSimulation"))
j_simconfig.at("ThermalSimulation").get_to(c.thermalSimulation);
if (j_simconfig.contains("UseMalloc"))
j_simconfig.at("UseMalloc").get_to(c.useMalloc);
if (j_simconfig.contains("WindowSize"))
j_simconfig.at("WindowSize").get_to(c.windowSize);
invalidateEnum(c.storeMode);
}
void from_dump(const std::string &dump, SimConfig &c)
{
json_t json_simconfig = json_t::parse(dump).at("simconfig");
json_simconfig.get_to(c);
}
std::string dump(const SimConfig &c, unsigned int indentation)
{
json_t json_simconfig;
json_simconfig["simconfig"] = c;
return json_simconfig.dump(indentation);
}
} // namespace DRAMSys::Config

62
src/configuration/DRAMSys/config/SimConfig.h
View File

@@ -42,9 +42,8 @@
namespace DRAMSys::Config
{
const std::string simConfigPath = "simconfig";
enum class StoreMode
enum class StoreModeType
{
NoStorage,
Store,
@@ -52,34 +51,47 @@ enum class StoreMode
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(StoreMode, {{StoreMode::Invalid, nullptr},
{StoreMode::NoStorage, "NoStorage"},
{StoreMode::Store, "Store"},
{StoreMode::ErrorModel, "ErrorModel"}})
NLOHMANN_JSON_SERIALIZE_ENUM(StoreModeType, {{StoreModeType::Invalid, nullptr},
{StoreModeType::NoStorage, "NoStorage"},
{StoreModeType::Store, "Store"},
{StoreModeType::ErrorModel, "ErrorModel"}})
struct SimConfig
{
std::optional<uint64_t> addressOffset;
std::optional<bool> checkTLM2Protocol;
std::optional<bool> databaseRecording;
std::optional<bool> debug;
std::optional<bool> enableWindowing;
std::optional<std::string> errorCsvFile;
std::optional<unsigned int> errorChipSeed;
std::optional<bool> powerAnalysis;
std::optional<std::string> simulationName;
std::optional<bool> simulationProgressBar;
std::optional<StoreMode> storeMode;
std::optional<bool> thermalSimulation;
std::optional<bool> useMalloc;
std::optional<unsigned int> windowSize;
static constexpr std::string_view KEY = "simconfig";
static constexpr std::string_view PATH = "simconfig";
std::optional<uint64_t> AddressOffset;
std::optional<bool> CheckTLM2Protocol;
std::optional<bool> DatabaseRecording;
std::optional<bool> Debug;
std::optional<bool> EnableWindowing;
std::optional<std::string> ErrorCSVFile;
std::optional<unsigned int> ErrorChipSeed;
std::optional<bool> PowerAnalysis;
std::optional<std::string> SimulationName;
std::optional<bool> SimulationProgressBar;
std::optional<StoreModeType> StoreMode;
std::optional<bool> ThermalSimulation;
std::optional<bool> UseMalloc;
std::optional<unsigned int> WindowSize;
};
void to_json(json_t &j, const SimConfig &c);
void from_json(const json_t &j, SimConfig &c);
void from_dump(const std::string &dump, SimConfig &c);
std::string dump(const SimConfig &c, unsigned int indentation = -1);
NLOHMANN_JSONIFY_ALL_THINGS(SimConfig,
AddressOffset,
CheckTLM2Protocol,
DatabaseRecording,
Debug,
EnableWindowing,
ErrorCSVFile,
ErrorChipSeed,
PowerAnalysis,
SimulationName,
SimulationProgressBar,
StoreMode,
ThermalSimulation,
UseMalloc,
WindowSize)
} // namespace Configuration

274
src/configuration/DRAMSys/config/TraceSetup.cpp
View File

@@ -37,278 +37,6 @@
#include <variant>
namespace DRAMSys::Config
{
TrafficInitiator::~TrafficInitiator()
{
}
TraceGeneratorState::~TraceGeneratorState()
{
}
void to_json(json_t &j, const TraceSetup &c)
{
// Create an empty array
j = json_t::array();
for (const auto &initiator : c.initiators)
{
json_t initiator_j;
std::visit(
[&initiator_j](auto &&initiator)
{
initiator_j["name"] = initiator.name;
initiator_j["clkMhz"] = initiator.clkMhz;
initiator_j["maxPendingReadRequests"] = initiator.maxPendingReadRequests;
initiator_j["maxPendingWriteRequests"] = initiator.maxPendingWriteRequests;
using T = std::decay_t<decltype(initiator)>;
if constexpr (std::is_same_v<T, TraceGenerator>)
{
initiator_j["type"] = "generator";
initiator_j["seed"] = initiator.seed;
initiator_j["maxTransactions"] = initiator.maxTransactions;
initiator_j["idleUntil"] = initiator.idleUntil;
// When there are less than 2 states, flatten out the json.
if (initiator.states.size() == 1)
{
std::visit(
[&initiator_j](auto &&state)
{
using U = std::decay_t<decltype(state)>;
if constexpr (std::is_same_v<U, TraceGeneratorTrafficState>)
{
initiator_j["numRequests"] = state.numRequests;
initiator_j["rwRatio"] = state.rwRatio;
initiator_j["addressDistribution"] = state.addressDistribution;
initiator_j["addressIncrement"] = state.addressIncrement;
initiator_j["minAddress"] = state.minAddress;
initiator_j["maxAddress"] = state.maxAddress;
initiator_j["clksPerRequest"] = state.clksPerRequest;
initiator_j["notify"] = state.notify;
}
else // if constexpr (std::is_same_v<U, TraceGeneratorIdleState>)
{
initiator_j["idleClks"] = state.idleClks;
}
},
initiator.states.at(0));
}
else
{
json_t states_j = json_t::array();
for (const auto &state : initiator.states)
{
json_t state_j;
state_j["id"] = state.first;
std::visit(
[&state_j](auto &&state)
{
using U = std::decay_t<decltype(state)>;
if constexpr (std::is_same_v<U, TraceGeneratorTrafficState>)
{
state_j["numRequests"] = state.numRequests;
state_j["rwRatio"] = state.rwRatio;
state_j["addressDistribution"] = state.addressDistribution;
state_j["addressIncrement"] = state.addressIncrement;
state_j["minAddress"] = state.minAddress;
state_j["maxAddress"] = state.maxAddress;
state_j["clksPerRequest"] = state.clksPerRequest;
state_j["notify"] = state.notify;
}
else // if constexpr (std::is_same_v<U, TraceGeneratorIdleState>)
{
state_j["idleClks"] = state.idleClks;
}
},
state.second);
remove_null_values(state_j);
states_j.insert(states_j.end(), state_j);
}
initiator_j["states"] = states_j;
json_t transitions_j = json_t::array();
for (const auto &transition : initiator.transitions)
{
json_t transition_j;
transition_j["from"] = transition.first;
transition_j["to"] = transition.second.to;
transition_j["probability"] = transition.second.probability;
remove_null_values(transition_j);
transitions_j.insert(transitions_j.end(), transition_j);
}
initiator_j["transitions"] = transitions_j;
}
}
else if constexpr (std::is_same_v<T, TraceHammer>)
{
initiator_j["type"] = "hammer";
initiator_j["numRequests"] = initiator.numRequests;
initiator_j["rowIncrement"] = initiator.rowIncrement;
}
else // if constexpr (std::is_same_v<T, TracePlayer>)
{
initiator_j["type"] = "player";
}
},
initiator);
remove_null_values(initiator_j);
j.insert(j.end(), initiator_j);
}
}
void from_json(const json_t&j, TraceSetup &c)
{
for (const auto &initiator_j : j)
{
// Default to Player, when not specified
TrafficInitiatorType type = initiator_j.value("type", TrafficInitiatorType::Player);
std::variant<TracePlayer, TraceGenerator, TraceHammer> initiator;
if (type == TrafficInitiatorType::Player)
{
initiator = TracePlayer{};
}
else if (type == TrafficInitiatorType::Generator)
{
TraceGenerator generator;
auto process_state = [](const json_t&state_j)
-> std::pair<unsigned int, std::variant<TraceGeneratorIdleState, TraceGeneratorTrafficState>>
{
std::variant<TraceGeneratorIdleState, TraceGeneratorTrafficState> state;
if (state_j.contains("idleClks"))
{
// Idle state
TraceGeneratorIdleState idleState;
state_j.at("idleClks").get_to(idleState.idleClks);
state = std::move(idleState);
}
else
{
// Traffic state
TraceGeneratorTrafficState trafficState;
state_j.at("numRequests").get_to(trafficState.numRequests);
state_j.at("rwRatio").get_to(trafficState.rwRatio);
state_j.at("addressDistribution").get_to(trafficState.addressDistribution);
if (state_j.contains("addressIncrement"))
state_j.at("addressIncrement").get_to(trafficState.addressIncrement);
if (state_j.contains("minAddress"))
state_j.at("minAddress").get_to(trafficState.minAddress);
if (state_j.contains("maxAddress"))
state_j.at("maxAddress").get_to(trafficState.maxAddress);
if (state_j.contains("clksPerRequest"))
state_j.at("clksPerRequest").get_to(trafficState.clksPerRequest);
if (state_j.contains("notify"))
state_j.at("notify").get_to(trafficState.notify);
state = std::move(trafficState);
}
// Default to 0
unsigned int id = 0;
if (state_j.contains("id"))
id = state_j.at("id");
return {id, std::move(state)};
};
if (initiator_j.contains("states"))
{
for (const auto &state_j : initiator_j.at("states"))
{
auto state = process_state(state_j);
generator.states[state.first] = std::move(state.second);
}
for (const auto &transition_j : initiator_j.at("transitions"))
{
TraceGeneratorStateTransition transition;
unsigned int from = transition_j.at("from");
transition.to = transition_j.at("to");
transition.probability = transition_j.at("probability");
generator.transitions.emplace(from, transition);
}
}
else // Only one state will be created
{
auto state = process_state(initiator_j);
generator.states[state.first] = std::move(state.second);
}
if (initiator_j.contains("seed"))
initiator_j.at("seed").get_to(generator.seed);
if (initiator_j.contains("maxTransactions"))
initiator_j.at("maxTransactions").get_to(generator.maxTransactions);
if (initiator_j.contains("dataLength"))
initiator_j.at("dataLength").get_to(generator.dataLength);
if (initiator_j.contains("idleUntil"))
initiator_j.at("idleUntil").get_to(generator.idleUntil);
initiator = generator;
}
else if (type == TrafficInitiatorType::Hammer)
{
TraceHammer hammer;
initiator_j.at("numRequests").get_to(hammer.numRequests);
initiator_j.at("rowIncrement").get_to(hammer.rowIncrement);
initiator = hammer;
}
std::visit(
[&initiator_j](auto &&initiator)
{
initiator_j.at("name").get_to(initiator.name);
initiator_j.at("clkMhz").get_to(initiator.clkMhz);
if (initiator_j.contains("maxPendingReadRequests"))
initiator_j.at("maxPendingReadRequests").get_to(initiator.maxPendingReadRequests);
if (initiator_j.contains("maxPendingWriteRequests"))
initiator_j.at("maxPendingWriteRequests").get_to(initiator.maxPendingWriteRequests);
},
initiator);
c.initiators.emplace_back(std::move(initiator));
}
}
void from_dump(const std::string &dump, TraceSetup &c)
{
json_t json_tracesetup = json_t::parse(dump).at("tracesetup");
json_tracesetup.get_to(c);
}
std::string dump(const TraceSetup &c, unsigned int indentation)
{
json_t json_tracesetup;
json_tracesetup["tracesetup"] = c;
return json_tracesetup.dump(indentation);
}
namespace DRAMSys::Config {
} // namespace DRAMSys::Config

122
src/configuration/DRAMSys/config/TraceSetup.h
View File

@@ -68,27 +68,21 @@ NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid
{AddressDistribution::Random, "random"},
{AddressDistribution::Sequential, "sequential"}})
struct TrafficInitiator
struct TracePlayer
{
virtual ~TrafficInitiator() = 0;
uint64_t clkMhz;
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
};
struct TracePlayer : public TrafficInitiator
{
};
NLOHMANN_JSONIFY_ALL_THINGS(
TracePlayer, clkMhz, name, maxPendingReadRequests, maxPendingWriteRequests)
struct TraceGeneratorState
struct TrafficGeneratorActiveState
{
virtual ~TraceGeneratorState() = 0;
};
unsigned int id;
struct TraceGeneratorTrafficState : public TraceGeneratorState
{
uint64_t numRequests;
double rwRatio;
AddressDistribution addressDistribution;
@@ -99,43 +93,123 @@ struct TraceGeneratorTrafficState : public TraceGeneratorState
std::optional<std::string> notify;
};
struct TraceGeneratorIdleState : public TraceGeneratorState
NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorActiveState,
id,
numRequests,
rwRatio,
addressDistribution,
addressIncrement,
minAddress,
maxAddress,
clksPerRequest,
notify)
struct TrafficGeneratorIdleState
{
unsigned int id;
uint64_t idleClks;
};
struct TraceGeneratorStateTransition
NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorIdleState, id, idleClks)
struct TrafficGeneratorStateTransition
{
unsigned int from;
unsigned int to;
float probability;
};
struct TraceGenerator : public TrafficInitiator
NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateTransition, from, to, probability)
struct TrafficGenerator
{
uint64_t clkMhz;
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
std::optional<uint64_t> seed;
std::optional<uint64_t> maxTransactions;
std::optional<unsigned> dataLength;
std::map<unsigned int, std::variant<TraceGeneratorIdleState, TraceGeneratorTrafficState>> states;
std::multimap<unsigned int, TraceGeneratorStateTransition> transitions;
uint64_t numRequests;
double rwRatio;
AddressDistribution addressDistribution;
std::optional<uint64_t> addressIncrement;
std::optional<uint64_t> minAddress;
std::optional<uint64_t> maxAddress;
std::optional<uint64_t> clksPerRequest;
std::optional<std::string> idleUntil;
};
struct TraceHammer : public TrafficInitiator
NLOHMANN_JSONIFY_ALL_THINGS(TrafficGenerator,
clkMhz,
name,
maxPendingReadRequests,
maxPendingWriteRequests,
seed,
maxTransactions,
dataLength,
numRequests,
rwRatio,
addressDistribution,
addressIncrement,
minAddress,
maxAddress,
clksPerRequest,
idleUntil)
struct TrafficGeneratorStateMachine
{
uint64_t clkMhz;
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
std::optional<uint64_t> seed;
std::optional<uint64_t> maxTransactions;
std::optional<unsigned> dataLength;
std::vector<std::variant<TrafficGeneratorActiveState, TrafficGeneratorIdleState>> states;
std::vector<TrafficGeneratorStateTransition> transitions;
std::optional<std::string> idleUntil;
};
NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateMachine,
clkMhz,
name,
maxPendingReadRequests,
maxPendingWriteRequests,
seed,
maxTransactions,
dataLength,
states,
transitions,
idleUntil)
struct TraceHammer
{
uint64_t clkMhz;
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
uint64_t numRequests;
uint64_t rowIncrement;
};
struct TraceSetup
NLOHMANN_JSONIFY_ALL_THINGS(
TraceHammer, clkMhz, name, maxPendingReadRequests, maxPendingWriteRequests, numRequests, rowIncrement)
struct TraceSetupConstants
{
std::vector<std::variant<TracePlayer, TraceGenerator, TraceHammer>> initiators;
static constexpr std::string_view KEY = "tracesetup";
static constexpr std::string_view PATH = "tracesetup";
};
void to_json(json_t &j, const TraceSetup &c);
void from_json(const json_t &j, TraceSetup &c);
void from_dump(const std::string &dump, TraceSetup &c);
std::string dump(const TraceSetup &c, unsigned int indentation = -1);
using TraceSetup = std::vector<
std::variant<TracePlayer, TrafficGenerator, TrafficGeneratorStateMachine, TraceHammer>>;
} // namespace Configuration

4
src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp
View File

@@ -38,7 +38,7 @@
namespace DRAMSys::Config
{
void to_json(json_t &j, const MemArchitectureSpec &c)
void to_json(json_t &j, const MemArchitectureSpecType &c)
{
j = json_t{};
@@ -48,7 +48,7 @@ void to_json(json_t &j, const MemArchitectureSpec &c)
}
}
void from_json(const json_t &j, MemArchitectureSpec &c)
void from_json(const json_t &j, MemArchitectureSpecType &c)
{
for (const auto &entry : j.items())
{

6
src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h
View File

@@ -43,13 +43,13 @@
namespace DRAMSys::Config
{
struct MemArchitectureSpec
struct MemArchitectureSpecType
{
std::unordered_map<std::string, unsigned int> entries;
};
void to_json(json_t &j, const MemArchitectureSpec &c);
void from_json(const json_t &j, MemArchitectureSpec &c);
void to_json(json_t &j, const MemArchitectureSpecType &c);
void from_json(const json_t &j, MemArchitectureSpecType &c);
} // namespace Configuration

37
src/configuration/DRAMSys/config/memspec/MemSpec.cpp
View File

@@ -38,41 +38,4 @@
namespace DRAMSys::Config
{
void to_json(json &j, const MemSpec &c)
{
j = json{{"memarchitecturespec", c.memArchitectureSpec},
{"memoryId", c.memoryId},
{"memoryType", c.memoryType},
{"memtimingspec", c.memTimingSpec},
{"mempowerspec", c.memPowerSpec}};
remove_null_values(j);
}
void from_json(const json &j, MemSpec &c)
{
json j_memspecs = get_config_json(j, memSpecPath, "memspec");
j_memspecs.at("memarchitecturespec").get_to(c.memArchitectureSpec);
j_memspecs.at("memoryId").get_to(c.memoryId);
j_memspecs.at("memoryType").get_to(c.memoryType);
j_memspecs.at("memtimingspec").get_to(c.memTimingSpec);
if (j_memspecs.contains("mempowerspec"))
j_memspecs.at("mempowerspec").get_to(c.memPowerSpec);
}
void from_dump(const std::string &dump, MemSpec &c)
{
json json_memspec = json::parse(dump).at("memspec");
json_memspec.get_to(c);
}
std::string dump(const MemSpec &c, unsigned int indentation)
{
json json_memspec;
json_memspec["memspec"] = c;
return json_memspec.dump(indentation);
}
} // namespace Configuration

18
src/configuration/DRAMSys/config/memspec/MemSpec.h
View File

@@ -45,22 +45,20 @@
namespace DRAMSys::Config {
const std::string memSpecPath = "memspec";
struct MemSpec
{
MemArchitectureSpec memArchitectureSpec;
static constexpr std::string_view KEY = "memspec";
static constexpr std::string_view PATH = "memspec";
MemArchitectureSpecType memarchitecturespec;
std::string memoryId;
std::string memoryType;
MemTimingSpec memTimingSpec;
std::optional<MemPowerSpec> memPowerSpec;
MemTimingSpecType memtimingspec;
std::optional<MemPowerSpec> mempowerspec;
};
void to_json(json &j, const MemSpec &c);
void from_json(const json &j, MemSpec &c);
void from_dump(const std::string &dump, MemSpec &c);
std::string dump(const MemSpec &c, unsigned int indentation = -1);
NLOHMANN_JSONIFY_ALL_THINGS(
MemSpec, memarchitecturespec, memoryId, memoryType, memtimingspec, mempowerspec)
} // namespace Configuration

4
src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp
View File

@@ -38,7 +38,7 @@
namespace DRAMSys::Config
{
void to_json(json_t &j, const MemTimingSpec &c)
void to_json(json_t &j, const MemTimingSpecType &c)
{
j = json_t{};
@@ -48,7 +48,7 @@ void to_json(json_t &j, const MemTimingSpec &c)
}
}
void from_json(const json_t &j, MemTimingSpec &c)
void from_json(const json_t &j, MemTimingSpecType &c)
{
for (const auto &entry : j.items())
{

6
src/configuration/DRAMSys/config/memspec/MemTimingSpec.h
View File

@@ -44,13 +44,13 @@ namespace DRAMSys::Config
{
using json = nlohmann::json;
struct MemTimingSpec
struct MemTimingSpecType
{
std::unordered_map<std::string, unsigned int> entries;
};
void to_json(json &j, const MemTimingSpec &c);
void from_json(const json &j, MemTimingSpec &c);
void to_json(json &j, const MemTimingSpecType &c);
void from_json(const json &j, MemTimingSpecType &c);
} // namespace Configuration

112
src/libdramsys/DRAMSys/configuration/Configuration.cpp
View File

@@ -87,22 +87,22 @@ enum sc_time_unit string2TimeUnit(const std::string &s)
void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)
{
if (const auto& _addressOffset = simConfig.addressOffset)
if (const auto& _addressOffset = simConfig.AddressOffset)
addressOffset = *_addressOffset;
if (const auto& _checkTLM2Protocol = simConfig.checkTLM2Protocol)
if (const auto& _checkTLM2Protocol = simConfig.CheckTLM2Protocol)
checkTLM2Protocol = *_checkTLM2Protocol;
if (const auto& _databaseRecording = simConfig.databaseRecording)
if (const auto& _databaseRecording = simConfig.DatabaseRecording)
databaseRecording = *_databaseRecording;
if (const auto& _debug = simConfig.debug)
if (const auto& _debug = simConfig.Debug)
debug = *_debug;
if (const auto& _enableWindowing = simConfig.enableWindowing)
if (const auto& _enableWindowing = simConfig.EnableWindowing)
enableWindowing = *_enableWindowing;
if (const auto& _powerAnalysis = simConfig.powerAnalysis)
if (const auto& _powerAnalysis = simConfig.PowerAnalysis)
{
powerAnalysis = *_powerAnalysis;
#ifndef DRAMPOWER
@@ -111,24 +111,24 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)
#endif
}
if (const auto& _simulationName = simConfig.simulationName)
if (const auto& _simulationName = simConfig.SimulationName)
simulationName = *_simulationName;
if (const auto& _simulationProgressBar = simConfig.simulationProgressBar)
if (const auto& _simulationProgressBar = simConfig.SimulationProgressBar)
simulationProgressBar = *_simulationProgressBar;
if (const auto& _useMalloc = simConfig.useMalloc)
if (const auto& _useMalloc = simConfig.UseMalloc)
useMalloc = *_useMalloc;
if (const auto& _windowSize = simConfig.windowSize)
if (const auto& _windowSize = simConfig.WindowSize)
windowSize = *_windowSize;
if (windowSize == 0)
SC_REPORT_FATAL("Configuration", "Minimum window size is 1");
if (const auto& _storeMode = simConfig.storeMode)
if (const auto& _storeMode = simConfig.StoreMode)
storeMode = [=] {
if (_storeMode == DRAMSys::Config::StoreMode::NoStorage)
if (_storeMode == DRAMSys::Config::StoreModeType::NoStorage)
return StoreMode::NoStorage;
else // (_storeMode == DRAMSys::Config::StoreMode::Store)
return StoreMode::Store;
@@ -137,151 +137,151 @@ void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)
void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig)
{
if (const auto& _pagePolicy = mcConfig.pagePolicy)
if (const auto& _pagePolicy = mcConfig.PagePolicy)
pagePolicy = [=] {
if (_pagePolicy == DRAMSys::Config::PagePolicy::Open)
if (_pagePolicy == DRAMSys::Config::PagePolicyType::Open)
return PagePolicy::Open;
else if (_pagePolicy == DRAMSys::Config::PagePolicy::OpenAdaptive)
else if (_pagePolicy == DRAMSys::Config::PagePolicyType::OpenAdaptive)
return PagePolicy::OpenAdaptive;
else if (_pagePolicy == DRAMSys::Config::PagePolicy::Closed)
else if (_pagePolicy == DRAMSys::Config::PagePolicyType::Closed)
return PagePolicy::Closed;
else
return PagePolicy::ClosedAdaptive;
}();
if (const auto& _scheduler = mcConfig.scheduler)
if (const auto& _scheduler = mcConfig.Scheduler)
scheduler = [=] {
if (_scheduler == DRAMSys::Config::Scheduler::Fifo)
if (_scheduler == DRAMSys::Config::SchedulerType::Fifo)
return Scheduler::Fifo;
else if (_scheduler == DRAMSys::Config::Scheduler::FrFcfs)
else if (_scheduler == DRAMSys::Config::SchedulerType::FrFcfs)
return Scheduler::FrFcfs;
else if (_scheduler == DRAMSys::Config::Scheduler::FrFcfsGrp)
else if (_scheduler == DRAMSys::Config::SchedulerType::FrFcfsGrp)
return Scheduler::FrFcfsGrp;
else if (_scheduler == DRAMSys::Config::Scheduler::GrpFrFcfs)
else if (_scheduler == DRAMSys::Config::SchedulerType::GrpFrFcfs)
return Scheduler::GrpFrFcfs;
else
return Scheduler::GrpFrFcfsWm;
}();
if (const auto& _highWatermark = mcConfig.highWatermark)
highWatermark = *mcConfig.highWatermark;
if (const auto& _highWatermark = mcConfig.HighWatermark)
highWatermark = *mcConfig.HighWatermark;
if (const auto& _lowWatermark = mcConfig.lowWatermark)
lowWatermark = *mcConfig.lowWatermark;
if (const auto& _lowWatermark = mcConfig.LowWatermark)
lowWatermark = *mcConfig.LowWatermark;
if (const auto& _schedulerBuffer = mcConfig.schedulerBuffer)
if (const auto& _schedulerBuffer = mcConfig.SchedulerBuffer)
schedulerBuffer = [=] {
if (_schedulerBuffer == DRAMSys::Config::SchedulerBuffer::Bankwise)
if (_schedulerBuffer == DRAMSys::Config::SchedulerBufferType::Bankwise)
return SchedulerBuffer::Bankwise;
else if (_schedulerBuffer == DRAMSys::Config::SchedulerBuffer::ReadWrite)
else if (_schedulerBuffer == DRAMSys::Config::SchedulerBufferType::ReadWrite)
return SchedulerBuffer::ReadWrite;
else
return SchedulerBuffer::Shared;
}();
if (const auto& _requestBufferSize = mcConfig.requestBufferSize)
requestBufferSize = *mcConfig.requestBufferSize;
if (const auto& _requestBufferSize = mcConfig.RequestBufferSize)
requestBufferSize = *mcConfig.RequestBufferSize;
if (requestBufferSize == 0)
SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!");
if (const auto& _cmdMux = mcConfig.cmdMux)
if (const auto& _cmdMux = mcConfig.CmdMux)
cmdMux = [=] {
if (_cmdMux == DRAMSys::Config::CmdMux::Oldest)
if (_cmdMux == DRAMSys::Config::CmdMuxType::Oldest)
return CmdMux::Oldest;
else
return CmdMux::Strict;
}();
if (const auto& _respQueue = mcConfig.respQueue)
if (const auto& _respQueue = mcConfig.RespQueue)
respQueue = [=] {
if (_respQueue == DRAMSys::Config::RespQueue::Fifo)
if (_respQueue == DRAMSys::Config::RespQueueType::Fifo)
return RespQueue::Fifo;
else
return RespQueue::Reorder;
}();
if (const auto& _refreshPolicy = mcConfig.refreshPolicy)
if (const auto& _refreshPolicy = mcConfig.RefreshPolicy)
refreshPolicy = [=] {
if (_refreshPolicy == DRAMSys::Config::RefreshPolicy::NoRefresh)
if (_refreshPolicy == DRAMSys::Config::RefreshPolicyType::NoRefresh)
return RefreshPolicy::NoRefresh;
else if (_refreshPolicy == DRAMSys::Config::RefreshPolicy::AllBank)
else if (_refreshPolicy == DRAMSys::Config::RefreshPolicyType::AllBank)
return RefreshPolicy::AllBank;
else if (_refreshPolicy == DRAMSys::Config::RefreshPolicy::PerBank)
else if (_refreshPolicy == DRAMSys::Config::RefreshPolicyType::PerBank)
return RefreshPolicy::PerBank;
else if (_refreshPolicy == DRAMSys::Config::RefreshPolicy::Per2Bank)
else if (_refreshPolicy == DRAMSys::Config::RefreshPolicyType::Per2Bank)
return RefreshPolicy::Per2Bank;
else // if (policy == DRAMSys::Config::RefreshPolicy::SameBank)
return RefreshPolicy::SameBank;
}();
if (const auto& _refreshMaxPostponed = mcConfig.refreshMaxPostponed)
if (const auto& _refreshMaxPostponed = mcConfig.RefreshMaxPostponed)
refreshMaxPostponed = *_refreshMaxPostponed;
if (const auto& _refreshMaxPulledin = mcConfig.refreshMaxPulledin)
if (const auto& _refreshMaxPulledin = mcConfig.RefreshMaxPulledin)
refreshMaxPulledin = *_refreshMaxPulledin;
if (const auto& _powerDownPolicy = mcConfig.powerDownPolicy)
if (const auto& _powerDownPolicy = mcConfig.PowerDownPolicy)
powerDownPolicy = [=] {
if (_powerDownPolicy == DRAMSys::Config::PowerDownPolicy::NoPowerDown)
if (_powerDownPolicy == DRAMSys::Config::PowerDownPolicyType::NoPowerDown)
return PowerDownPolicy::NoPowerDown;
else
return PowerDownPolicy::Staggered;
}();
if (const auto& _arbiter = mcConfig.arbiter)
if (const auto& _arbiter = mcConfig.Arbiter)
arbiter = [=] {
if (_arbiter == DRAMSys::Config::Arbiter::Simple)
if (_arbiter == DRAMSys::Config::ArbiterType::Simple)
return Arbiter::Simple;
else if (_arbiter == DRAMSys::Config::Arbiter::Fifo)
else if (_arbiter == DRAMSys::Config::ArbiterType::Fifo)
return Arbiter::Fifo;
else
return Arbiter::Reorder;
}();
if (const auto& _maxActiveTransactions = mcConfig.maxActiveTransactions)
if (const auto& _maxActiveTransactions = mcConfig.MaxActiveTransactions)
maxActiveTransactions = *_maxActiveTransactions;
if (const auto& _refreshManagement = mcConfig.refreshManagement)
if (const auto& _refreshManagement = mcConfig.RefreshManagement)
refreshManagement = *_refreshManagement;
if (const auto& _arbitrationDelayFw = mcConfig.arbitrationDelayFw)
if (const auto& _arbitrationDelayFw = mcConfig.ArbitrationDelayFw)
{
arbitrationDelayFw = std::round(sc_time(*_arbitrationDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
if (const auto& _arbitrationDelayBw = mcConfig.arbitrationDelayBw)
if (const auto& _arbitrationDelayBw = mcConfig.ArbitrationDelayBw)
{
arbitrationDelayBw = std::round(sc_time(*_arbitrationDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
if (const auto& _thinkDelayFw = mcConfig.thinkDelayFw)
if (const auto& _thinkDelayFw = mcConfig.ThinkDelayFw)
{
thinkDelayFw = std::round(sc_time(*_thinkDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
if (const auto& _thinkDelayBw = mcConfig.thinkDelayBw)
if (const auto& _thinkDelayBw = mcConfig.ThinkDelayBw)
{
thinkDelayBw = std::round(sc_time(*_thinkDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
if (const auto& _phyDelayFw = mcConfig.phyDelayFw)
if (const auto& _phyDelayFw = mcConfig.PhyDelayFw)
{
phyDelayFw = std::round(sc_time(*_phyDelayFw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
if (const auto& _phyDelayBw = mcConfig.phyDelayBw)
if (const auto& _phyDelayBw = mcConfig.PhyDelayBw)
{
phyDelayBw = std::round(sc_time(*_phyDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
{
auto _blockingReadDelay = mcConfig.blockingReadDelay.value_or(60);
auto _blockingReadDelay = mcConfig.BlockingReadDelay.value_or(60);
blockingReadDelay = std::round(sc_time(_blockingReadDelay, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
{
auto _blockingWriteDelay = mcConfig.blockingWriteDelay.value_or(60);
auto _blockingWriteDelay = mcConfig.BlockingWriteDelay.value_or(60);
blockingWriteDelay = std::round(sc_time(_blockingWriteDelay, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
}

18
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
View File

@@ -55,20 +55,20 @@ MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec,
banksPerChannel(banksPerChannel),
bankGroupsPerChannel(bankGroupsPerChannel),
devicesPerRank(devicesPerRank),
rowsPerBank(memSpec.memArchitectureSpec.entries.at("nbrOfRows")),
columnsPerRow(memSpec.memArchitectureSpec.entries.at("nbrOfColumns")),
defaultBurstLength(memSpec.memArchitectureSpec.entries.at("burstLength")),
maxBurstLength(memSpec.memArchitectureSpec.entries.find("maxBurstLength") !=
memSpec.memArchitectureSpec.entries.end()
? memSpec.memArchitectureSpec.entries.at("maxBurstLength")
rowsPerBank(memSpec.memarchitecturespec.entries.at("nbrOfRows")),
columnsPerRow(memSpec.memarchitecturespec.entries.at("nbrOfColumns")),
defaultBurstLength(memSpec.memarchitecturespec.entries.at("burstLength")),
maxBurstLength(memSpec.memarchitecturespec.entries.find("maxBurstLength") !=
memSpec.memarchitecturespec.entries.end()
? memSpec.memarchitecturespec.entries.at("maxBurstLength")
: defaultBurstLength),
dataRate(memSpec.memArchitectureSpec.entries.at("dataRate")),
bitWidth(memSpec.memArchitectureSpec.entries.at("width")),
dataRate(memSpec.memarchitecturespec.entries.at("dataRate")),
bitWidth(memSpec.memarchitecturespec.entries.at("width")),
dataBusWidth(bitWidth* devicesPerRank),
bytesPerBeat(dataBusWidth / 8),
defaultBytesPerBurst((defaultBurstLength* dataBusWidth) / 8),
maxBytesPerBurst((maxBurstLength* dataBusWidth) / 8),
fCKMHz(memSpec.memTimingSpec.entries.at("clkMhz")),
fCKMHz(memSpec.memtimingspec.entries.at("clkMhz")),
tCK(sc_time(1.0 / fCKMHz, SC_US)),
memoryId(memSpec.memoryId),
memoryType(memoryType),

94
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -45,61 +45,61 @@ using namespace tlm;
MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR3,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
tAL (tCK * memSpec.memTimingSpec.entries.at("AL")),
tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")),
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
iDD0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd0") : 0),
iDD2N (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2n") : 0),
iDD3N (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3n") : 0),
iDD4R (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4r") : 0),
iDD4W (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4w") : 0),
iDD5 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd5") : 0),
iDD6 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd6") : 0),
vDD (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("vdd") : 0),
iDD2P0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p0") : 0),
iDD2P1 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p1") : 0),
iDD3P0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p0") : 0),
iDD3P1 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p1") : 0)
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")),
tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
iDD0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0),
iDD2N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0),
iDD3N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0),
iDD4R (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0),
iDD4W (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0),
iDD5 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0),
iDD6 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0),
vDD (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0),
iDD2P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") : 0),
iDD2P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") : 0),
iDD3P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") : 0),
iDD3P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0)
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
if (!memSpec.memPowerSpec.has_value())
if (!memSpec.mempowerspec.has_value())
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
std::cout << headline << std::endl;

132
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -45,79 +45,79 @@ using namespace tlm;
MemSpecDDR4::MemSpecDDR4(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR4,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tRPRE (tCK * memSpec.memTimingSpec.entries.at("RPRE")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tREFI ((memSpec.memTimingSpec.entries.at("REFM") == 4) ?
(tCK * (static_cast<double>(memSpec.memTimingSpec.entries.at("REFI")) / 4)) :
((memSpec.memTimingSpec.entries.at("REFM") == 2) ?
(tCK * (static_cast<double>(memSpec.memTimingSpec.entries.at("REFI")) / 2)) :
(tCK * memSpec.memTimingSpec.entries.at("REFI")))),
tRFC ((memSpec.memTimingSpec.entries.at("REFM") == 4) ?
(tCK * memSpec.memTimingSpec.entries.at("RFC4")) :
((memSpec.memTimingSpec.entries.at("REFM") == 2) ?
(tCK * memSpec.memTimingSpec.entries.at("RFC2")) :
(tCK * memSpec.memTimingSpec.entries.at("RFC")))),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tCCD_S (tCK * memSpec.memTimingSpec.entries.at("CCD_S")),
tCCD_L (tCK * memSpec.memTimingSpec.entries.at("CCD_L")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRRD_S (tCK * memSpec.memTimingSpec.entries.at("RRD_S")),
tRRD_L (tCK * memSpec.memTimingSpec.entries.at("RRD_L")),
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
tAL (tCK * memSpec.memTimingSpec.entries.at("AL")),
tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")),
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
iDD0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd0") : 0),
iDD2N (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2n") : 0),
iDD3N (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3n") : 0),
iDD4R (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4r") : 0),
iDD4W (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4w") : 0),
iDD5 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd5") : 0),
iDD6 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd6") : 0),
vDD (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("vdd") : 0),
iDD02 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd02") : 0),
iDD2P0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p0") : 0),
iDD2P1 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p1") : 0),
iDD3P0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p0") : 0),
iDD3P1 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p1") : 0),
iDD62 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd62") : 0),
vDD2 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("vdd2") : 0)
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tRPRE (tCK * memSpec.memtimingspec.entries.at("RPRE")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWPRE (tCK * memSpec.memtimingspec.entries.at("WPRE")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tREFI ((memSpec.memtimingspec.entries.at("REFM") == 4) ?
(tCK * (static_cast<double>(memSpec.memtimingspec.entries.at("REFI")) / 4)) :
((memSpec.memtimingspec.entries.at("REFM") == 2) ?
(tCK * (static_cast<double>(memSpec.memtimingspec.entries.at("REFI")) / 2)) :
(tCK * memSpec.memtimingspec.entries.at("REFI")))),
tRFC ((memSpec.memtimingspec.entries.at("REFM") == 4) ?
(tCK * memSpec.memtimingspec.entries.at("RFC4")) :
((memSpec.memtimingspec.entries.at("REFM") == 2) ?
(tCK * memSpec.memtimingspec.entries.at("RFC2")) :
(tCK * memSpec.memtimingspec.entries.at("RFC")))),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tCCD_S (tCK * memSpec.memtimingspec.entries.at("CCD_S")),
tCCD_L (tCK * memSpec.memtimingspec.entries.at("CCD_L")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD_S (tCK * memSpec.memtimingspec.entries.at("RRD_S")),
tRRD_L (tCK * memSpec.memtimingspec.entries.at("RRD_L")),
tWTR_S (tCK * memSpec.memtimingspec.entries.at("WTR_S")),
tWTR_L (tCK * memSpec.memtimingspec.entries.at("WTR_L")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")),
tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
iDD0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0),
iDD2N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0),
iDD3N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0),
iDD4R (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0),
iDD4W (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0),
iDD5 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0),
iDD6 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0),
vDD (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0),
iDD02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0),
iDD2P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") : 0),
iDD2P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") : 0),
iDD3P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") : 0),
iDD3P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0),
iDD62 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0),
vDD2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0)
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
if (!memSpec.memPowerSpec.has_value())
if (!memSpec.mempowerspec.has_value())
SC_REPORT_WARNING("MemSpec", "No power spec defined!");
std::cout << headline << std::endl;

90
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -45,52 +45,52 @@ using namespace tlm;
MemSpecGDDR5::MemSpecGDDR5(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::GDDR5,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tCL (tCK * memSpec.memTimingSpec.entries.at("CL")),
tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")),
tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")),
tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
tXPN (tCK * memSpec.memTimingSpec.entries.at("XPN")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
t32AW (tCK * memSpec.memTimingSpec.entries.at("32AW")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")),
tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")),
tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")),
tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")),
tCL (tCK * memSpec.memtimingspec.entries.at("CL")),
tWCK2CKPIN (tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")),
tWCK2CK (tCK * memSpec.memtimingspec.entries.at("WCK2CK")),
tWCK2DQO (tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWCK2DQI (tCK * memSpec.memtimingspec.entries.at("WCK2DQI")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")),
tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCK * memSpec.memtimingspec.entries.at("PD")),
tXPN (tCK * memSpec.memtimingspec.entries.at("XPN")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memtimingspec.entries.at("REFIPB")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
t32AW (tCK * memSpec.memtimingspec.entries.at("32AW")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tLK (tCK * memSpec.memtimingspec.entries.at("LK")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;

90
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -45,52 +45,52 @@ using namespace tlm;
MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::GDDR5X,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tRL (tCK * memSpec.memTimingSpec.entries.at("CL")),
tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")),
tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")),
tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
t32AW (tCK * memSpec.memTimingSpec.entries.at("32AW")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("TRS"))
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")),
tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")),
tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")),
tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")),
tRL (tCK * memSpec.memtimingspec.entries.at("CL")),
tWCK2CKPIN (tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")),
tWCK2CK (tCK * memSpec.memtimingspec.entries.at("WCK2CK")),
tWCK2DQO (tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWCK2DQI (tCK * memSpec.memtimingspec.entries.at("WCK2DQI")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")),
tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCK * memSpec.memtimingspec.entries.at("PD")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memtimingspec.entries.at("REFIPB")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
t32AW (tCK * memSpec.memtimingspec.entries.at("32AW")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tLK (tCK * memSpec.memtimingspec.entries.at("LK")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("TRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;

96
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -45,55 +45,55 @@ using namespace tlm;
MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::GDDR6,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memArchitectureSpec.entries.at("per2BankOffset")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")),
tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")),
tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIpb")),
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCab")),
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCpb")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
tACTPDE (tCK * memSpec.memTimingSpec.entries.at("ACTPDE")),
tPREPDE (tCK * memSpec.memTimingSpec.entries.at("PREPDE")),
tREFPDE (tCK * memSpec.memTimingSpec.entries.at("REFPDE")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")),
tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")),
tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")),
tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tWCK2CKPIN (tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")),
tWCK2CK (tCK * memSpec.memtimingspec.entries.at("WCK2CK")),
tWCK2DQO (tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWCK2DQI (tCK * memSpec.memtimingspec.entries.at("WCK2DQI")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")),
tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")),
tPD (tCK * memSpec.memtimingspec.entries.at("PD")),
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")),
tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tLK (tCK * memSpec.memtimingspec.entries.at("LK")),
tACTPDE (tCK * memSpec.memtimingspec.entries.at("ACTPDE")),
tPREPDE (tCK * memSpec.memtimingspec.entries.at("PREPDE")),
tREFPDE (tCK * memSpec.memtimingspec.entries.at("REFPDE")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;

78
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -45,47 +45,47 @@ using namespace tlm;
MemSpecHBM2::MemSpecHBM2(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::HBM2,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tPL (tCK * memSpec.memTimingSpec.entries.at("PL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")),
tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")),
tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tPL (tCK * memSpec.memtimingspec.entries.at("PL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")),
tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")),
tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")),
tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")),
tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCKE + tCK),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRFCSB (tCK * memSpec.memTimingSpec.entries.at("RFCSB")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFISB (tCK * memSpec.memTimingSpec.entries.at("REFISB"))
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRFCSB (tCK * memSpec.memtimingspec.entries.at("RFCSB")),
tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFISB (tCK * memSpec.memtimingspec.entries.at("REFISB"))
{
commandLengthInCycles[Command::ACT] = 2;

78
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -45,47 +45,47 @@ using namespace tlm;
MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::LPDDR4,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCAB")),
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRPab (tCK * memSpec.memTimingSpec.entries.at("RPAB")),
tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPPB")),
tRCab (tCK * memSpec.memTimingSpec.entries.at("RCAB")),
tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCPB")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tRPST (tCK * memSpec.memTimingSpec.entries.at("RPST")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tDQSS (tCK * memSpec.memTimingSpec.entries.at("DQSS")),
tDQS2DQ (tCK * memSpec.memTimingSpec.entries.at("DQS2DQ")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")),
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tSR (tCK * memSpec.memTimingSpec.entries.at("SR")),
tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")),
tESCKE (tCK * memSpec.memTimingSpec.entries.at("ESCKE")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tCMDCKE (tCK * memSpec.memTimingSpec.entries.at("CMDCKE")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIPB")),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")),
tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")),
tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tDQSS (tCK * memSpec.memtimingspec.entries.at("DQSS")),
tDQS2DQ (tCK * memSpec.memtimingspec.entries.at("DQS2DQ")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tWPRE (tCK * memSpec.memtimingspec.entries.at("WPRE")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tSR (tCK * memSpec.memtimingspec.entries.at("SR")),
tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")),
tESCKE (tCK * memSpec.memtimingspec.entries.at("ESCKE")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tCMDCKE (tCK * memSpec.memtimingspec.entries.at("CMDCKE")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
{
commandLengthInCycles[Command::ACT] = 4;
commandLengthInCycles[Command::PREPB] = 2;

62
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -45,40 +45,40 @@ using namespace tlm;
MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::STTMRAM,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
tAL (tCK * memSpec.memTimingSpec.entries.at("AL")),
tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")),
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")),
tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;

108
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -45,67 +45,67 @@ using namespace tlm;
MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::WideIO,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tAC (tCK * memSpec.memTimingSpec.entries.at("AC")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")),
tCCD_R (tCK * memSpec.memTimingSpec.entries.at("CCD_R")),
tCCD_W (tCK * memSpec.memTimingSpec.entries.at("CCD_W")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
tTAW (tCK * memSpec.memTimingSpec.entries.at("TAW")),
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
iDD0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd0") : 0),
iDD2N (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2n") : 0),
iDD3N (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3n") : 0),
iDD4R (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4r") : 0),
iDD4W (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4w") : 0),
iDD5 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd5") : 0),
iDD6 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd6") : 0),
vDD (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("vdd") : 0),
iDD02 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd02") : 0),
iDD2P0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p0") : 0),
iDD2P02 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p02") : 0),
iDD2P1 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p1") : 0),
iDD2P12 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2p12") : 0),
iDD2N2 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd2n2") : 0),
iDD3P0 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p0") : 0),
iDD3P02 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p02") : 0),
iDD3P1 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p1") : 0),
iDD3P12 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3p12") : 0),
iDD3N2 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd3n2") : 0),
iDD4R2 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4r2") : 0),
iDD4W2 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd4w2") : 0),
iDD52 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd52") : 0),
iDD62 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("idd62") : 0),
vDD2 (memSpec.memPowerSpec.has_value() ? memSpec.memPowerSpec.value().entries.at("vdd2") : 0)
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tAC (tCK * memSpec.memtimingspec.entries.at("AC")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")),
tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")),
tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tTAW (tCK * memSpec.memtimingspec.entries.at("TAW")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
iDD0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0),
iDD2N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0),
iDD3N (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0),
iDD4R (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0),
iDD4W (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0),
iDD5 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0),
iDD6 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0),
vDD (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0),
iDD02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0),
iDD2P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") : 0),
iDD2P02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p02") : 0),
iDD2P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") : 0),
iDD2P12 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p12") : 0),
iDD2N2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n2") : 0),
iDD3P0 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") : 0),
iDD3P02 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p02") : 0),
iDD3P1 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0),
iDD3P12 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p12") : 0),
iDD3N2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n2") : 0),
iDD4R2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r2") : 0),
iDD4W2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w2") : 0),
iDD52 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd52") : 0),
iDD62 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0),
vDD2 (memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0)
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
if (!memSpec.memPowerSpec.has_value())
if (!memSpec.mempowerspec.has_value())
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
std::cout << headline << std::endl;

70
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -45,43 +45,43 @@ using namespace tlm;
MemSpecWideIO2::MemSpecWideIO2(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::WideIO2,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tDQSS (tCK * memSpec.memTimingSpec.entries.at("DQSS")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCPB")),
tRCab (tCK * memSpec.memTimingSpec.entries.at("RCAB")),
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPPB")),
tRPab (tCK * memSpec.memTimingSpec.entries.at("RPAB")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tREFI (tCK * static_cast<unsigned>(memSpec.memTimingSpec.entries.at("REFI")
* memSpec.memTimingSpec.entries.at("REFM"))),
tREFIpb (tCK * static_cast<unsigned>(memSpec.memTimingSpec.entries.at("REFIPB")
* memSpec.memTimingSpec.entries.at("REFM"))),
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCAB")),
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tDQSS (tCK * memSpec.memtimingspec.entries.at("DQSS")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")),
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")),
tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tREFI (tCK * static_cast<unsigned>(memSpec.memtimingspec.entries.at("REFI")
* memSpec.memtimingspec.entries.at("REFM"))),
tREFIpb (tCK * static_cast<unsigned>(memSpec.memtimingspec.entries.at("REFIPB")
* memSpec.memtimingspec.entries.at("REFM"))),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;

18
src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
View File

@@ -45,45 +45,45 @@
AddressDecoder::AddressDecoder(const Configuration& config, const DRAMSys::Config::AddressMapping& addressMapping)
{
if (const auto& channelBits = addressMapping.channelBits)
if (const auto &channelBits = addressMapping.CONGEN.CHANNEL_BIT)
{
std::copy(channelBits->begin(), channelBits->end(), std::back_inserter(vChannelBits));
}
if (const auto& rankBits = addressMapping.rankBits)
if (const auto &rankBits = addressMapping.CONGEN.RANK_BIT)
{
std::copy(rankBits->begin(), rankBits->end(), std::back_inserter(vRankBits));
}
if (const auto& bankGroupBits = addressMapping.bankGroupBits)
if (const auto& bankGroupBits = addressMapping.CONGEN.BANKGROUP_BIT)
{
std::copy(bankGroupBits->begin(), bankGroupBits->end(), std::back_inserter(vBankGroupBits));
}
if (const auto& byteBits = addressMapping.byteBits)
if (const auto &byteBits = addressMapping.CONGEN.BYTE_BIT)
{
std::copy(byteBits->begin(), byteBits->end(), std::back_inserter(vByteBits));
}
if (const auto& xorBits = addressMapping.xorBits)
if (const auto &xorBits = addressMapping.CONGEN.XOR)
{
for (const auto& xorBit : *xorBits)
{
vXor.emplace_back(xorBit.first, xorBit.second);
vXor.emplace_back(xorBit.FIRST, xorBit.SECOND);
}
}
if (const auto& bankBits = addressMapping.bankBits)
if (const auto &bankBits = addressMapping.CONGEN.BANK_BIT)
{
std::copy(bankBits->begin(), bankBits->end(), std::back_inserter(vBankBits));
}
if (const auto& rowBits = addressMapping.rowBits)
if (const auto &rowBits = addressMapping.CONGEN.ROW_BIT)
{
std::copy(rowBits->begin(), rowBits->end(), std::back_inserter(vRowBits));
}
if (const auto& columnBits = addressMapping.columnBits)
if (const auto &columnBits = addressMapping.CONGEN.COLUMN_BIT)
{
std::copy(columnBits->begin(), columnBits->end(), std::back_inserter(vColumnBits));
}

8
src/libdramsys/DRAMSys/simulation/DRAMSys.cpp
View File

@@ -86,9 +86,9 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name,
// Load configLib and initialize modules
// Important: The memSpec needs to be the first configuration to be loaded!
config.loadMemSpec(configLib.memSpec);
config.loadMCConfig(configLib.mcConfig);
config.loadSimConfig(configLib.simConfig);
config.loadMemSpec(configLib.memspec);
config.loadMCConfig(configLib.mcconfig);
config.loadSimConfig(configLib.simconfig);
// Setup the debug manager:
setupDebugManager(config.simulationName);
@@ -96,7 +96,7 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name,
if (initAndBind)
{
// Instantiate all internal DRAMSys modules:
instantiateModules(configLib.addressMapping);
instantiateModules(configLib.addressmapping);
// Connect all internal DRAMSys modules:
bindSockets();
report(headline);

10
src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp
View File

@@ -71,9 +71,9 @@ DRAMSysRecordable::DRAMSysRecordable(const sc_core::sc_module_name& name, const
// is prepended to the simulation name if found.
std::string traceName;
if (!configLib.simulationId.empty())
if (!configLib.simulationid.empty())
{
std::string sid = configLib.simulationId;
std::string sid = configLib.simulationid;
traceName = sid + '_' + config.simulationName;
}
else
@@ -111,8 +111,8 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName,
std::string recorderName = "tlmRecorder" + std::to_string(i);
tlmRecorders.emplace_back(recorderName, config, dbName);
tlmRecorders.back().recordMcConfig(::DRAMSys::Config::dump(configLib.mcConfig));
tlmRecorders.back().recordMemspec(::DRAMSys::Config::dump(configLib.memSpec));
tlmRecorders.back().recordMcConfig(nlohmann::json(configLib.mcconfig).dump());
tlmRecorders.back().recordMemspec(nlohmann::json(configLib.memspec).dump());
tlmRecorders.back().recordTraceNames(config.simulationName);
}
}
@@ -120,7 +120,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string& traceName,
void DRAMSysRecordable::instantiateModules(const std::string& traceName,
const ::DRAMSys::Config::Configuration& configLib)
{
addressDecoder = std::make_unique<AddressDecoder>(config, configLib.addressMapping);
addressDecoder = std::make_unique<AddressDecoder>(config, configLib.addressmapping);
addressDecoder->print();
// Create and properly initialize TLM recorders.

6
src/simulator/simulator/main.cpp
View File

@@ -99,16 +99,16 @@ int sc_main(int argc, char **argv)
// Instantiate DRAMSys:
std::unique_ptr<DRAMSys::DRAMSys> dramSys;
if (configLib.simConfig.databaseRecording.value_or(false))
if (configLib.simconfig.DatabaseRecording.value_or(false))
dramSys = std::make_unique<DRAMSys::DRAMSysRecordable>("DRAMSys", configLib);
else
dramSys = std::make_unique<DRAMSys::DRAMSys>("DRAMSys", configLib);
if (!configLib.traceSetup.has_value())
if (!configLib.tracesetup.has_value())
SC_REPORT_FATAL("sc_main", "No trace setup section provided.");
// Instantiate STL Players:
TraceSetup setup(dramSys->getConfig(), configLib.traceSetup.value(), resources, players);
TraceSetup setup(dramSys->getConfig(), configLib.tracesetup.value(), resources, players);
// Bind STL Players with DRAMSys:
for (auto& player : players)

88
src/util/DRAMSys/util/json.h
View File

@@ -1,5 +1,9 @@
/*
<<<<<<< HEAD
* Copyright (c) 2021, Technische Universität Kaiserslautern
=======
* Copyright (c) 2021, Technische Universit<69>t Kaiserslautern
>>>>>>> 6a800d9a (Refactor SimConfig to use new jsonify macro)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -40,11 +44,83 @@
#include "nlohmann/json.hpp"
#include <optional>
#include <string>
#include <variant>
using json_t = nlohmann::json;
namespace DRAMSys::util {
// See https://www.kdab.com/jsonify-with-nlohmann-json/
// Try to set the value of type T into the variant data if it fails, do nothing
template <typename T, typename... Ts>
void variant_from_json(const nlohmann::json &j, std::variant<Ts...> &data)
{
try {
data = j.get<T>();
} catch (...) {
}
}
template <typename T>
void optional_to_json(nlohmann::json &j, std::string_view name, const std::optional<T> &value)
{
if (value)
j[name] = *value;
}
template <class T>
void optional_from_json(const nlohmann::json &j, std::string_view name, std::optional<T> &value)
{
const auto it = j.find(name);
if (it != j.end())
value = it->get<T>();
else
value = std::nullopt;
}
template <typename>
constexpr bool is_optional = false;
template <typename T>
constexpr bool is_optional<std::optional<T>> = true;
template <typename T>
void extended_to_json(const char *key, nlohmann::json &j, const T &value)
{
if constexpr (is_optional<T>)
optional_to_json(j, key, value);
else
j[key] = value;
}
template <typename T>
void extended_from_json(const char *key, const nlohmann::json &j, T &value)
{
if constexpr (is_optional<T>)
optional_from_json(j, key, value);
else
j.at(key).get_to(value);
}
} // namespace DRAMSys::util
NLOHMANN_JSON_NAMESPACE_BEGIN
template <typename... Ts>
struct adl_serializer<std::variant<Ts...>>
{
static void to_json(nlohmann::json &j, const std::variant<Ts...> &data)
{
std::visit([&j](const auto &v) { j = v; }, data);
}
static void from_json(const nlohmann::json &j, std::variant<Ts...> &data)
{
// Call variant_from_json for all types, only one will succeed
(DRAMSys::util::variant_from_json<Ts>(j, data), ...);
}
};
template <typename T>
struct adl_serializer<std::optional<T>> {
static void to_json(json_t& j, const std::optional<T>& opt) {
@@ -66,6 +142,18 @@ struct adl_serializer<std::optional<T>> {
}
};
NLOHMANN_JSON_NAMESPACE_END
#define EXTEND_JSON_TO(v1) DRAMSys::util::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1);
#define EXTEND_JSON_FROM(v1) DRAMSys::util::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1);
#define NLOHMANN_JSONIFY_ALL_THINGS(Type, ...) \
inline void to_json(nlohmann::json &nlohmann_json_j, const Type &nlohmann_json_t) { \
NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_TO, __VA_ARGS__)) \
} \
inline void from_json(const nlohmann::json &nlohmann_json_j, Type &nlohmann_json_t) { \
NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \
}
#endif

30
tests/tests_configuration/CMakeLists.txt
View File

@@ -1,8 +1,26 @@
add_executable(simpletest "${CMAKE_CURRENT_LIST_DIR}/simpletest.cpp")
target_link_libraries(simpletest PRIVATE DRAMSys::config)
set_target_properties(simpletest PROPERTIES FOLDER tests/configuration)
###############################################
### tests_configuration ###
###############################################
cmake_minimum_required(VERSION 3.1.0)
add_executable(converter "${CMAKE_CURRENT_LIST_DIR}/converter.cpp")
target_link_libraries(converter PRIVATE DRAMSys::config)
set_target_properties(converter PROPERTIES FOLDER tests/configuration)
project(test_configuration)
add_executable(${PROJECT_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/test_configuration.cpp)
set_target_properties(${PROJECT_NAME} PROPERTIES FOLDER tests/configuration)
target_link_libraries(${PROJECT_NAME} PRIVATE
DRAMSys::config
gtest_main
)
gtest_discover_tests(${PROJECT_NAME}
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
add_executable(jsonconverter ${CMAKE_CURRENT_SOURCE_DIR}/jsonconverter.cpp)
target_link_libraries(jsonconverter PRIVATE DRAMSys::config)
set_target_properties(jsonconverter PROPERTIES FOLDER tests/configuration)
build_source_group()

4
tests/tests_configuration/converter.cpp → tests/tests_configuration/jsonconverter.cpp
View File

@@ -33,12 +33,12 @@
* Derek Christ
*/
#include <DRAMSys/config/DRAMSysConfiguration.h>
#include <nlohmann/json.hpp>
#include <fstream>
#include <iostream>
#include <DRAMSys/config/DRAMSysConfiguration.h>
int main(int argc, char **argv)
{
if (argc != 2)

212
tests/tests_configuration/reference.json Normal file
View File

@@ -0,0 +1,212 @@
{
"simulation": {
"addressmapping": {
"CONGEN": {
"BANKGROUP_BIT": [
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
],
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"RANK_BIT": [
33
],
"ROW_BIT": [
16
]
}
},
"mcconfig": {
"Arbiter": "Simple",
"CmdMux": "Oldest",
"HighWatermark": 0,
"LowWatermark": 0,
"MaxActiveTransactions": 128,
"PagePolicy": "Open",
"PowerDownPolicy": "NoPowerDown",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"RefreshPolicy": "AllBank",
"RequestBufferSize": 8,
"RespQueue": "Fifo",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise"
},
"memspec": {
"memarchitecturespec": {
"RAACDR": 1,
"RAAIMT": 32,
"RAAMMT": 96,
"burstLength": 16,
"cmdMode": 1,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfChannels": 2,
"nbrOfColumns": 2048,
"nbrOfDIMMRanks": 1,
"nbrOfDevices": 8,
"nbrOfLogicalRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"refMode": 1,
"width": 4
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",
"memtimingspec": {
"ACTPDEN": 2,
"CCD_L_WR2_slr": 16,
"CCD_L_WR_slr": 32,
"CCD_L_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_S_slr": 8,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"CCD_dlr": 0,
"CPDED": 8,
"FAW_dlr": 0,
"FAW_slr": 32,
"PD": 12,
"PPD": 2,
"PRPDEN": 2,
"RAS": 52,
"RCD": 22,
"RDDQS": 0,
"REFI1": 6240,
"REFI2": 3120,
"REFISB": 1560,
"REFPDEN": 2,
"REFSBRD_dlr": 0,
"REFSBRD_slr": 48,
"RFC1_dlr": 0,
"RFC1_dpr": 0,
"RFC1_slr": 312,
"RFC2_dlr": 0,
"RFC2_dpr": 0,
"RFC2_slr": 208,
"RFCsb_dlr": 0,
"RFCsb_slr": 184,
"RL": 22,
"RP": 22,
"RPRE": 1,
"RPST": 0,
"RRD_L_slr": 8,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"RTP": 12,
"RTRS": 2,
"WL": 20,
"WPRE": 2,
"WPST": 0,
"WR": 48,
"WTR_L": 16,
"WTR_S": 4,
"XP": 12,
"clkMhz": 1600
}
},
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "error.csv",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
},
"simulationid": "std::string_simulationId",
"tracesetup": [
{
"clkMhz": 100,
"name": "mytrace.stl"
},
{
"addressDistribution": "random",
"clkMhz": 100,
"name": "MyTestGen",
"numRequests": 1000,
"rwRatio": 0.5
},
{
"clkMhz": 100,
"maxPendingReadRequests": 8,
"name": "MyTestGen",
"states": [
{
"addressDistribution": "sequential",
"addressIncrement": 256,
"id": 0,
"maxAddress": 1024,
"numRequests": 1000,
"rwRatio": 0.5
},
{
"addressDistribution": "sequential",
"addressIncrement": 512,
"id": 1,
"maxAddress": 2048,
"minAddress": 1024,
"numRequests": 100,
"rwRatio": 0.75
}
],
"transitions": [
{
"from": 0,
"probability": 1.0,
"to": 1
}
]
},
{
"clkMhz": 100,
"name": "MyTestHammer",
"numRequests": 4000,
"rowIncrement": 2097152
}
]
}
}

50
tests/tests_configuration/resources/addressmapping/am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json Normal file
View File

@@ -0,0 +1,50 @@
{
"CONGEN": {
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
13,
14,
15
],
"BANK_BIT": [
16
],
"ROW_BIT": [
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
],
"CHANNEL_BIT": [
33
]
}
}

11
tests/tests_configuration/resources/ddr5-example.json Normal file
View File

@@ -0,0 +1,11 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "ddr5.json",
"simulationid": "ddr5-example",
"thermalconfig": "config.json",
"tracesetup": "ddr5-trace.json"
}
}

17
tests/tests_configuration/resources/mcconfig/fr_fcfs.json Normal file
View File

@@ -0,0 +1,17 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "AllBank",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128,
"RefreshManagement": false
}
}

77
tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json Normal file
View File

@@ -0,0 +1,77 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevices": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1,
"RAAIMT" : 32,
"RAAMMT" : 96,
"RAACDR" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 22,
"PPD": 2,
"RP": 22,
"RAS": 52,
"RL": 22,
"RTP": 12,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 20,
"WPRE": 2,
"WPST": 0,
"WR": 48,
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 8,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 184,
"RFCsb_dlr": 0,
"REFI1": 6240,
"REFI2": 3120,
"REFISB": 1560,
"REFSBRD_slr": 48,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 8,
"PD": 12,
"XP": 12,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 1600
}
}
}

19
tests/tests_configuration/resources/simconfig/ddr5.json Normal file
View File

@@ -0,0 +1,19 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

28
tests/tests_configuration/resources/tracesetup/ddr5-trace.json Normal file
View File

@@ -0,0 +1,28 @@
{
"tracesetup": [
{
"clkMhz": 2000,
"name": "ddr3_example.stl"
},
{
"clkMhz": 2000,
"name": "gen0",
"numRequests": 2000,
"rwRatio": 0.85,
"addressDistribution": "sequential",
"addressIncrement": 256,
"maxPendingReadRequests": 8,
"maxPendingWriteRequests": 8
},
{
"clkMhz": 2000,
"name": "gen1",
"numRequests": 2000,
"rwRatio": 0.85,
"addressDistribution": "random",
"seed": 123456,
"maxPendingReadRequests": 8,
"maxPendingWriteRequests": 8
}
]
}

564
tests/tests_configuration/test_configuration.cpp Normal file
View File

@@ -0,0 +1,564 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Derek Christ
*/
#include <DRAMSys/config/DRAMSysConfiguration.h>
#include <DRAMSys/util/json.h>
#include <fstream>
#include <gtest/gtest.h>
#include <iostream>
#include <unordered_map>
using namespace DRAMSys::Config;
class ConfigurationTest : public ::testing::Test
{
protected:
ConfigurationTest()
: memSpec(createMemSpec()),
tracePlayer(createTracePlayer()),
traceGeneratorOneState(createTraceGeneratorOneState()),
traceGeneratorMultipleStates(createTraceGeneratorMultipleStates()),
traceHammer(createTraceHammer())
{
}
static DRAMSys::Config::MemSpec createMemSpec();
static DRAMSys::Config::TracePlayer createTracePlayer();
static DRAMSys::Config::TrafficGenerator createTraceGeneratorOneState();
static DRAMSys::Config::TrafficGeneratorStateMachine createTraceGeneratorMultipleStates();
static DRAMSys::Config::TraceHammer createTraceHammer();
DRAMSys::Config::AddressMapping addressMapping{
{{{0, 1}},
{{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}},
{{16}},
{{13, 14, 15}},
{{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}},
{{33}},
std::nullopt,
std::nullopt,
std::nullopt}};
DRAMSys::Config::McConfig mcConfig{PagePolicyType::Open,
SchedulerType::FrFcfs,
0,
0,
SchedulerBufferType::Bankwise,
8,
CmdMuxType::Oldest,
RespQueueType::Fifo,
RefreshPolicyType::AllBank,
0,
0,
PowerDownPolicyType::NoPowerDown,
ArbiterType::Simple,
128,
{}};
DRAMSys::Config::SimConfig simConfig{0,
false,
true,
false,
false,
{"error.csv"},
42,
false,
{"ddr5"},
true,
DRAMSys::Config::StoreModeType::NoStorage,
false,
false,
1000};
DRAMSys::Config::MemSpec memSpec;
DRAMSys::Config::TracePlayer tracePlayer;
DRAMSys::Config::TrafficGenerator traceGeneratorOneState;
DRAMSys::Config::TrafficGeneratorStateMachine traceGeneratorMultipleStates;
DRAMSys::Config::TraceHammer traceHammer;
DRAMSys::Config::TraceSetup traceSetup{{tracePlayer, traceGeneratorOneState, traceGeneratorMultipleStates, traceHammer}};
DRAMSys::Config::Configuration configuration{
addressMapping,
mcConfig,
memSpec,
simConfig,
"std::string_simulationId",
traceSetup
};
};
DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
{
MemArchitectureSpecType memArchitectureSpec{{{"burstLength", 16},
{"dataRate", 2},
{"nbrOfBankGroups", 8},
{"nbrOfBanks", 16},
{"nbrOfColumns", 2048},
{"nbrOfRanks", 1},
{"nbrOfDIMMRanks", 1},
{"nbrOfPhysicalRanks", 1},
{"nbrOfLogicalRanks", 1},
{"nbrOfRows", 65536},
{"width", 4},
{"nbrOfDevices", 8},
{"nbrOfChannels", 2},
{"cmdMode", 1},
{"refMode", 1},
{"RAAIMT", 32},
{"RAAMMT", 96},
{"RAACDR", 1}}};
MemTimingSpecType memTimingSpec{{{
{"RCD", 22}, {"PPD", 2}, {"RP", 22}, {"RAS", 52},
{"RL", 22}, {"RTP", 12}, {"RPRE", 1}, {"RPST", 0},
{"RDDQS", 0}, {"WL", 20}, {"WPRE", 2}, {"WPST", 0},
{"WR", 48}, {"CCD_L_slr", 8}, {"CCD_L_WR_slr", 32}, {"CCD_L_WR2_slr", 16},
{"CCD_S_slr", 8}, {"CCD_S_WR_slr", 8}, {"CCD_dlr", 0}, {"CCD_WR_dlr", 0},
{"CCD_WR_dpr", 0}, {"RRD_L_slr", 8}, {"RRD_S_slr", 8}, {"RRD_dlr", 0},
{"FAW_slr", 32}, {"FAW_dlr", 0}, {"WTR_L", 16}, {"WTR_S", 4},
{"RFC1_slr", 312}, {"RFC2_slr", 208}, {"RFC1_dlr", 0}, {"RFC2_dlr", 0},
{"RFC1_dpr", 0}, {"RFC2_dpr", 0}, {"RFCsb_slr", 184}, {"RFCsb_dlr", 0},
{"REFI1", 6240}, {"REFI2", 3120}, {"REFISB", 1560}, {"REFSBRD_slr", 48},
{"REFSBRD_dlr", 0}, {"RTRS", 2}, {"CPDED", 8}, {"PD", 12},
{"XP", 12}, {"ACTPDEN", 2}, {"PRPDEN", 2}, {"REFPDEN", 2},
{"clkMhz", 1600},
}}};
return {memArchitectureSpec, "JEDEC_2x8x2Gbx4_DDR5-3200A", "DDR5", memTimingSpec, {}};
}
DRAMSys::Config::TracePlayer ConfigurationTest::createTracePlayer()
{
DRAMSys::Config::TracePlayer player;
player.clkMhz = 100;
player.name = "mytrace.stl";
return player;
}
DRAMSys::Config::TrafficGenerator ConfigurationTest::createTraceGeneratorOneState()
{
DRAMSys::Config::TrafficGenerator gen;
gen.clkMhz = 100;
gen.name = "MyTestGen";
gen.numRequests = 1000;
gen.rwRatio = 0.5;
gen.addressDistribution = DRAMSys::Config::AddressDistribution::Random;
gen.addressIncrement = {};
gen.minAddress = {};
gen.maxAddress = {};
gen.clksPerRequest = {};
return gen;
}
DRAMSys::Config::TrafficGeneratorStateMachine ConfigurationTest::createTraceGeneratorMultipleStates()
{
DRAMSys::Config::TrafficGeneratorStateMachine gen;
gen.clkMhz = 100;
gen.name = "MyTestGen";
gen.maxPendingReadRequests = 8;
DRAMSys::Config::TrafficGeneratorActiveState state0;
state0.numRequests = 1000;
state0.rwRatio = 0.5;
state0.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
state0.addressIncrement = 256;
state0.minAddress = {};
state0.maxAddress = 1024;
state0.clksPerRequest = {};
state0.id = 0;
DRAMSys::Config::TrafficGeneratorActiveState state1;
state1.numRequests = 100;
state1.rwRatio = 0.75;
state1.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
state1.addressIncrement = 512;
state1.minAddress = 1024;
state1.maxAddress = 2048;
state1.clksPerRequest = {};
state1.id = 1;
gen.states.push_back(state0);
gen.states.push_back(state1);
DRAMSys::Config::TrafficGeneratorStateTransition transistion0{0, 1, 1.0};
gen.transitions.push_back(transistion0);
return gen;
}
DRAMSys::Config::TraceHammer ConfigurationTest::createTraceHammer()
{
DRAMSys::Config::TraceHammer hammer;
hammer.clkMhz = 100;
hammer.name = "MyTestHammer";
hammer.numRequests = 4000;
hammer.rowIncrement = 2097152;
return hammer;
}
TEST_F(ConfigurationTest, ToJson)
{
json_t config_json;
config_json["simulation"] = configuration;
std::ifstream file("reference.json");
ASSERT_TRUE(file.is_open());
json_t reference_json = json_t::parse(file);
std::cout << reference_json.dump(4) << std::endl;
EXPECT_EQ(config_json, reference_json);
}
TEST(Configuration, FromToJson)
{
std::ifstream file("reference.json");
ASSERT_TRUE(file.is_open());
json_t reference_json = json_t::parse(file);
DRAMSys::Config::Configuration reference_configuration =
reference_json["simulation"].get<DRAMSys::Config::Configuration>();
json_t new_json;
new_json["simulation"] = reference_configuration;
EXPECT_EQ(new_json, reference_json);
}
TEST_F(ConfigurationTest, DumpConfiguration)
{
// This test does not test anything. It just dumps the configuration to stdout for manual
// inspection.
json_t json;
json["simulation"] = configuration;
std::cout << json.dump(4) << std::endl;
}
TEST(Configuration, ResourceDirectory)
{
// Test should not throw exceptions
Configuration config = from_path("resources/ddr5-example.json", "resources");
}
TEST(Configuration, FromPath)
{
// Test should not throw exceptions
Configuration config = from_path("reference.json");
}
TEST_F(ConfigurationTest, SimConfig)
{
std::string_view simconfig_string = R"(
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "error.csv",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}
)";
json_t simconfig_reference = json_t::parse(simconfig_string);
json_t simconfig_test;
simconfig_test[SimConfig::KEY] = simConfig;
EXPECT_EQ(simconfig_test, simconfig_reference);
}
TEST_F(ConfigurationTest, McConfig)
{
std::string_view mcconfig_string = R"(
{
"mcconfig": {
"Arbiter": "Simple",
"CmdMux": "Oldest",
"HighWatermark": 0,
"LowWatermark": 0,
"MaxActiveTransactions": 128,
"PagePolicy": "Open",
"PowerDownPolicy": "NoPowerDown",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"RefreshPolicy": "AllBank",
"RequestBufferSize": 8,
"RespQueue": "Fifo",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise"
}
}
)";
json_t mcconfig_reference = json_t::parse(mcconfig_string);
json_t mcconfig_test;
mcconfig_test[McConfig::KEY] = mcConfig;
EXPECT_EQ(mcconfig_test, mcconfig_reference);
}
TEST_F(ConfigurationTest, MemSpec)
{
std::string_view memspec_string = R"(
{
"memspec": {
"memarchitecturespec": {
"RAACDR": 1,
"RAAIMT": 32,
"RAAMMT": 96,
"burstLength": 16,
"cmdMode": 1,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfChannels": 2,
"nbrOfColumns": 2048,
"nbrOfDIMMRanks": 1,
"nbrOfDevices": 8,
"nbrOfLogicalRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"refMode": 1,
"width": 4
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",
"memtimingspec": {
"ACTPDEN": 2,
"CCD_L_WR2_slr": 16,
"CCD_L_WR_slr": 32,
"CCD_L_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_S_slr": 8,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"CCD_dlr": 0,
"CPDED": 8,
"FAW_dlr": 0,
"FAW_slr": 32,
"PD": 12,
"PPD": 2,
"PRPDEN": 2,
"RAS": 52,
"RCD": 22,
"RDDQS": 0,
"REFI1": 6240,
"REFI2": 3120,
"REFISB": 1560,
"REFPDEN": 2,
"REFSBRD_dlr": 0,
"REFSBRD_slr": 48,
"RFC1_dlr": 0,
"RFC1_dpr": 0,
"RFC1_slr": 312,
"RFC2_dlr": 0,
"RFC2_dpr": 0,
"RFC2_slr": 208,
"RFCsb_dlr": 0,
"RFCsb_slr": 184,
"RL": 22,
"RP": 22,
"RPRE": 1,
"RPST": 0,
"RRD_L_slr": 8,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"RTP": 12,
"RTRS": 2,
"WL": 20,
"WPRE": 2,
"WPST": 0,
"WR": 48,
"WTR_L": 16,
"WTR_S": 4,
"XP": 12,
"clkMhz": 1600
}
}
}
)";
json_t memspec_reference = json_t::parse(memspec_string);
json_t memspec_test;
memspec_test[MemSpec::KEY] = memSpec;
EXPECT_EQ(memspec_test, memspec_reference);
}
TEST_F(ConfigurationTest, AddressMapping)
{
std::string_view addressmapping_string = R"(
{
"CONGEN": {
"BANKGROUP_BIT": [
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
],
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"RANK_BIT": [
33
],
"ROW_BIT": [
16
]
}
}
)";
json_t addressmapping_reference = json_t::parse(addressmapping_string);
json_t addressmapping_test = addressMapping;
EXPECT_EQ(addressmapping_test, addressmapping_reference);
}
TEST_F(ConfigurationTest, TraceSetup)
{
std::string_view tracesetup_string = R"(
{
"tracesetup": [
{
"clkMhz": 100,
"name": "mytrace.stl"
},
{
"addressDistribution": "random",
"clkMhz": 100,
"name": "MyTestGen",
"numRequests": 1000,
"rwRatio": 0.5
},
{
"clkMhz": 100,
"maxPendingReadRequests": 8,
"name": "MyTestGen",
"states": [
{
"addressDistribution": "sequential",
"addressIncrement": 256,
"id": 0,
"maxAddress": 1024,
"numRequests": 1000,
"rwRatio": 0.5
},
{
"addressDistribution": "sequential",
"addressIncrement": 512,
"id": 1,
"maxAddress": 2048,
"minAddress": 1024,
"numRequests": 100,
"rwRatio": 0.75
}
],
"transitions": [
{
"from": 0,
"probability": 1.0,
"to": 1
}
]
},
{
"clkMhz": 100,
"name": "MyTestHammer",
"numRequests": 4000,
"rowIncrement": 2097152
}
]
}
)";
json_t tracesetup_reference = json_t::parse(tracesetup_string);
json_t tracesetup_test;
tracesetup_test[TraceSetupConstants::KEY] = traceSetup;
EXPECT_EQ(tracesetup_test, tracesetup_reference);
}

110
tests/tests_dramsys/CommandMuxTests.cpp
View File

@@ -1,110 +0,0 @@
///*
// * Copyright (c) 2019, Technische Universität Kaiserslautern
// * All rights reserved.
// *
// * Redistribution and use in source and binary forms, with or without
// * modification, are permitted provided that the following conditions are
// * met:
// *
// * 1. Redistributions of source code must retain the above copyright notice,
// * this list of conditions and the following disclaimer.
// *
// * 2. Redistributions in binary form must reproduce the above copyright
// * notice, this list of conditions and the following disclaimer in the
// * documentation and/or other materials provided with the distribution.
// *
// * 3. Neither the name of the copyright holder nor the names of its
// * contributors may be used to endorse or promote products derived from
// * this software without specific prior written permission.
// *
// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *
// * Authors:
// * Lukas Steiner
// */
//
//#include <gtest/gtest.h>
//#include <tlm.h>
//#include <utility>
//#include <vector>
//
//#include <DRAMSys/controller/cmdmux/CmdMuxOldest.h>
//#include <DRAMSys/controller/Command.h>
//
//using namespace DRAMSys;
//
//class CommandMuxState
//{
//public:
// Command firstCommand;
// Command secondCommand;
// Command resultCommand;
//};
//
//class CommandMuxTestBase : public testing::Test
//{
//public:
// CommandMux *commandMux;
//
// tlm_generic_payload *firstPayload;
// tlm_generic_payload *secondPayload;
//
// std::pair<Command, tlm_generic_payload *> firstPair;
// std::pair<Command, tlm_generic_payload *> secondPair;
//
// std::vector<std::pair<Command, tlm_generic_payload *>> readyCommands;
//
// std::pair<Command, tlm_generic_payload *> result;
//
// CommandMuxTestBase()
// {
// commandMux = new CommandMux();
// firstPayload = new tlm_generic_payload();
// secondPayload = new tlm_generic_payload();
// }
//
// ~CommandMuxTestBase()
// {
// delete commandMux;
// delete firstPayload;
// delete secondPayload;
// }
//};
//
//class CommandMuxTestParam : public CommandMuxTestBase, public testing::WithParamInterface<CommandMuxState>
//{
//public:
// CommandMuxTestParam()
// {
// commandMux->insertPayload(firstPayload);
// commandMux->insertPayload(secondPayload);
//
// firstPair.first = GetParam().firstCommand;
// firstPair.second = firstPayload;
// secondPair.first = GetParam().secondCommand;
// secondPair.second = secondPayload;
//
// readyCommands.push_back(secondPair);
// readyCommands.push_back(firstPair);
// result = commandMux->selectCommand(readyCommands);
// }
//};
//
//TEST_P(CommandMuxTestParam, satisfiesCommandOrder)
//{
// EXPECT_EQ(result.first, GetParam().resultCommand);
//}
//
//INSTANTIATE_TEST_CASE_P(Default, CommandMuxTestParam, testing::Values(
// CommandMuxState{Command::RD, Command::WR, Command::RD},
// CommandMuxState{Command::RD, Command::ACT, Command::ACT}));