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Merge branch 'work/DDR5' into 'develop'

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Implement new DDR5 tCCD_M timings

See merge request ems/astdm/modeling.dram/dram.sys.5!13
This commit is contained in:
Lukas Steiner
2023-04-12 13:53:39 +00:00
parent daecc19252 5f1c74790b
commit a95db95030
24 changed files with 143 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 9,
"CCD_L_WR_slr": 36,
"CCD_L_WR2_slr": 18,
"CCD_M_slr": 9,
"CCD_M_WR_slr": 36,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 18,
"WTR_M": 18,
"WTR_S": 5,
"RFC1_slr": 351,
"RFC2_slr": 234,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 10,
"CCD_L_WR_slr": 40,
"CCD_L_WR2_slr": 20,
"CCD_M_slr": 10,
"CCD_M_WR_slr": 40,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 20,
"WTR_M": 20,
"WTR_S": 5,
"RFC1_slr": 390,
"RFC2_slr": 260,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 11,
"CCD_L_WR_slr": 44,
"CCD_L_WR2_slr": 22,
"CCD_M_slr": 11,
"CCD_M_WR_slr": 44,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 22,
"WTR_M": 22,
"WTR_S": 6,
"RFC1_slr": 429,
"RFC2_slr": 286,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 12,
"CCD_L_WR_slr": 48,
"CCD_L_WR2_slr": 24,
"CCD_M_slr": 12,
"CCD_M_WR_slr": 48,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 24,
"WTR_M": 24,
"WTR_S": 6,
"RFC1_slr": 468,
"RFC2_slr": 312,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 13,
"CCD_L_WR_slr": 52,
"CCD_L_WR2_slr": 26,
"CCD_M_slr": 13,
"CCD_M_WR_slr": 52,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 26,
"WTR_M": 26,
"WTR_S": 7,
"RFC1_slr": 507,
"RFC2_slr": 338,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 14,
"CCD_L_WR_slr": 56,
"CCD_L_WR2_slr": 28,
"CCD_M_slr": 14,
"CCD_M_WR_slr": 56,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 28,
"WTR_M": 28,
"WTR_S": 7,
"RFC1_slr": 546,
"RFC2_slr": 364,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 15,
"CCD_L_WR_slr": 60,
"CCD_L_WR2_slr": 30,
"CCD_M_slr": 15,
"CCD_M_WR_slr": 60,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 30,
"WTR_M": 30,
"WTR_S": 8,
"RFC1_slr": 585,
"RFC2_slr": 390,

3
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 16,
"CCD_L_WR_slr": 64,
"CCD_L_WR2_slr": 32,
"CCD_M_slr": 16,
"CCD_M_WR_slr": 64,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 32,
"WTR_M": 32,
"WTR_S": 8,
"RFC1_slr": 624,
"RFC2_slr": 416,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 9,
"CCD_L_WR_slr": 36,
"CCD_L_WR2_slr": 18,
"CCD_M_slr": 9,
"CCD_M_WR_slr": 36,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 18,
"WTR_M": 18,
"WTR_S": 5,
"RFC1_slr": 351,
"RFC2_slr": 234,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 10,
"CCD_L_WR_slr": 40,
"CCD_L_WR2_slr": 20,
"CCD_M_slr": 10,
"CCD_M_WR_slr": 40,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 20,
"WTR_M": 20,
"WTR_S": 5,
"RFC1_slr": 390,
"RFC2_slr": 260,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 11,
"CCD_L_WR_slr": 44,
"CCD_L_WR2_slr": 22,
"CCD_M_slr": 11,
"CCD_M_WR_slr": 44,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 22,
"WTR_M": 22,
"WTR_S": 6,
"RFC1_slr": 429,
"RFC2_slr": 286,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 12,
"CCD_L_WR_slr": 48,
"CCD_L_WR2_slr": 24,
"CCD_M_slr": 12,
"CCD_M_WR_slr": 48,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 24,
"WTR_M": 24,
"WTR_S": 6,
"RFC1_slr": 468,
"RFC2_slr": 312,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 13,
"CCD_L_WR_slr": 52,
"CCD_L_WR2_slr": 26,
"CCD_M_slr": 13,
"CCD_M_WR_slr": 52,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 26,
"WTR_M": 26,
"WTR_S": 7,
"RFC1_slr": 507,
"RFC2_slr": 338,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 14,
"CCD_L_WR_slr": 56,
"CCD_L_WR2_slr": 28,
"CCD_M_slr": 14,
"CCD_M_WR_slr": 56,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 28,
"WTR_M": 28,
"WTR_S": 7,
"RFC1_slr": 546,
"RFC2_slr": 364,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 15,
"CCD_L_WR_slr": 60,
"CCD_L_WR2_slr": 30,
"CCD_M_slr": 15,
"CCD_M_WR_slr": 60,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 30,
"WTR_M": 30,
"WTR_S": 8,
"RFC1_slr": 585,
"RFC2_slr": 390,

3
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 16,
"CCD_L_WR_slr": 64,
"CCD_L_WR2_slr": 32,
"CCD_M_slr": 16,
"CCD_M_WR_slr": 64,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
@@ -50,6 +52,7 @@
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 32,
"WTR_M": 32,
"WTR_S": 8,
"RFC1_slr": 624,
"RFC2_slr": 416,

5
configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json
View File

@@ -39,6 +39,8 @@
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_L_WR2_slr": 16,
"CCD_M_slr": 8,
"CCD_M_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 8,
@@ -49,7 +51,8 @@
"RRD_dlr": 4,
"FAW_slr": 32,
"FAW_dlr": 16,
"WTR_L": 16,
"WTR_L": 16,
"WTR_M": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,

3
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -84,6 +84,8 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
tCCD_L_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_slr")),
tCCD_L_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR_slr")),
tCCD_L_WR2_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR2_slr")),
tCCD_M_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_M_slr")),
tCCD_M_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_M_WR_slr")),
tCCD_S_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_slr")),
tCCD_S_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_WR_slr")),
tCCD_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_dlr")),
@@ -95,6 +97,7 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
tFAW_slr (tCK * memSpec.memTimingSpec.entries.at("FAW_slr")),
tFAW_dlr (tCK * memSpec.memTimingSpec.entries.at("FAW_dlr")),
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
tWTR_M (tCK * memSpec.memTimingSpec.entries.at("WTR_M")),
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
tRFC_slr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_slr")
: tCK * memSpec.memTimingSpec.entries.at("RFC2_slr")),

3
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
View File

@@ -74,6 +74,8 @@ public:
const sc_core::sc_time tCCD_L_slr;
const sc_core::sc_time tCCD_L_WR_slr;
const sc_core::sc_time tCCD_L_WR2_slr;
const sc_core::sc_time tCCD_M_slr;
const sc_core::sc_time tCCD_M_WR_slr;
const sc_core::sc_time tCCD_S_slr;
const sc_core::sc_time tCCD_S_WR_slr;
const sc_core::sc_time tCCD_dlr;
@@ -85,6 +87,7 @@ public:
const sc_core::sc_time tFAW_slr;
const sc_core::sc_time tFAW_dlr;
const sc_core::sc_time tWTR_L;
const sc_core::sc_time tWTR_M;
const sc_core::sc_time tWTR_S;
const sc_core::sc_time tRFC_slr;
const sc_core::sc_time tRFC_dlr;

99
extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
View File

@@ -104,6 +104,7 @@ CheckerDDR5::CheckerDDR5(const Configuration& config)
tRDWR_ddr = memSpec->tRL - memSpec->tWL + tBURST16 + memSpec->tRTRS
- memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE;
tCCD_L_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_L;
tCCD_M_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_M; // tWTR_M is max(16nck, 10ns)
tCCD_S_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_S;
tCCD_WTR_dlr = memSpec->tWL + tBURST16 + memSpec->tWTR_S;
tWRWR_dpr = std::max(memSpec->tCCD_WR_dpr, tBURST16 + memSpec->tRTRS);
@@ -140,10 +141,14 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_slr);
lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalRank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr);
@@ -178,7 +183,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_slr);
lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalRank.ID()];
if (lastCommandStart != sc_max_time())
@@ -224,13 +229,22 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
}
}
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr + tBURST16);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr);
}
lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalRank.ID()];
@@ -274,9 +288,9 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr + tBURST16);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr);
}
lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()];
@@ -419,22 +433,47 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
}
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
{
if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32)
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32)
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr);
}
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr);
}
else
{
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr);
}
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != lastScheduledByCommandAndBank[Command::WR][bank.ID()]) // different bank
{
if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32)
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr);
}
else
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr);
}
}
}
else // no RMW
{
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32)
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr);
}
else
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr);
}
}
}
@@ -470,22 +509,34 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
}
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
{
if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32)
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr);
if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32)
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr);
}
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr);
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr);
}
}
else
}
else // no RMW
{
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr);
if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32)
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr);
}
else
{
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr);
}
}
}

1
extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h
View File

@@ -96,6 +96,7 @@ private:
sc_core::sc_time tRDWR_dpr;
sc_core::sc_time tRDWR_ddr;
sc_core::sc_time tCCD_L_WTR_slr;
sc_core::sc_time tCCD_M_WTR_slr;
sc_core::sc_time tCCD_S_WTR_slr;
sc_core::sc_time tCCD_WTR_dlr;
sc_core::sc_time tWRWR_dpr;