From 49954df6ee365dcde7cf88926ead84cbb2578f7b Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 6 Apr 2023 10:38:48 +0200 Subject: [PATCH 1/5] Add tCCD_M DDR5 timings, MemSpecs still incomplete --- .../memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json | 3 + .../configuration/memspec/MemSpecDDR5.cpp | 3 + .../configuration/memspec/MemSpecDDR5.h | 3 + .../controller/checker/CheckerDDR5.cpp | 74 ++++++++++++++++--- .../DRAMSys/controller/checker/CheckerDDR5.h | 1 + 5 files changed, 73 insertions(+), 11 deletions(-) diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json index 9b3e1e4e..8f72eba6 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 8, "CCD_L_WR_slr": 32, "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, "RFC1_slr": 312, "RFC2_slr": 208, diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index 1558946a..f58f086b 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -84,6 +84,8 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) tCCD_L_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_slr")), tCCD_L_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR_slr")), tCCD_L_WR2_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR2_slr")), + tCCD_M_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_M_slr")), + tCCD_M_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_M_WR_slr")), tCCD_S_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_slr")), tCCD_S_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_WR_slr")), tCCD_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_dlr")), @@ -95,6 +97,7 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) tFAW_slr (tCK * memSpec.memTimingSpec.entries.at("FAW_slr")), tFAW_dlr (tCK * memSpec.memTimingSpec.entries.at("FAW_dlr")), tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")), + tWTR_M (tCK * memSpec.memTimingSpec.entries.at("WTR_M")), tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), tRFC_slr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_slr") : tCK * memSpec.memTimingSpec.entries.at("RFC2_slr")), diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h index 156d2a96..485d229b 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h @@ -74,6 +74,8 @@ public: const sc_core::sc_time tCCD_L_slr; const sc_core::sc_time tCCD_L_WR_slr; const sc_core::sc_time tCCD_L_WR2_slr; + const sc_core::sc_time tCCD_M_slr; + const sc_core::sc_time tCCD_M_WR_slr; const sc_core::sc_time tCCD_S_slr; const sc_core::sc_time tCCD_S_WR_slr; const sc_core::sc_time tCCD_dlr; @@ -85,6 +87,7 @@ public: const sc_core::sc_time tFAW_slr; const sc_core::sc_time tFAW_dlr; const sc_core::sc_time tWTR_L; + const sc_core::sc_time tWTR_M; const sc_core::sc_time tWTR_S; const sc_core::sc_time tRFC_slr; const sc_core::sc_time tRFC_dlr; diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index d1c9d87b..15d53f92 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -104,6 +104,7 @@ CheckerDDR5::CheckerDDR5(const Configuration& config) tRDWR_ddr = memSpec->tRL - memSpec->tWL + tBURST16 + memSpec->tRTRS - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; tCCD_L_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_L; + tCCD_M_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_M; // tWTR_M is max(16nck, 10ns) tCCD_S_WTR_slr = memSpec->tWL + tBURST16 + memSpec->tWTR_S; tCCD_WTR_dlr = memSpec->tWL + tBURST16 + memSpec->tWTR_S; tWRWR_dpr = std::max(memSpec->tCCD_WR_dpr, tBURST16 + memSpec->tRTRS); @@ -140,10 +141,14 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_slr); + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); @@ -176,10 +181,14 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_slr); + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); @@ -224,13 +233,22 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + } + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr + tBURST16); else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr); } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalRank.ID()]; @@ -270,13 +288,22 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + } + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr + tBURST16); else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_M_WTR_slr); } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; @@ -419,10 +446,10 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) { - if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); @@ -438,6 +465,19 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); + } + else + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); + } + } + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); @@ -470,20 +510,32 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != sc_max_time()) + { + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + { + if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + } + } + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); } else { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); } diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h index c03cd051..a9f2e3e0 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h @@ -96,6 +96,7 @@ private: sc_core::sc_time tRDWR_dpr; sc_core::sc_time tRDWR_ddr; sc_core::sc_time tCCD_L_WTR_slr; + sc_core::sc_time tCCD_M_WTR_slr; sc_core::sc_time tCCD_S_WTR_slr; sc_core::sc_time tCCD_WTR_dlr; sc_core::sc_time tWRWR_dpr; From 60b2bcbffa6cc533ae97f4c9d44681fe37c5e4c4 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 11 Apr 2023 14:08:32 +0200 Subject: [PATCH 2/5] Fix DDR5 write-to-write delay in TimingChecker --- .../controller/checker/CheckerDDR5.cpp | 47 ++++++++++++++----- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index 15d53f92..0eb80250 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -453,14 +453,25 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); } else { if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); - else + } + } + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) + { + if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); + } + else + { + if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); } } @@ -513,11 +524,14 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != sc_max_time()) { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) { - if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); - else + } + else + { + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); } } @@ -527,20 +541,29 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic { if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); - else + if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); } else { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); - else + if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); } } + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) + { + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); + } + else + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); + } + } + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); From 949cf944bc37a6ff4566b8f96d8895977110dfb1 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 11 Apr 2023 14:27:26 +0200 Subject: [PATCH 3/5] Update tCCD_M timings in memspecs for DDR5 --- configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json | 3 +++ configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json | 3 +++ configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json | 3 +++ configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json | 5 ++++- 19 files changed, 58 insertions(+), 1 deletion(-) diff --git a/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json b/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json index a53f77d8..e4bdd037 100644 --- a/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 8, "CCD_L_WR_slr": 32, "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, "RFC1_slr": 312, "RFC2_slr": 208, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json index 4e65f215..f719e72a 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 8, "CCD_L_WR_slr": 32, "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, "RFC1_slr": 312, "RFC2_slr": 208, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json index ba477a9b..359b362a 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 9, "CCD_L_WR_slr": 36, "CCD_L_WR2_slr": 18, + "CCD_M_slr": 9, + "CCD_M_WR_slr": 36, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 18, + "WTR_M": 18, "WTR_S": 5, "RFC1_slr": 351, "RFC2_slr": 234, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json index ee642481..411f7e07 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 10, "CCD_L_WR_slr": 40, "CCD_L_WR2_slr": 20, + "CCD_M_slr": 10, + "CCD_M_WR_slr": 40, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 20, + "WTR_M": 20, "WTR_S": 5, "RFC1_slr": 390, "RFC2_slr": 260, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json index 9c20c24e..9f270893 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 11, "CCD_L_WR_slr": 44, "CCD_L_WR2_slr": 22, + "CCD_M_slr": 11, + "CCD_M_WR_slr": 44, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 22, + "WTR_M": 22, "WTR_S": 6, "RFC1_slr": 429, "RFC2_slr": 286, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json index 3e01074e..b2ee9f4c 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 12, "CCD_L_WR_slr": 48, "CCD_L_WR2_slr": 24, + "CCD_M_slr": 12, + "CCD_M_WR_slr": 48, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 24, + "WTR_M": 24, "WTR_S": 6, "RFC1_slr": 468, "RFC2_slr": 312, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json index a0334a70..f6195751 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 13, "CCD_L_WR_slr": 52, "CCD_L_WR2_slr": 26, + "CCD_M_slr": 13, + "CCD_M_WR_slr": 52, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 26, + "WTR_M": 26, "WTR_S": 7, "RFC1_slr": 507, "RFC2_slr": 338, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json index cbd646be..dac8025d 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 14, "CCD_L_WR_slr": 56, "CCD_L_WR2_slr": 28, + "CCD_M_slr": 14, + "CCD_M_WR_slr": 56, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 28, + "WTR_M": 28, "WTR_S": 7, "RFC1_slr": 546, "RFC2_slr": 364, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json index 3cda8802..a916a36b 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 15, "CCD_L_WR_slr": 60, "CCD_L_WR2_slr": 30, + "CCD_M_slr": 15, + "CCD_M_WR_slr": 60, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 30, + "WTR_M": 30, "WTR_S": 8, "RFC1_slr": 585, "RFC2_slr": 390, diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json index 66cf4a2e..3cd3e234 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 16, "CCD_L_WR_slr": 64, "CCD_L_WR2_slr": 32, + "CCD_M_slr": 16, + "CCD_M_WR_slr": 64, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 32, + "WTR_M": 32, "WTR_S": 8, "RFC1_slr": 624, "RFC2_slr": 416, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json index 26a82afa..dd7baaf9 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 9, "CCD_L_WR_slr": 36, "CCD_L_WR2_slr": 18, + "CCD_M_slr": 9, + "CCD_M_WR_slr": 36, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 18, + "WTR_M": 18, "WTR_S": 5, "RFC1_slr": 351, "RFC2_slr": 234, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json index d518b7e8..c7f182eb 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 10, "CCD_L_WR_slr": 40, "CCD_L_WR2_slr": 20, + "CCD_M_slr": 10, + "CCD_M_WR_slr": 40, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 20, + "WTR_M": 20, "WTR_S": 5, "RFC1_slr": 390, "RFC2_slr": 260, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json index b7933630..fe7878e2 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 11, "CCD_L_WR_slr": 44, "CCD_L_WR2_slr": 22, + "CCD_M_slr": 11, + "CCD_M_WR_slr": 44, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 22, + "WTR_M": 22, "WTR_S": 6, "RFC1_slr": 429, "RFC2_slr": 286, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json index 3dc97958..c9b2f126 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 12, "CCD_L_WR_slr": 48, "CCD_L_WR2_slr": 24, + "CCD_M_slr": 12, + "CCD_M_WR_slr": 48, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 24, + "WTR_M": 24, "WTR_S": 6, "RFC1_slr": 468, "RFC2_slr": 312, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json index 7688520c..85b13eee 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 13, "CCD_L_WR_slr": 52, "CCD_L_WR2_slr": 26, + "CCD_M_slr": 13, + "CCD_M_WR_slr": 52, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 26, + "WTR_M": 26, "WTR_S": 7, "RFC1_slr": 507, "RFC2_slr": 338, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json index d9f181df..09418ff4 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 14, "CCD_L_WR_slr": 56, "CCD_L_WR2_slr": 28, + "CCD_M_slr": 14, + "CCD_M_WR_slr": 56, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 28, + "WTR_M": 28, "WTR_S": 7, "RFC1_slr": 546, "RFC2_slr": 364, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json index a14606bd..420e23a5 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 15, "CCD_L_WR_slr": 60, "CCD_L_WR2_slr": 30, + "CCD_M_slr": 15, + "CCD_M_WR_slr": 60, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 30, + "WTR_M": 30, "WTR_S": 8, "RFC1_slr": 585, "RFC2_slr": 390, diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json index 65d465fb..c8d3f989 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 16, "CCD_L_WR_slr": 64, "CCD_L_WR2_slr": 32, + "CCD_M_slr": 16, + "CCD_M_WR_slr": 64, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +52,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 32, + "WTR_M": 32, "WTR_S": 8, "RFC1_slr": 624, "RFC2_slr": 416, diff --git a/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json b/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json index b8b0fd2a..caa01d4c 100644 --- a/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json @@ -39,6 +39,8 @@ "CCD_L_slr": 8, "CCD_L_WR_slr": 32, "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 8, @@ -49,7 +51,8 @@ "RRD_dlr": 4, "FAW_slr": 32, "FAW_dlr": 16, - "WTR_L": 16, + "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, "RFC1_slr": 312, "RFC2_slr": 208, From 507c1d32d665e2559fdaf2b43d57383627837a42 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 12 Apr 2023 09:40:18 +0200 Subject: [PATCH 4/5] Update tCCD_L_WR, tCCD_L_WR2 and tCCD_M_WR timings in DDR5 timing checker --- .../controller/checker/CheckerDDR5.cpp | 108 +++++++++--------- 1 file changed, 56 insertions(+), 52 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index 0eb80250..d2efee43 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -181,12 +181,8 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) + if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_slr); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalRank.ID()]; @@ -288,15 +284,6 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommandStart != sc_max_time()) - { - if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tBURST16); - else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); - } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; if (lastCommandStart != sc_max_time()) { @@ -446,46 +433,47 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != sc_max_time()) + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW { - if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != sc_max_time()) { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + { earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); - } - else - { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + } + else + { earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + } + } + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; + if (lastCommandStart != lastScheduledByCommandAndBank[Command::WR][bank.ID()]) // different bank + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); + } + else + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); + } } } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) + else // no RMW { - if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) { - if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) + { earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); - } - else - { - if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW + } + else + { earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); - } - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - { - if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32) - { - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); - } - else - { - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); + } } } @@ -521,18 +509,34 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommandStart != sc_max_time()) + if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW { - if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR_slr); + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); + } + else + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); + } } - else + } + else // no RMW + { + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; + if (lastCommandStart != sc_max_time()) { - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); + } + else + { + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); + } } } From 5f1c74790bd4ba36aa3e360856257491750daa56 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Apr 2023 13:45:44 +0000 Subject: [PATCH 5/5] Remove duplicate checks in DDR5 checker. --- .../controller/checker/CheckerDDR5.cpp | 28 ------------------- 1 file changed, 28 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index d2efee43..4c6d8463 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -540,34 +540,6 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - { - if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) - { - if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_L_WR2_slr); - } - else - { - if (!(burstLength == 16 && memSpec->bitWidth == 4)) // no RMW - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); - } - } - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()]; - if (lastCommandStart != sc_max_time()) - { - if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32) - { - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tCCD_M_WR_slr); - } - else - { - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_M_WR_slr); - } - } - lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalRank.ID()]; if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr);