Implement cache into checker.

src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp

@@ -71,6 +71,12 @@ CheckerDDR4::CheckerDDR4(const Configuration& config)
 
 sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
 {
+    if (auto hit = cache.find(&payload); hit != cache.end())
+    {
+        if (hit->second.first == command)
+            return hit->second.second;
+    }
+
     Rank rank = ControllerExtension::getRank(payload);
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
@@ -454,6 +460,8 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic
     if (lastCommandOnBus != sc_max_time())
         earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
 
+    cache.insert_or_assign(&payload, std::pair<Command, sc_time>{command, earliestTimeToStart});
+
     return earliestTimeToStart;
 }
 
@@ -478,4 +486,6 @@ void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload)
             last4Activates[rank.ID()].pop();
         last4Activates[rank.ID()].push(sc_time_stamp());
     }
+
+    cache.clear();
 }

src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h

@@ -41,6 +41,8 @@
 
 #include <queue>
 #include <vector>
+#include <unordered_map>
+#include <utility>
 
 class CheckerDDR4 final : public CheckerIF
 {
@@ -73,6 +75,8 @@ private:
     sc_core::sc_time tRDPDEN;
     sc_core::sc_time tWRPDEN;
     sc_core::sc_time tWRAPDEN;
+
+    mutable std::unordered_map<const tlm::tlm_generic_payload*, std::pair<Command, sc_core::sc_time>> cache;
 };
 
 #endif // CHECKERDDR4_H