d392d0ab98
Write GeneralInfo table at the beginning
...
and do not include information in it that is only known at the end of
the simulation. These can trivially be calculated by the trace itself
and would be redundant information regardless.
The TraceAnalyzer gets the number of transactions and the length of
the trace by additional SQL queries.
This enables us to inspect traces of simulations that were aborted
without finishing cleanlywithout finishing cleanly.
2023-08-09 11:55:10 +02:00
a064f46413
Fix includes that cause build errors on some platforms
2023-08-03 15:04:39 +02:00
24654be952
Fix a timing issue in the traffic initiator
...
When the generator clock did not match the memory clock,
the generator always created a constant delay to the
next transaction.
This is not correct as due to rounding, the delay should be
one cycle more or less depending on the current simulation time.
2023-07-27 11:02:45 +02:00
085bfbd8de
Don't create log file when debug is not enabled
2023-07-21 09:39:52 +02:00
14ecc64ed0
Introduce Simulator class
2023-07-14 14:31:03 +02:00
Lukas Steiner
12dcbfd917
Use scoped enums for DRAM types.
2023-06-30 15:49:41 +02:00
Lukas Steiner
4e0891affb
Inherit privately from std::vector.
2023-06-26 16:32:39 +02:00
Lukas Steiner
413921f420
Minor formatting.
2023-06-22 10:19:34 +02:00
Lukas Steiner
c833471480
Use type safe index vectors in remaining controller.
2023-06-21 14:51:15 +02:00
Lukas Steiner
ba3f367676
Use type safe index vectors in timing checkers (2/2).
2023-06-21 12:59:26 +02:00
Lukas Steiner
d045af9d16
Use type safe index vectors in timing checkers (1).
2023-06-20 13:54:36 +02:00
Lukas Steiner
f3f9f9e8cd
Merge branch 'bug/stl_exceptions' into 'develop'
...
Add checks for empty trace and catch conversion exceptions.
See merge request ems/astdm/modeling.dram/dram.sys.5!30
2023-06-15 14:45:09 +00:00
Lukas Steiner
6e582907c0
Add checks for empty trace and catch conversion exceptions.
2023-06-15 11:32:51 +02:00
20f4f111ac
Align next request to initiator clock period
2023-06-15 10:59:29 +02:00
Lukas Steiner
ec731888a3
Remove check to issue first transaction at zero time.
2023-06-12 10:29:25 +02:00
55bbaf632d
Fix incorrect copyright disclaimer in Cache
2023-06-09 11:29:35 +02:00
3ce54b8faa
Fix readability-misleading-indentation warnings
2023-06-09 11:29:35 +02:00
32e828d254
Fix cppcoreguidelines-special-member-functions warnings
2023-06-09 11:29:35 +02:00
a9759f51fa
Enable warnings in dev preset and fix them
2023-06-09 11:29:15 +02:00
ad96e3ba14
Apply default clang-tidy fixes
2023-06-09 11:29:12 +02:00
2d590fda0d
Apply clang-tidy readability-named-parameter fixes
2023-06-09 11:17:57 +02:00
5d8d7c197e
Apply clang-tidy readability-* fixes
2023-06-09 11:17:57 +02:00
8bac84577f
Apply clang-tidy modernize-* fixes
2023-06-09 11:17:57 +02:00
79a54f11f6
Apply clang-tidy modernize-use-* fixes
2023-06-09 11:17:57 +02:00
77decb70ec
Apply clang-tidy modernize-use-nodiscard fixes
2023-06-09 11:17:57 +02:00
Lukas Steiner
71172f9545
Remove old files, move pct to extensions.
2023-05-26 15:39:06 +02:00
Lukas Steiner
20f6aae787
Replace tabs with whitespaces.
2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02
Update TUK to RPTU.
2023-05-25 15:15:52 +02:00
Lukas Steiner
4212e55f6c
Set cmake defaults, replace TUK with RPTU.
2023-05-23 16:47:03 +02:00
Lukas Steiner
93aecc3555
Merge branch 'gem5_instructions' into 'develop'
...
Add instructions for the new gem5 integration
See merge request ems/astdm/modeling.dram/dram.sys.5!23
2023-05-23 13:12:07 +00:00
Lukas Steiner
e389474139
Remove deprecated gem5 files.
2023-05-23 14:53:06 +02:00
b2fd6f2a84
Add instructions for the new gem5 integration
2023-05-22 12:17:59 +02:00
69cd04c448
Namespace the complete DRAMSys library
2023-05-17 11:42:00 +02:00
Lukas Steiner
58d486fb82
Merge branch 'work/hbm_rfm_fixes' into 'develop'
...
HBM and RFM fixes
See merge request ems/astdm/modeling.dram/dram.sys.5!17
2023-04-26 08:36:08 +00:00
fa88b34052
Refactor deserilization of RefreshPolicyType and remove McConfig.cpp
2023-04-24 09:34:50 +02:00
44a4d71635
Fix HBM pseudochannels not respeced in AddressDecoder
2023-04-21 11:12:21 +02:00
85f944fe58
Rename RAACDR to RAADEC
2023-04-21 11:10:09 +02:00
Lukas Steiner
7c0198cf21
Change default simulation file back to DDR4.
2023-04-20 10:38:33 +02:00
0814aa0cf1
Fix DatabaseRecording and SimulationProgressBar fields in SimConfig
2023-04-14 14:04:31 +02:00
Lukas Steiner
9a1443835d
Merge branch 'develop' into wip/unit_test_preps
...
# Conflicts:
# extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
2023-04-14 11:35:32 +02:00
Lukas Steiner
f844449d50
Remove empty cpp files.
2023-04-14 11:21:36 +02:00
Lukas Steiner
9b31fef555
Use local copies of sc_max_time() instead of calling the function.
2023-04-14 10:03:59 +02:00
Lukas Steiner
9115845862
Add common interface for BM, RM and PDM (2).
2023-04-13 16:10:59 +02:00
Lukas Steiner
7c33d48398
Add common interface for BM, RM and PDM.
2023-04-13 16:09:00 +02:00
b343ea821f
Refactor Configuration and add warnings when invalid values are provided
2023-04-13 11:21:37 +02:00
8f6e55f9fa
Enable StoreMode in new simulator and some refactoring
2023-04-13 11:21:36 +02:00
1f161b412f
Update documentation
2023-04-13 11:21:36 +02:00
56d43ac1d4
Remove dead function in RequestIssuer
2023-04-13 11:21:36 +02:00
3cd6396207
Add "dataAlignment" field for random traffic generators
2023-04-13 11:21:36 +02:00
15075c3be0
Use predefined resource directory if none is specified
2023-04-13 11:21:36 +02:00
