Fix a timing issue in the traffic initiator

When the generator clock did not match the memory clock,
the generator always created a constant delay to the
next transaction.

This is not correct as due to rounding, the delay should be
one cycle more or less depending on the current simulation time.

src/simulator/simulator/request/RequestIssuer.cpp

@@ -81,13 +81,21 @@ void RequestIssuer::sendNextRequest()
     tlm::tlm_phase phase = tlm::BEGIN_REQ;
     sc_core::sc_time delay = request.delay;
 
-    // Align to next clock
-    if (delay < clkPeriod && transactionsSent != 0)
+    sc_core::sc_time sendingTime = sc_core::sc_time_stamp() + delay;
+
+    bool needsOffset = (sendingTime % clkPeriod) != sc_core::SC_ZERO_TIME;
+    if (needsOffset)
     {
-        delay = delay + clkPeriod;
-        delay -= delay % clkPeriod;
+        sendingTime += clkPeriod;
+        sendingTime -= sendingTime % clkPeriod;
     }
 
+    if (sendingTime == lastEndRequest)
+    {
+        sendingTime += clkPeriod;
+    }
+
+    delay = sendingTime - sc_core::sc_time_stamp();
     iSocket->nb_transport_fw(payload, phase, delay);
 
     if (request.command == Request::Command::Read)
@@ -116,6 +124,8 @@ void RequestIssuer::peqCallback(tlm::tlm_generic_payload &payload, const tlm::tl
 {
     if (phase == tlm::END_REQ)
     {
+        lastEndRequest = sc_core::sc_time_stamp();
+
         if (nextRequestSendable())
             sendNextRequest();
         else

src/simulator/simulator/request/RequestIssuer.h

@@ -71,6 +71,7 @@ private:
 
     uint64_t transactionsSent = 0;
     uint64_t transactionsReceived = 0;
+    sc_core::sc_time lastEndRequest = sc_core::sc_max_time();
 
     unsigned int pendingReadRequests = 0;
     unsigned int pendingWriteRequests = 0;